DETAILED ACTION
Response to Amendment
This action is responsive to the amendment filed on 8/11/2026. Claims 1-28 are pending and have been examined. Claims 1, 5, 8, 12, 15, 19, 22-23 and 25-26 have been amended.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do use the word “means,” and are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “means for receiving”, “means for determining”, “means for transforming”, “means for generating”, “means for unrolling” and “means for replacing” in claims 15-16 and 18-19. The specification does not appear to provide sufficient structure for each of the recited means. Instead, paragraphs [0084-0085] disclose that each of the means can be hardware such as a CPU or software but has provided no specific structure for each of the individual means nor any specific algorithm applied to the CPU to generate the specific means. (See MPEP 2181(II)(B) “…To claim a means for performing a specific computer-implemented function and then to disclose only a general purpose computer as the structure designed to perform that function amounts to pure functional claiming…Mere reference to a general purpose computer with appropriate programming without providing an explanation of the appropriate programming, or simply reciting "software" without providing detail about the means to accomplish a specific software function, would not be an adequate disclosure of the corresponding structure to satisfy the requirements of 35 U.S.C. 112(b) or pre-AIA 35 U.S.C. 112, second paragraph.”)
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
6. Claims 15-21 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
7. Claims 15-16 and 18-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as claims 15-16 and 18-19 invoke 35 U.S.C. 112(f) but the written description fails to disclose each corresponding structure, material, or acts for the claimed functions. See claim construction above (e.g. the written description fails to disclose sufficient structure for each of the recited means.)
Claims 17 and 20-21 are dependent upon one or more claims above and therefore are rejected for including the deficiencies of one or more claims above.
8. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
9. Claims 1-28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regard to claim 1, line 4 stating “the loop order aligning an input data layout and an output data layout with a loop index” lacks clarity. The limitation lacks clarity because it is unclear if “aligning” as claimed means (1) that the sequence of loop indices is the same as the sequence of dimensions in the input and output layouts, (2) that particular dimensions of input and output layouts have a same loop index, (3) the sequence of loop indices in the loop order provide contiguous/sequential access of data in both the input and output data layout or something else?
Claims 8, 15 and 22 are similarly rejected for the same reasons as claim 1 above.
Claims 15-16 and 18-19 invoke 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth
paragraph. However, the written description fails to disclose the corresponding
structure, material, or acts for the claimed functions. For purposes of examination the examiner will interpret each means to be steps performed by a processor. As the specification does not provide adequate disclosure, the claim boundaries are not known, thus rendering the claim indefinite. Applicant may: (a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph; or (b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the claimed function, without introducing any new matter (35 U.S.C. 132(a)). If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function applicant should clarify the record by either: (a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or(b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181.
Claims 2-7, 9-14, 16-21 and 23-28 are dependent upon one or more claims above and therefore are rejected for including the deficiencies of one or more claims above.
Claim Rejections - 35 USC § 102
10. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
11. Claim(s) 1, 8, 15 and 22 are is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rahavan, PGPUB No. 2008/0263530.
In regards to claim 8, Rahavan discloses An apparatus ([0050]: computation engine), comprising: at least one memory; and at least one processor coupled to the at least one memory ([0050-0052]: wherein engine comprises memory and a processor coupled to the memory) the at least one processor is configured to: receive a first program code including one or more nested loops ([0119-0128]: wherein program code with one or more nested loops are received) determine a loop order for the one or more nested loops, the loop order aligning an input data layout and an output data layout with a loop index of the one or more nested loops ([0120-0137]: wherein it is determined that the one or more loop nest are to have their loops interchanged, thus an order of the loops for interchanging is determined (e.g., nested loops first outer for loop with i as index is interchanged with second inner for loop with j as index) . Wherein it is determined that interchanging the order of the loops would cause aligning input and output data layouts of arrays (A, B, and/or D) to column major layouts with loop index (i) because i changes in the fastest-moving inner loop, thus the index ensures the code achieves layout locality which sequentially accesses data (see also [0085-00886 and 0094] aligning access patterns based on transformation (e.g. interchange) and discussing layout locality occurs from consecutive iterations of innermost loop to access consecutive data elements) transform the one or more nested loops based on the loop order ([0129-0137]: wherein the code is transformed with interchanged nested loops based on interchanging loop order) and generate a second program code based on the transformed one or more nested loops. ([0129-0137]: wherein generated code based on loop interchange is illustrated)
Claim 1 is similarly rejected on the same basis as claim 8 above as claim 1 is the method corresponding to the apparatus of claim 8 above.
Claim 15 is similarly rejected on the same basis as claim 8 above.
Claim 22 is similarly rejected on the same basis as claim 8 above as claim 22 is the non-transitory medium corresponding to the apparatus of claim 8 above. (see [0050-0052]: for discussion of medium)
Claim Rejections - 35 USC § 103
12. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
13. Claim(s) 1-3, 6-10, 13-17, 20-24 and 27-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over NPL reference “Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays” hereby referred to as Heirdorn, and further in view of Rahavan, PGPUB No. 2008/0263530.
In regards to claim 8, Heirdorn discloses An apparatus (See page 542: TCPA accelerator (Fig. 1a)) comprising: a memory (See page 542: memory (Fig. 1a)) and at least one processor coupled to the memory (See page 542: wherein a processor is coupled to memory (Fig. 1a)) the at least one processor is configured: to receive a first program code including one or more nested loops (see page 542, “…TCPAs are thus particularly suited to accelerate computationally expensive nested loop programs that exhibit a high degree of parallelism such as CNNs” thus processor of TCPAs receive a nested loop program.; see page 546, section 3.3 (algorithm 1)) to determine a loop order for the one or more nested loops (see page 547: “… Apart from moving the loop with iterator 𝑚 to the innermost position, also iterator 𝑛 has been permuted. Another advantage of this schedule is the potential of reusing input data when processing the same input region for the total of 𝑀 filters… by moving the spatial feature map loops (𝑟, 𝑐, 𝑘) to the
outer and the loops which iterate over the different features and filters (𝑛, 𝑚) to the innermost positions…”. Wherein loop order for loop permutation is determined for one or more nested loops. (also see page 546, algorithm 1))
to transform the one or more nested loops based on the loop order (page 547: “…This may be achieved by loop permutation, resulting in the transformed code shown in Algorithm 2… after loop permutation, by moving the spatial feature map loops (𝑟, 𝑐, 𝑘) to the outer and the loops which iterate over the different features and filters (𝑛, 𝑚) to the innermost positions…” wherein the one or more nested loops are transformed based on the loop order) and to generate a second program code based on the transformed one or more nested loops. (page 547: “…This may be achieved by loop permutation, resulting in the transformed code shown in Algorithm 2… after loop permutation, by moving the spatial feature map loops (𝑟, 𝑐, 𝑘) to the outer and the loops which iterate over the different features and filters (𝑛, 𝑚) to the innermost positions…”. Page 549: “…thus generating one program …” wherein program is generated based on transformed one or more nested loops)
Heirdorn does not disclose the loop order aligning an input data layout and an output data layout with a loop index of one or more nested loops.
Rahavan discloses the loop order aligning an input data layout and an output data layout with a loop index of the one or more nested loops ([0120-0137]: wherein it is determined that the one or more loop nest are to have their loops interchanged, thus an order of the loops for interchanging is determined (e.g., nested loops first outer for loop with i as index is interchanged with second inner for loop with j as index) . Wherein it is determined that interchanging the order of the loops would cause aligning input and output data layouts of arrays (A, B, and/or D) to column major layouts with loop index (i) because i changes in the fastest-moving inner loop, thus the index ensures the code achieves layout locality which sequentially accesses data (see also [0085-00886 and 0094] aligning access patterns based on transformation (e.g. interchange) and discussing layout locality occurs from consecutive iterations of innermost loop to access consecutive data elements)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the loop ordering (loop permuting) as taught in Heirdorn to align input and output data layouts as the loop ordering in Rahavan. It would have been obvious to one of ordinary skill in the art because aligning data layouts based on loop ordering can improve access/layout locality of arrays used in nested loops to optimize nested loop code (Rahavan [0077-0079, 0094, 0129 and 0138-0142]).
Claim 1 is similarly rejected on the same basis as claim 8 above as claim 1 is the method corresponding to the apparatus of claim 8 above.
Claim 15 is similarly rejected on the same basis as claim 8 above.
Claim 22 is similarly rejected on the same basis as claim 8 above as claim 22 is the non-transitory medium corresponding to the apparatus of claim 8 above. (see Rahavan [0050-0052]: for discussion of medium)
In regard to claim 9, the combination of Heirdorn and Rahavan discloses The apparatus of claim 8 (see rejection of claim 8 above) in which the at least one processor is further configured to unroll at least one loop of the one or more nested loops. (Heirdorn: page 548 “…For that, the inner loops (𝑑, 𝑝) are unrolled (Algorithm 3).”)
Claim 2 is similarly rejected on the same basis as claim 9 above as claim 2 is the method corresponding to the apparatus of claim 9 above.
Claim 16 is similarly rejected on the same basis as claim 9 above.
Claim 23 is similarly rejected on the same basis as claim 9 above as claim 23 is the non-transitory medium corresponding to the apparatus of claim 9 above.
In regard to claim 10, the combination of Heirdorn and Rahavan discloses The apparatus of claim 9 (see rejection of claim 9 above) in which the at least one loop includes an output loop. (Heirdorn: page 548 “…For that, the inner loops (𝑑, 𝑝) are unrolled (Algorithm 3).” And see algorithm 3, line 6 comment stating “…number of output feature maps” which indicates one of the loops unrolled includes an output feature map loop (e.g. an output loop))
Claim 3 is similarly rejected on the same basis as claim 10 above as claim 3 is the method corresponding to the apparatus of claim 10 above.
Claim 17 is similarly rejected on the same basis as claim 10 above.
Claim 24 is similarly rejected on the same basis as claim 10 above as claim 24 is the non-transitory medium corresponding to the apparatus of claim 10 above.
In regard to claim 13, the combination of Heirdorn and Rahavan discloses The apparatus of claim 8 (see rejection of claim 8 above) in which the first program code is configured to convolve an input feature map array with a kernel array to produce an output feature map array. (page 546, section 3.3 “…processing of the CNN layers (if implemented in parallel), the data dependencies between successive layer computations need to be carefully examined. Algorithm 1 shows the pseudocode of a standard sequential loop nest for the computations of one layer according to Eq. (1). Algorithm 1. Pseudocode for a standard sequential convolution derived from Eq. (1) …” (also see page 544, Fig. 2 and section 3.1 for details of convolution performed using input feature map array, weight kernel array and output feature map array))
Claim 6 is similarly rejected on the same basis as claim 13 above as claim 6 is the method corresponding to the apparatus of claim 13 above.
Claim 20 is similarly rejected on the same basis as claim 13 above.
Claim 27 is similarly rejected on the same basis as claim 13 above as claim 27 is the non-transitory medium corresponding to the apparatus of claim 13 above.
In regard to claim 14, the combination of Heirdorn and Rahavan discloses The apparatus of claim 8 (see rejection of claim 8 above) in which the second program code is configured to implement a stride-1 reference pattern for reading the input feature map array and writing the output feature map array. (Heirdorn: page 544: “…With stride size 𝑆𝑖, the step width with that the filter is moved over the feature map. For this formula, a pseudo-code is visualized by Algorithm 1. Equation (1) equally describes also pooling layers and the fully connected layers. In case of a fully-connected layer, the computation in Eq. (1) simplifies to the special case
𝑆𝑖 = 𝐾𝑖 = 𝑅𝑖 = 𝐶𝑖 = 1.” Page 545: “…stride of 𝑆𝑖 = 1”: see pages 546-548: wherein each algorithm would use Si=1 for the programs to process convolution, thus an input feature map and output feature map are read and written using a stride-1 reference pattern)
Claim 7 is similarly rejected on the same basis as claim 14 above as claim 7 is the method corresponding to the apparatus of claim 14 above.
Claim 21 is similarly rejected on the same basis as claim 14 above.
Claim 28 is similarly rejected on the same basis as claim 14 above as claim 28 is the non-transitory medium corresponding to the apparatus of claim 14 above.
14. Claim(s) 4-5, 11-12, 18-19 and 25-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over NPL reference “Efficient Mapping of CNNs onto Tightly Coupled Processor Arrays” hereby referred to as Heirdorn, Rahavan, PGPUB No. 2008/0263530 and further in view of NPL reference, “Increasing the Applicability of Scalar Replacement” hereby referred to as So.
In regard to claim 11, the combination of Heirdorn and Rahavan disclose The apparatus of claim 8 (see rejection of claim 8 above) in which the at least one processor (Heirdorn: See page 542: wherein a processor is disclosed (Fig. 1a))
one or more array elements for computing an output feature in an input channel from a memory unit (Heirdorn: page 544, see Fig.2 and section 3.1: wherein convolution layer calculation involves one or more array elements as shown in Fig. 2 for computing output features. See page 547, section 4 and Fig. 5 which illustrates that convolution layer outputs are inputs to a next layer, and therefore an output feature in an input channel of a next convolution layer is disclosed (also see page 542, Figs. 1(a-b) for further details memory and array elements))
The combination of Heirdorn and Rahavan does not disclose processor configured to replace at least one instruction for retrieving a value of one or more array elements for computing from a memory unit for with an instruction for storing a scalar value corresponding to the value of the one or more array elements in a local register.
So discloses processor (page 186, wherein a FPGA is disclosed) configured
to replace at least one instruction for retrieving a value of one or more array elements for computing from a memory unit with an instruction for storing a scalar value corresponding to the value of the one or more array elements in a local register. (Pages 186: “…One specific code transformation for exploiting data reuse is scalar replacement which replaces array references with scalar temporaries. As such, two references that access the same memory location will instead use the scalar temporaries. This idea can be extended to exploit register reuse by replacing all but the final write of a datum with writes to a register… Increases the candidates for reuse both by exploiting reuse across multiple loops in a nest (not just the innermost loop) and by removing redundant write memory accesses (in addition to redundant reads)”. Wherein read access instructions for retrieving data from array elements from memory are replaced with an instruction for storing scalar values to a register (See Figs. 1a and 3a) (Also pages 189-195 and 200, see sections 3 and 7 for details for further details on scalar replacement))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the processor of Heirdorn and Rahavan which performs nested loops to use scalar replacement in nested loops as taught in So. It would have been obvious to one of ordinary skill in the art because performing scalar replacement eliminates redundant memory accesses and exploits data reuse across multiple loops in nested loops (So, see sections 1 and 7 on pages 185-186 and 200).
Claim 4 is similarly rejected on the same basis as claim 11 above as claim 4 is the method corresponding to the apparatus of claim 11 above.
Claim 18 is similarly rejected on the same basis as claim 11 above.
Claim 25 is similarly rejected on the same basis as claim 11 above as claim 25 is the non-transitory medium corresponding to the apparatus of claim 11 above.
In regard to claim 12, the combination of Heirdorn and Rahavan disclose The apparatus of claim 8 (see rejection of claim 8 above) in which the at least one processor (Heirdorn: See page 542: wherein a processor is disclosed (Fig. 1a))
one or more array elements for computing an output feature in an output channel to a memory unit (Heirdorn: page 544, see Fig. 2 and section 3.1: wherein convolution layer calculation involves one or more array elements as shown in Fig. 2 for computing output features in an output channel of a layer. See page 547, section 4 and Fig. 5 which illustrates that convolution layer outputs and therefore an output feature in an output channel is disclosed (also see page 542, Figs. 1(a-b) for further details memory and array elements))
The combination of Heirdorn and Rahavan does not disclose processor configured to replace at least one instruction for writing a value of one or more array elements for computing to a memory unit with an instruction for storing the value in a local register.
So discloses processor (page 186, wherein a FPGA is disclosed) configured
to replace at least one instruction for writing a value of one or more array elements for computing to a memory unit with an instruction for storing the value in a local register. (Pages 186: “…One specific code transformation for exploiting data reuse is scalar replacement which replaces array references with scalar temporaries. As such, two references that access the same memory location will instead use the scalar temporaries. This idea can be extended to exploit register reuse by replacing all but the final write of a datum with writes to a register… Increases the candidates for reuse both by exploiting reuse across multiple loops in a nest (not just the innermost loop) and by removing redundant write memory accesses (in addition to redundant reads)”. Wherein write access instructions for writing data to array elements in memory are replaced with an instruction for storing scalar values to a register (See Figs. 1a and 3a) (Also pages 189-195 and 200, see sections 3 and 7 for details for further details on scalar replacement))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the processor of Heirdorn and Rahavan which performs nested loops to use scalar replacement in nested loops as taught in So. It would have been obvious to one of ordinary skill in the art because performing scalar replacement eliminates redundant memory accesses and exploits data reuse across multiple loops in nested loops (So, see sections 1 and 7 on pages 185-186 and 200).
Claim 5 is similarly rejected on the same basis as claim 12 above as claim 5 is the method corresponding to the apparatus of claim 12 above.
Claim 19 is similarly rejected on the same basis as claim 12 above.
Claim 26 is similarly rejected on the same basis as claim 12 above as claim 26 is the non-transitory medium corresponding to the apparatus of claim 12 above.
Response to Arguments
15. Applicant's arguments filed on 8/11/2026 with regards to the previous 35 USC 112(a-b) rejections have been fully considered but they are not persuasive. Therefore, the rejections are maintained.
16. Applicant argues the 35 USC 112 rejections, on pages 7-8 of the remarks in the substance that:
“Applicant respectfully traverses. The corresponding structure and the corresponding acts identified above appear in the specification as originally filed, for example, in paragraph 129 of the published specification. Reconsideration and withdrawal of the rejection of claims 15-21 are respectfully requested.
Claims 1-28 have been rejected under 35 U.S.C. § 112(b) as allegedly being indefinite for failing to particularly point out and distinctly claim the subject matter.
Claims 1, 5, 8, 12, 15, 19, 22 23, 25, and 26 have been amended. Applicant respectfully submits that the amendments overcome the rejections and add no new matter. Reconsideration and withdrawal of the rejections of claims 1-28 are respectfully requested.”
The applicant first argues that the specification paragraph [129] discloses the corresponding structure relative to the “means” in claims 15-21. However, the examiner respectfully disagrees because 129 states “the receiving means, determining means, transforming means and/or generating means may be the CPU 102, program memory associated with the CPU 102, DSP 106, fully connected layers 362, NPU 428 and or the routing connection processing unit 216 configured to perform the functions recited. In another configuration, the aforementioned means may be any module or any apparatus configured to perform the functions recited by the aforementioned means.” Thus, it appears applicant argues that the “means” performing each function is done by a CPU, software associated with CPU, DSP, layers of neural network, NPU and/or a routing connection processing unit. However, this is not persuasive because MPEP 2181(II)(B) states “… "a microprocessor can serve as structure for a computer-implemented function only where the claimed function is ‘coextensive’ with a microprocessor itself." …"‘[S]pecial programming’ includes any functionality that is not ‘coextensive’ with a microprocessor or general-purpose computer." EON Corp., 785 F.3d at 623, 114 USPQ2d at 1715 (citations omitted). "Examples of such coextensive functions are ‘receiving’ data, storing’ data, and ‘processing’ data—the only three functions on which the Katz court vacated the district court’s decision and remanded for the district court to determine whether disclosure of a microprocessor was sufficient." 785 F.3d at 622, 114 USPQ2d at 1714. Thus, "[a] microprocessor or general purpose computer lends sufficient structure only to basic functions of a microprocessor. All other computer-implemented functions require disclosure of an algorithm." Id., 114 USPQ2d at 1714”. At best, the only claimed means that paragraph 129 could provide structure for would be the “means for receiving” as it is a coextensive function within a CPU. However, the specification must provide an algorithm for all the other claimed means such as means for determining, means for transforming, means for generating and means for replacing as these functions are not coextensive. (Note: the applicant could remove the means plus function language from the claim or amend the “means” to “circuitry” as to overcome the rejections)
In addition, the applicant argues that the claims have been amended to overcome the previous 112(b) rejections. The examiner notes that the previous 112(b) rejection with regards to independent claim recitation of “aligning” remains unclear. The applicant has amended the limitation to state “…the loop order aligning an input data layout and an output data layout with a loop index of the one or more nested loops”, which remains unclear because the claim has not been amended to clarify what “aligning” means in the claimed invention. For example, it is unclear if “aligning” means the loop order causes the sequence of loop indices to be the same as the sequence of dimensions in the input and output layouts, (2) that particular dimensions of input and output layouts have a same loop index, (3) the sequence of loop indices in the loop order provide contiguous/sequential access of data in both the input and output data layout?
17. Applicant's arguments filed on 8/11/2026 have been fully considered but they are not persuasive. Thus, the previous 35 USC 102 and 103 rejections have been maintained.
18. Applicant argues the prior art rejections on pages 8-9 of the remarks in the substance that:
“Rahavan describes "loop-nests down the chain could be transformed easily to align their access pattern to the prefixed placements so that good layout locality may still be achieved." Rahavan also describes "The lesser constrained loop nest has more freedom, and so it will be easier to find a legal loop transformation that matches the access order of the arrays to the predefined data placement." Rahavan further states "If instead was started with Loop-Nest II, then a loop-interchange could be performed to improve access locality for C. This would mean that B's layout should be set to column-major for good layout locality in Loop-Nest II. Rahavan appears to suggest conversion of certain code. However, Rahavan fails to disclose "determining a loop order for the one or more nested loops, the loop order aligning an input data layout and an output data layout with a loop index of the one or more nested loops. “However, So like, Rahavan and Heirdorn, fails to disclose "determining a loop order for the one or more nested loops, the loop order aligning an input data layout and an output data layout with a loop index of the one or more nested loops."
The examiner respectfully disagrees with the applicants’ assertions above because Rahavan does disclose the current claim language under broadest reasonable interpretation. For example, Rahavan discloses determining if one or more nested loops should have their respective loops interchanged, thus a loop order is determined as to indicate what order the interchanged loops would be in. Further, Rahavan discloses code of the nested loops which includes input data layouts and output data layouts (see arrays A[i][j], B[i[j] and D[i][j] for example paragraphs [0130-0137]) which are all aligned to column major format to improve layout locality with a loop index (i) of one or more nested loops. Also, Rahavan paragraph [0085] states “In order to have layout locality, consecutive iterations of the innermost loop in {right arrow over (I)}'.sub.k access consecutive elements of A.sub.p”. Thus, by improving layout locality of input and output layouts of data arrays the innermost loop (e.g. loop index (i)) can access consecutive data elements of each of the arrays. Therefore, the determined loop order, based on the loop interchange, aligns input and output data layouts with an innermost loop index of the one or more nested loops.
Conclusion
19. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Doshi, USPAT No. 11,256,489 for teaching reordering iterations of a first inner loop of a nested loop as to increase cache memory hits
20. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
21. Any inquiry concerning this communication or earlier communications from the examiner should be directed to COURTNEY P SPANN whose telephone number is (571)431-0692. The examiner can normally be reached M-F, 9am-6pm, EST.
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/COURTNEY P SPANN/Primary Examiner, Art Unit 2183
