DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 02/01/2024 and 03/20/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 5-11, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ipek (US 2019/0188596) in view of Gupta (US 2004/0022332).
Regarding claim 1, Ipek teaches an apparatus (Fig. 3, Quantum communication apparatus shown; Paragraph 0071, single flux quantum (ERSFQ) technology), comprising: a routing network (Fig. 3, Mesh network routes data between ERSFQ nodes; Paragraph 0094, a mesh architecture connects processing nodes, each comprising a multithreaded ERSFQ processor, off-chip L2 cache implemented with MJJs, and main memory) to route packets between a set of sending devices and a set of receiving devices (Fig. 3, Plurality of processing nodes are split into groups that communicate read/write packets between each other and thus are sets of senders and receivers; Paragraph 0228, nodes will access their broadcast bus in a time multiplexed fashion when transmitting read and write requests. In some embodiments, a read or write request will comprise a preamble, followed by a node ID, plus a read or write request… Paragraph 0229, Nodes will be grouped into clusters that can communicate directly with each other, with a global router), wherein: one or more of the routing network, the set of sending devices, and the set of receiving devices are part of a superconducting device (Fig. 3, Network router and sending/receiving ERSFQ processor nodes are part of a superconductor; Paragraph 0154, described hereinabove new superconducting architectures for parallel applications using ERSFQ… Paragraph 0157, includes a system of compute nodes, each with processors and a supporting memory hierarchy, interconnected by a networking fabric to primary storage); and a scheduling module (Figs. 3-5, Processing node is a ERSFQ processor shown in Figure 3 containing a fetch unit with a thread selector shown in Figure 4 which comprises a round robin scheduling module (i.e. a scheduling module) shown in Figure 5; Paragraph 0094, processing nodes, each comprising a multithreaded ERSFQ processor… Paragraph 0096, processor comprises six major pipeline stages: fetch… Paragraph 0098, fetch unit includes a thread selector… the thread selection logic implements a simple, pseudo-round-robin policy) to interconnect different subsets of the set of sending devices to different subsets of the set of receiving devices based on a set of connection schedules (Fig. 5, Round robin scheduling module interconnects four different groups of sending/receiving threads (i.e. thread group 0-3, thread group 4-7, thread group 8-11, and thread group 12-15) implemented on processor nodes based on a round-robin order (i.e. round-robin arbitrates communications between groups of threads one after the other and thus is a set of connection schedules); Paragraph 0099, pseudo round-robin scheme which… divides the sixteen threads into four groups, and uses a four-bit shifter to select one of the groups in round-robin order), wherein the packets are routed between the different subsets of the set of sending devices and the different subsets of the set of receiving devices based on the set of connection schedules (Fig. 5, Round-robin scheduling routes the packets between the nodes based on the round-robin connection schedules; Paragraph 0228, nodes will access their broadcast bus in a time multiplexed fashion when transmitting read and write requests).
Ipek does not explicitly teach the apparatus comprising the set of sending devices and the set of receiving devices use a race logic architecture.
Gupta teaches the apparatus comprising the set of sending devices and the set of receiving devices use a race logic architecture (Figs. 2 and 24, ADC 120 in Figure 2 contains race arbitration logic shown in Figure 24; Paragraph 0131, ADC 120 is a so-called `race arbiter` circuit. A basic race arbiter circuit is shown in FIG. 24. A race arbiter determines the arrival of one signal with respect to another signal in time. In rapid single flux quantum (RSFQ) circuits).
Ipek and Gupta are analogous arts because they are in the same field of endeavor of controlling data communications in a superconducting quantum communication network.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ipek’s apparatus to incorporate the teachings of Gupta and include race logic arbitration between the receiving/sending processor nodes of Ipek.
One of ordinary skill in the art would be motivated to make the modifications in order to provide a universal data communication standard that can flexibly support multiple types of modulation and frequency bands (See Gupta: Paragraph 0042) which can improve efficiency and bandwidth use (See Gupta: Paragraphs 0045-0047).
Regarding claim 5, Ipek in view of Gupta teaches the apparatus of claim 1. Ipek teaches the apparatus comprising wherein the set of connection schedules rotate between the set of sending devices and the set of receiving devices in a round robin schedule (Fig. 5, Round-robin scheduling routes the packets between the nodes based on the round-robin connection schedules; Paragraph 0099, pseudo round-robin scheme which… divides the sixteen threads into four groups, and uses a four-bit shifter to select one of the groups in round-robin order).
Regarding claim 6, Ipek in view of Gupta teaches the apparatus of claim 1. Ipek teaches the apparatus comprising wherein: the scheduling module comprises a set of scheduling devices (Fig. 5, Round-robin scheduling module comprises multiple selectors (i.e. a set of scheduling devices)); and each scheduling device of the set of scheduling devices is associated with a respective subset of the routing network (Fig. 5, Each selector is associated with a subset of threads 0-3, 4-7, 8-11, and 12-15; Paragraph 0099, the first level, it divides the sixteen threads into four groups, and uses a four-bit shifter to select one of the groups in round-robin order. Within the selected group, one of the ready threads (i.e., the threads that are not stalled due to a full instruction buffer or an instruction cache miss) is selected using a priority encoder).
Regarding claim 7, Ipek in view of Gupta teaches the apparatus of claim 6. Ipek teaches the apparatus comprising wherein each scheduling device of the set of scheduling devices comprises a set of merging circuits and a set of toggle flip flop (TFF) circuits (Fig. 5, Selector merges inputs to be selected and comprises flip flops; Paragraph 0023, ERSFQ circuits includes an array of magnetic tunnel junction (MTJ) devices… Paragraph 0024, the MTJ devices are configured as T Flip-Flop Josephson junction (JJ) circuits… Paragraph 0185, multiplexers to be replaced by much more efficient mergers).
Regarding claim 8, Ipek in view of Gupta teaches the apparatus of claim 1. Ipek teaches the apparatus comprising wherein each routing device of the routing network comprises a nondestructive read out (NDRO) cell (Fig. 5, Nondestructive read out registers (NRDO) are shown; Paragraph 0019, A flush signal input terminal is coupled to a nondestructive read out (NDRO) register).
Regarding claim 9, Ipek in view of Gupta teaches the apparatus of claim 8. Ipek teaches the apparatus comprising wherein each NDRO cell is to generated a respective output based on one connection schedule of the set of connection schedules (Fig. 5, NRDO generates an output based on the round-robin selection of the thread group; Paragraph 0099, Within the selected group, one of the ready threads (i.e., the threads that are not stalled due to a full instruction buffer or an instruction cache miss) is selected using a priority encoder).
Regarding claim 10, Ipek in view of Gupta teaches the apparatus of claim 1. Ipek teaches the apparatus further comprising: one or more shift buffers coupled to one or more of the set of sending devices and the set of receiving devices, wherein the one or more shift buffers are configured to store the packets for a period of time (Fig. 5, Four-bit shifter is shown which FIFO buffers the read/write packets; Paragraph 0099, pseudo round-robin scheme which implements a two-level selection mechanism. In the first level, it divides the sixteen threads into four groups, and uses a four-bit shifter to select one of the groups in round-robin order… Paragraph 0100, the buffers that connect the decode stage to the fetch and register wheel access stages are implemented with a FIFO structure).
Regarding claim 11, Ipek teaches a system (Fig. 3, Quantum communication system shown; Paragraph 0071, single flux quantum (ERSFQ) technology), comprising: a set of sending devices to transmit packets (Fig. 3, Plurality of processing nodes are split into groups that communicate read/write packets between each other and thus are sets of senders and receivers; Paragraph 0228, nodes will access their broadcast bus in a time multiplexed fashion when transmitting read and write requests. In some embodiments, a read or write request will comprise a preamble, followed by a node ID, plus a read or write request… Paragraph 0229, Nodes will be grouped into clusters that can communicate directly with each other, with a global router); a set of receiving devices to receive the packets (Fig. 3, Processing nodes also receive packets; Paragraph 0228, Once a read or write request is received, the node will wait for any ongoing data transmissions to complete); a routing network to route the packets between the set of sending devices and the set of receiving devices (Fig. 3, Mesh network routes data between nodes; Paragraph 0094, a mesh architecture connects processing nodes, each comprising a multithreaded ERSFQ processor, off-chip L2 cache implemented with MJJs, and main memory), wherein: one or more of the routing network, the set of sending devices, and the set of receiving devices are part of a superconducting device (Fig. 3, Network router and sending/receiving processor nodes are part of a superconductor; Paragraph 0154, described hereinabove new superconducting architectures for parallel applications using ERSFQ… Paragraph 0157, includes a system of compute nodes, each with processors and a supporting memory hierarchy, interconnected by a networking fabric to primary storage); and a scheduling module to interconnect different subsets of the set of sending devices to different subsets of the set of receiving devices based on a set of connection schedules (Figs. 3-5, Processing node is a ERSFQ processor shown in Figure 3 containing a fetch unit with a thread selector shown in Figure 4 which comprises a round robin scheduling module (i.e. a scheduling module) shown in Figure 5; Paragraph 0094, processing nodes, each comprising a multithreaded ERSFQ processor… Paragraph 0096, processor comprises six major pipeline stages: fetch… Paragraph 0098, fetch unit includes a thread selector… the thread selection logic implements a simple, pseudo-round-robin policy), wherein the packets are routed between the different subsets of the set of sending devices and the different subsets of the set of receiving devices based on the set of connection schedules (Fig. 5, Round-robin scheduling routes the packets between the nodes based on the round-robin connection schedules; Paragraph 0228, nodes will access their broadcast bus in a time multiplexed fashion when transmitting read and write requests).
Ipek does not explicitly teach the system comprising the set of sending devices and the set of receiving devices use a race logic architecture.
Gupta teaches the system comprising the set of sending devices and the set of receiving devices use a race logic architecture (Figs. 2 and 24, ADC 120 in Figure 2 contains race arbitration logic shown in Figure 24; Paragraph 0131, ADC 120 is a so-called `race arbiter` circuit. A basic race arbiter circuit is shown in FIG. 24. A race arbiter determines the arrival of one signal with respect to another signal in time. In rapid single flux quantum (RSFQ) circuits digital "1" ("0") is represented by the presence (or absence) of data signal with respect to clock signal, where both data and clock are in the form of single flux quantum (SFQ) pulses).
Ipek and Gupta are analogous arts because they are in the same field of endeavor of controlling data communications in a superconducting quantum communication network.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ipek’s system to incorporate the teachings of Gupta and include race logic arbitration between the receiving/sending processor nodes of Ipek.
One of ordinary skill in the art would be motivated to make the modifications in order to provide a universal data communication standard that can flexibly support multiple types of modulation and frequency bands (See Gupta: Paragraph 0042) which can improve efficiency and bandwidth use (See Gupta: Paragraphs 0045-0047).
Regarding claim 15, Ipek in view of Gupta teaches the system of claim 11. Ipek teaches the system comprising wherein the set of connection schedules rotate between the set of sending devices and the set of receiving devices in a round robin schedule (Fig. 5, Round-robin scheduling routes the packets between the nodes based on the round-robin connection schedules; Paragraph 0099, pseudo round-robin scheme which… divides the sixteen threads into four groups, and uses a four-bit shifter to select one of the groups in round-robin order).
Regarding claim 16, Ipek in view of Gupta teaches the system of claim 11. Ipek teaches the system comprising wherein: the scheduling module comprises a set of scheduling devices (Fig. 5, Round-robin scheduling module comprises multiple selectors (i.e. a set of scheduling devices)); and each scheduling device of the set of scheduling devices is associated with a respective subset of the routing network (Fig. 5, Each selector is associated with a subset of threads 0-3, 4-7, 8-11, and 12-15; Paragraph 0099, the first level, it divides the sixteen threads into four groups, and uses a four-bit shifter to select one of the groups in round-robin order. Within the selected group, one of the ready threads (i.e., the threads that are not stalled due to a full instruction buffer or an instruction cache miss) is selected using a priority encoder).
Regarding claim 17, Ipek in view of Gupta teaches the system of claim 16. Ipek teaches the system comprising wherein each scheduling device of the set of scheduling devices comprises a set of merging circuits and a set of toggle flip flop (TFF) circuits (Fig. 5, Selector merges inputs to be selected and comprises flip flops; Paragraph 0023, ERSFQ circuits includes an array of magnetic tunnel junction (MTJ) devices… Paragraph 0024, the MTJ devices are configured as T Flip-Flop Josephson junction (JJ) circuits… Paragraph 0185, multiplexers to be replaced by much more efficient mergers).
Regarding claim 18, Ipek in view of Gupta teaches the system of claim 11. Ipek teaches the system comprising wherein each routing device of the routing network comprises a nondestructive read out (NDRO) cell (Fig. 5, Nondestructive read out registers (NRDO) are shown; Paragraph 0019, A flush signal input terminal is coupled to a nondestructive read out (NDRO) register).
Regarding claim 19, Ipek in view of Gupta teaches the system of claim 18. Ipek teaches the system comprising wherein each NDRO cell is to generated a respective output based on one connection schedule of the set of connection schedules (Fig. 5, NRDO generates an output based on the round-robin selection of the thread group; Paragraph 0099, Within the selected group, one of the ready threads (i.e., the threads that are not stalled due to a full instruction buffer or an instruction cache miss) is selected using a priority encoder).
Regarding claim 20, Ipek teaches a method (Fig. 3, Quantum communication method shown; Paragraph 0071, single flux quantum (ERSFQ) technology), comprising: obtaining a set of schedules (Fig. 5, Round-robin scheduling algorithm used to obtain a schedule to route the packets between the nodes; Paragraph 0228, nodes will access their broadcast bus in a time multiplexed fashion when transmitting read and write requests… Paragraph 0185, a simple round robin policy selects one of the groups each cycle. Within the selected group, a low-radix priority encoder can pick the highest priority thread) for a routing network (Fig. 3, Mesh network routes data between nodes; Paragraph 0094, a mesh architecture connects processing nodes, each comprising a multithreaded ERSFQ processor, off-chip L2 cache implemented with MJJs, and main memory) to route packets between a set of sending devices and a set of receiving devices (Fig. 3, Plurality of processing nodes are split into groups that communicate read/write packets between each other and thus are sets of senders and receivers; Paragraph 0228, nodes will access their broadcast bus in a time multiplexed fashion when transmitting read and write requests. In some embodiments, a read or write request will comprise a preamble, followed by a node ID, plus a read or write request… Paragraph 0229, Nodes will be grouped into clusters that can communicate directly with each other, with a global router), wherein: one or more of the routing network, the set of sending devices, and the set of receiving devices are part of a superconducting device (Fig. 3, Network router and sending/receiving processor nodes are part of a superconductor; Paragraph 0154, described hereinabove new superconducting architectures for parallel applications using ERSFQ… Paragraph 0157, includes a system of compute nodes, each with processors and a supporting memory hierarchy, interconnected by a networking fabric to primary storage); and coupling a subset of the set of sending devices to a subset of the set of receiving devices based on the set of schedules (Fig. 5, Round robin scheduling module interconnects four different groups of sending/receiving threads (i.e. thread group 0-3, thread group 4-7, thread group 8-11, and thread group 12-15) implemented on processor nodes based on a round-robin order (i.e. round-robin arbitrates communications between groups of threads one after the other and thus is a set of connection schedules); Paragraph 0099, pseudo round-robin scheme which… divides the sixteen threads into four groups, and uses a four-bit shifter to select one of the groups in round-robin order).
Ipek does not explicitly teach the apparatus comprising the set of sending devices and the set of receiving devices use a race logic architecture.
Gupta teaches the apparatus comprising the set of sending devices and the set of receiving devices use a race logic architecture (Figs. 2 and 24, ADC 120 in Figure 2 contains race arbitration logic shown in Figure 24; Paragraph 0131, ADC 120 is a so-called `race arbiter` circuit. A basic race arbiter circuit is shown in FIG. 24. A race arbiter determines the arrival of one signal with respect to another signal in time. In rapid single flux quantum (RSFQ) circuits digital "1" ("0") is represented by the presence (or absence) of data signal with respect to clock signal, where both data and clock are in the form of single flux quantum (SFQ) pulses).
Ipek and Gupta are analogous arts because they are in the same field of endeavor of controlling data communications in a superconducting quantum communication network.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ipek’s apparatus to incorporate the teachings of Gupta and include race logic arbitration between the receiving/sending processor nodes of Ipek.
One of ordinary skill in the art would be motivated to make the modifications in order to provide a universal data communication standard that can flexibly support multiple types of modulation and frequency bands (See Gupta: Paragraph 0042) which can improve efficiency and bandwidth use (See Gupta: Paragraphs 0045-0047).
Claims 2-4 and 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Ipek (US 2019/0188596) in view of Gupta (US 2004/0022332) and further in view of Elg (US 2004/0047319).
Regarding claim 2, Ipek in view of Gupta teaches the apparatus of claim 1. Neither Ipek nor Gupta teaches the apparatus comprising wherein: each connection schedule of the set of connection schedules is divided into a set of windows; and each window is divided into a set of time slots.
Elg teaches the apparatus (Fig. 1, Mesh network apparatus 100 for communicating packets between masters and slaves) comprising wherein: each connection schedule of the set of connection schedules is divided into a set of windows (Fig. 5, Multiple contention windows 501; Paragraph 0042, contention windows of time (henceforth referred to simply as "contention windows") are defined to occur at predefined intervals of time 500); and each window is divided into a set of time slots (Fig. 5, Contention windows 501 are divided into a plurality of slots S; Paragraph 0042, "contention windows") are defined to occur at predefined intervals of time 500. Each contention window 501 begins on a time slot boundary within the communications system and occupies a predefined number of slots, S).
Ipek, Gupta, and Elg are analogous arts because they are in the same field of endeavor of scheduling communication packets between senders and receivers in a network.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ipek/Gupta’s apparatus to incorporate the teachings of Elg and include multiple time windows containing multiple time slots that can be used for communications wherein packets are identified based on group access codes.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent communication conflicts and contention thus optimizing performance (See Elg: Paragraphs 0011-0017 and 0020-0023).
Regarding claim 3, the combination of Ipek/Gupta/Elg teaches the apparatus of claim 2.
Elg teaches the apparatus comprising wherein a values of a packet are based on a window when the packet was received (Fig. 3, Packet contains access code 201 which is based on a contention window group; Paragraph 0038, master and one or more slaves form a piconet which is a star network with the master controlling the traffic… packet is illustrated in greater detail in FIG. 3. The preamble 201 contains a unique binary code identifying the piconet… Paragraph 0054, These one or more communication units together constitute a "contention group". At the top of the loop, it is determined whether the present time slot is a contention window priority slot).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ipek/Gupta’s apparatus to incorporate the teachings of Elg and include multiple time windows containing multiple time slots that can be used for communications wherein packets are identified based on group access codes.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent communication conflicts and contention thus optimizing performance (See Elg: Paragraphs 0011-0017 and 0020-0023).
Regarding claim 4, the combination of Ipek/Gupta/Elg teaches the apparatus of claim 2.
Elg teaches the apparatus comprising wherein each of the different subsets of the set of sending devices and the different subsets of the set of receiving devices are associated with a respective window of the set of windows (Fig. 5, Different devices A, B, C are part of different contention groups which each use a different contention window 501; Paragraph 0081, Starting at the beginning of a contention window 500, each member of the contention group that wishes to transmit a packet first listens to the communication medium for up to s time slots in order to determine whether any other communication unit is accessing the medium (decision block 801). If any other access is detected during these s time slots ("YES" path out of decision block 801), then the present communication unit will have to try to gain access during a next contention window).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ipek/Gupta’s apparatus to incorporate the teachings of Elg and include multiple time windows containing multiple time slots that can be used for communications wherein packets are identified based on group access codes.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent communication conflicts and contention thus optimizing performance (See Elg: Paragraphs 0011-0017 and 0020-0023).
Regarding claim 12, Ipek in view of Gupta teaches the system of claim 11. Neither Ipek nor Gupta teaches the system comprising wherein: each connection schedule of the set of connection schedules is divided into a set of windows; and each window is divided into a set of time slots.
Elg teaches the system (Fig. 1, Mesh network system 100 for communicating packets between masters and slaves) comprising wherein: each connection schedule of the set of connection schedules is divided into a set of windows (Fig. 5, Multiple contention windows 501; Paragraph 0042, contention windows of time (henceforth referred to simply as "contention windows") are defined to occur at predefined intervals of time 500); and each window is divided into a set of time slots (Fig. 5, Contention windows 501 are divided into a plurality of slots S; Paragraph 0042, "contention windows") are defined to occur at predefined intervals of time 500. Each contention window 501 begins on a time slot boundary within the communications system and occupies a predefined number of slots, S).
Ipek, Gupta, and Elg are analogous arts because they are in the same field of endeavor of scheduling communication packets between senders and receivers in a network.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ipek/Gupta’s system to incorporate the teachings of Elg and include multiple time windows containing multiple time slots that can be used for communications wherein packets are identified based on group access codes.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent communication conflicts and contention thus optimizing performance (See Elg: Paragraphs 0011-0017 and 0020-0023).
Regarding claim 13, the combination of Ipek/Gupta/Elg teaches the system of claim 12.
Elg teaches the system comprising wherein a values of a packet are based on a window when the packet was received (Fig. 3, Packet contains access code 201 which is based on a contention window group; Paragraph 0038, master and one or more slaves form a piconet which is a star network with the master controlling the traffic… packet is illustrated in greater detail in FIG. 3. The preamble 201 contains a unique binary code identifying the piconet… Paragraph 0054, These one or more communication units together constitute a "contention group". At the top of the loop, it is determined whether the present time slot is a contention window priority slot).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ipek/Gupta’s system to incorporate the teachings of Elg and include multiple time windows containing multiple time slots that can be used for communications wherein packets are identified based on group access codes.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent communication conflicts and contention thus optimizing performance (See Elg: Paragraphs 0011-0017 and 0020-0023).
Regarding claim 14, the combination of Ipek/Gupta/Elg teaches the system of claim 12.
Elg teaches the system comprising wherein each of the different subsets of the set of sending devices and the different subsets of the set of receiving devices are associated with a respective window of the set of windows (Fig. 5, Different devices A, B, C are part of different contention groups which each use a different contention window 501; Paragraph 0081, Starting at the beginning of a contention window 500, each member of the contention group that wishes to transmit a packet first listens to the communication medium for up to s time slots in order to determine whether any other communication unit is accessing the medium (decision block 801). If any other access is detected during these s time slots ("YES" path out of decision block 801), then the present communication unit will have to try to gain access during a next contention window).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Ipek/Gupta’s system to incorporate the teachings of Elg and include multiple time windows containing multiple time slots that can be used for communications wherein packets are identified based on group access codes.
One of ordinary skill in the art would be motivated to make the modifications in order to prevent communication conflicts and contention thus optimizing performance (See Elg: Paragraphs 0011-0017 and 0020-0023).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PGPUB 2012/0328290 to Yuan discloses a superconducting quantum computer wherein a timing control module controls routing of light pulses between a transmitter source and a receiver.
US PGPUB 2014/0317582 to Chan discloses race logic synthesis of IC circuits.
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/H.Z.W./Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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