DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to submission of application on 11/07/2023.
Claims 57-76 are presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 66 is objected to because of the following informalities:
Claim 66 recites the limitation “the delay line elements.” There is insufficient antecedent basis for this limitation in the claims.
Appropriate correction is required.
Claim 57-76 are rejected under 35 U.S.C 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention.
Claim 57 includes the limitation, “wherein the inner ring and the outer ring operate in tandem to achieve efficient short-term accurate storage of delay state.” This limitation is indefinite because “efficient” and “accurate” are terms of degree with no relative basis for comparison.
Claim 63 includes the limitation, “wherein time is stored temporarily in a nanowatt or a picowatt power consumption space.” This limitation is indefinite because the term “temporarily” is a term of degree and it is undefined how long “temporarily” is.
Claim 69 includes the limitation, “wherein the period of time is seconds.” This limitation is indefinite because it is unbounded.
Claim 76 includes the limitation, “wherein all information is processed ratiometrically with respect to time.” This limitation is indefinite because the scope of “all information” is unclear. Claims 58-76 are dependent on claim 57, thus rejected on the same grounds of rejected claim 57.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The following are the references used:
Du, Kevin Tan (Time Domain Multiply and Accumulate Engine for Convolutional Neural Networks, herein Du)
Tadros et al. (Ultra-low power pass-transistor-logic-based delay line design for sub-threshold applications, herein Tadros)
Shimomura et al (US 7952510 B2, Solid-state Imaging Device, Driving Method Thereof, And Camera, herein Shimomura)
Yamaguchi et al. (An Energy-efficient Time-domain Analog VLSI Neural Network Processor Based on a Pulse-width Modulation Approach, herein Yamaguchi)
Kiyota (US 5402009 A, Pulse Generator For Generating A Variable-width Pulse Having A Small Delay, herein Kiyota)
Claim(s) 57, 58, and 73-76 is/are rejected under 35 U.S.C. 103 as being unpatentable over Du in view of Tadros.
Regarding claim 57,
Du teaches,
An apparatus for providing an ephemeral memory for retaining information temporarily between layers of an artificial neural network (ANN), the apparatus comprising: (Du, page 11, section 2.3.1, “a string of tri-state inverters can function as a time-register, essentially storing time information for later use.”, note: storing information for later use is retention that is temporary rather than permanent, which is ephemeral memory. Du, abstract, “time domain multiply-and-accumulate (MAC) engine used for convolutional neural networks.”)
an inner ring comprising (Du, page 18, section 3.5.1, “The GRO TDC consists of an odd numbered ring of tri-state inverters.”, note: Du’s delay block is a ring of inventers and maps to an inner ring. Du, page 12, section 2.3.1, “the nodes will charge sequentially according to the intrinsic delay of the inverter. Therefore, the phase of the GRO will advance through the circuit”, note: the signal moves around Du’s ring one inverter at a time, and how fast it moves is set by how long each inverter takes to switch which is intrinsic delay. This is a circuit that paces itself off its own date delays with no external clock which makes it asynchronous. Du page 21-22, section 3.5.2, “the second path will be selected, collapsing the DCGRO into a ring with half as many delay elements. 21 In this state, the phase will advance twice as fast by skipping every other inverter, corresponding to quantizing twice as much information due to reaching the counter twice as fast… the first path will be selected, doubling the number of delay elements. The phase advances at the original rate in this case,” note: The amount of delay is a settable quantity, not a fixed one which maps to controllable delay.)
and an outer ring comprising a plurality of asynchronous counters to support the inner ring; (Du, page 12, section 2.3.1, Figure 4, “
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… the phase of the GRO will advance through the circuit as shown in Figure 5, incrementing the counter at each point, converting the time domain signal to a digital value, which is stored in the counter… the counters at each node can be removed, and a single counter can be used at any given node” note: Fig. 4 shows a counter at each node. Du says the per-node counters can be removed and you can only remove things that are there. Therefore, there are multiple counters. Also. A counter driven by the circuit’s own edges instead of a clock is asynchronous and the counter’s job is to turn the ring’s phase into a stored number. So the counters exist to serve the ring which maps to supper the inner ring.)
wherein the inner ring and the outer ring operate in tandem to achieve efficient short-term accurate storage of delay state. (Du, page 19, section 3.5.1, “the phase in the GRO is held while the input is low, storing accumulated phase corresponding to the input pulse width. When the phase reaches the end of the ring, the input to the counter will toggle from low to high, incrementing the MAC out value.”, note: Du shows two halves splitting the work, which maps to in tandem. The ring keeps the leftover partial amount, it freezes mid-lap and holds that phase. The counter keeps the whole laps, every time the phase finishes a lap, the counter moves up one.)
Du does not teach,
an analog subthreshold delay block
Tadros teaches,
an analog subthreshold delay block (Tadros, abstract, “a pass-tran-sistor-logic-based programmable delay line (DL) circuit is presented that is designed specifically for sub-threshold operation” note: a delay line that’s timing is set by that below-threshold current maps to the analog subthreshold delay block)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Du and Tadros because Du wants low power and tells it to drop the supply voltage toward the transistor threshold, but it stops at the threshold. Tadros is built to operate below the threshold. This allows for controllable delay at a lower power.
Regarding claim 58,
Tadros teaches,
The apparatus of claim 57, wherein the analog subthreshold delay block comprises a plurality of subthreshold pass transistor logic (PTL) delay line elements. (Tadros, abstract, “a pass-tran-sistor-logic-based programmable delay line (DL) circuit is presented that is designed specifically for sub-threshold operation”)
Regarding claim 73,
Du teaches,
The apparatus of claim 57, wherein the apparatus uses dynamic logic to save space and power. (Du, page 19, section 3.5.1, “As the input falls low, the nodes are frozen and the charge on the nodes are held, even if they are not fully 1”, note: The circuit remembers something by parking the electrical charge on a wire and leaving it there. It holds whichever charge happens to be sitting there which maps to dynamic logic, remembering by parking charge saves space and power because it skips the extra transistors.)
Regarding claim 74,
Du teaches,
The apparatus of claim 57, wherein the ephemeral memory comprises time-ephemeral memory. (Du, page 11, section 2.3.1, “a string of tri-state inverters can function as a time-register, essentially storing time information for later use.” note: the claim asks for a memory that is temporary and holds time. Du stores time information and it only stores it for later use and then lets it go.)
Regarding claim 75,
Du teaches,
The apparatus of claim 74, wherein time is calculated as one or more of absolute time, elapsed time, delay in time, and rate of change in time. (Du, page 17, section 3.3, “each element along the delay line adds an additional LSB to the pulse width, modulating the pulse by changing when it falls from high to low”, note: Du builds its number by stacking up delays. Each part in the chain makes the pulse a little bit longer by pushing back the moment it switches off. So the value Du works with is made out of delay and is carried around as the length of a pulse.)
Regarding claim 76,
Du teaches,
The apparatus of claim 74, wherein time is calculated as absolute time (Du, page 15, section 3.3, “An input clock with period Tmax equal to the maximum possible pulse width is asserted at the beginning of the delay line” note: Du’s values are stretches of time with actual pulse lengths, measured against a fixed window. Real durations are absolute time.)
and wherein all information is processed ratiometrically with respect to time (Du, page 20, section 3.5.1, “If the input time scale is equal to the time scale of the delay elements in the GRO, the scaling factor is simply the number of delay elements in the GRO divided by the number of counters along the ring” note: ratiometrically means that the answer comes from a ratio, one thing divided by another. Du does this because to get the final answer, Du multiplies by a ratio, the number of delay parts divided by the number of counters.)
Claim(s) 59-63, 65, and 66 is/are rejected under 35 U.S.C. 103 as being unpatentable over Du in view of Tadros and Shimomura.
Regarding claim 59,
Du teaches,
The apparatus of claim 57, wherein the asynchronous counters comprise a first asynchronous counter, (Du, page 12, section 2.3.1, “incrementing the counter at each point… a single counter can be used at any given node”, note: Du has a counter sitting on the ring, it ticks on the ring’s own signal walking past, not a clock which makes it asynchronous.)
Du does not teach,
wherein the first asynchronous counter is a 1-bit asynchronous sub-threshold counter, and wherein the asynchronous counters comprise D flip-flops.
Shimomura teaches,
wherein the first asynchronous counter is a 1-bit asynchronous sub-threshold counter, and wherein the asynchronous counters comprise D flip-flops. (Shimomura, Fig 8, “a plurality of negative-edge D flip-flops 412, 414, 416, and 418 (collectively 410) are connected by cascade connection. Each of the flip-flops 410 has an inverting output NQ (indicated with a horizontal bar over Q in the diagram) connected to a D input terminal thereof. Thus, the counter circuit 400 is capable of functioning as a 4-bit asynchronous counter” note: A d flip-flop is a small circuit that remembers one bit, a single 0 or 1. Shimomura wires each one so that its opposite answer feeds back into itself. The effect is that every time a signal arrives, the flip flop flips, 0 becomes 1 and 1 become 0.)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Du, Tadros, and Shimomura because Du has a counter that sits at each node of the ring and it records how far the ring advances. However, it only states that it exists and what it does, but not what it is made of. Shimomura explains a counter built from a chain of D flip-flops connected one after another. This allows for each stage to be triggered by the one before it rather than a clock.
Regarding claim 60,
Du teaches,
The apparatus of claim 59, further comprising multiple asynchronous counters. (Du, page 12, section 2.3.1, “the counters at each node”)
Regarding claim 61,
Shimomura teaches,
The apparatus of claim 60, wherein the multiple asynchronous counters are 1-bit cascaded sub-threshold counters. (Shimomura, Fig 8, “a plurality of negative-edge D flip-flops 412, 414, 416, and 418 (collectively 410) are connected by cascade connection. Each of the flip-flops 410 has an inverting output NQ (indicated with a horizontal bar over Q in the diagram) connected to a D input terminal thereof. Thus, the counter circuit 400 is capable of functioning as a 4-bit asynchronous counter” note: A d flip-flop is a small circuit that remembers one bit, a single 0 or 1. Shimomura wires each one so that its opposite answer feeds back into itself. The effect is that every time a signal arrives, the flip flop flips, 0 becomes 1 and 1 become 0.)
Regarding claim 62,
Du teaches,
The apparatus of claim 59, wherein the ephemeral memory functions asynchronously. (Du, page 12, section 2.3.1, “the nodes will charge sequentially according to the intrinsic delay of the inverter… Due to the gating of the inverters, the internal nodes will hold their charge and the GRO will hold its phase for as long as the enable signal is held low.”)
Regarding claim 63,
Du teaches,
The apparatus of claim 59, wherein time is stored temporarily in a nanowatt or a picowatt power consumption space (Du, page 19, section 3.5.1, “Due to the gating of the inverters, the internal nodes will hold their charge and the GRO will hold its phase for as long as the enable signal is held low.” And Du, page 36, section 5.3, “The power consumption of the DCGRO was measured to be 283.6pW”)
Regarding claim 65,
Du teaches,
The apparatus of claim 59, wherein the analog subthreshold delay block and the first asynchronous counter together create a positive feedback loop with internal delay resulting in an oscillator. (Du, page 18, section 3.5.1, “an odd numbered ring of tri-state inverters,” Du, page 12, section 2.3.1, “the nodes will charge sequentially according to the intrinsic delay of the inverter… incrementing the counter at each point,” Du, page 19, section 3.5.1, “the ring oscillates and the phase along the ring advances as the nodes”, note: An inverter is a part that flips whatever comes in, a 1 goes in and a 0 goes out. Du makes the inverters into a closed loop with an odd number of them. When it sends a signal around the loop and because it gets flipped an odd number of times, it comes back as the opposite of what it started as, which flops the loop again. The output keeps re-driving the input, which is a feedback loop. The internal delay maps to the trip around the loop is not instant. The delay is in the loop because it takes a moment to switch.)
Regarding claim 66,
Du teaches,
The apparatus of claim 65, wherein the oscillator is a self-timed oscillator that oscillates based on a frequency of the delay line elements, (Du, page 19, section 3.5.1, “the ring oscillates” and page 12, section 2.3.1, “the nodes will charge sequentially according to the intrinsic delay of the inverter” note: Du’s ring swings back and forth on its own at the space of as fast as the inverters can switch. Its speed is decided by the delay parts themselves)
and wherein the apparatus further comprises a second counter clocked by the self- timed oscillator and created by the delay line elements and the first asynchronous counter. (Du, page 12, section 2.3.1, “the phase of the GRO will advance through the circuit as shown in Figure 5, incrementing the counter at each point, converting the time domain signal to a digital value, which is stored in the counter.”)
Claim(s) 67-70, and 72 is/are rejected under 35 U.S.C. 103 as being unpatentable over Du in view of Tadros, Shimomura, and in view of Yamaguchi and Kiyota.
Regarding claim 67,
Du teaches,
wherein the oscillator triggers the first asynchronous counter to count up when the oscillator is enabled, (Du, page 19, section 3.5.1, “When the phase reaches the end of the ring, the input to the counter will toggle from low to high, incrementing the MAC out value.” note: while the ring is oscillating, every completed traversal raises a counter by 1, which is counting up.)
wherein when the capacitor is discharged the oscillator is disabled and the first asynchronous counter retains a value, (Du, page 19, section 3.5.1, “As the input falls low, the nodes are frozen and the charge on the nodes are held, even if they are not fully 1. Thus, the phase in the GRO is held while the input is low,” note: when the input is removed the ring freezes, so oscillation ceases and simply holds the number it had reached.
Du does not teach,
The apparatus of claim 66, wherein the oscillator is enabled when a capacitor is discharging,
wherein the oscillator is subsequently enabled again and the first asynchronous counter counts back down to zero during a first time, and wherein during the first time a pulse is generated as an input to a subsequent neuron.
Yamaguchi teaches,
The apparatus of claim 66, wherein the oscillator is enabled when a capacitor is discharging, (Yamaguchi, page 3, section 2, “The total charge amount Q stored at the node of capacitor C charged by N SCSs with inputs Si, each of which has pulse width of Wi, is expressed by N X Q= i=1 WiIi, (1) where Q can be considered as the weighted-sum calculation result” and abstract, “our time-domain analog circuits use transient operation in charging/discharging processes to capacitors.” and page 4, section 2, “Vn is reset by Srst”, note: The capacitor of Yamaguchi accumulates the charge representing the weighted sum, and the timed operation of the neuron runs over the capacitor’s transient, beginning when the transient begins and ends when the comparator fires, where the capacitor is reset for the next cycle. The interval during which is circuit is active is therefore controlled by the capacitor’s charge/ discharge cycle)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Du, Tadros, Shimomura, and Yamaguchi because Du’s counter runs, but does not have a start or stop criteria. Yamaguchi uses a capacitor that fills and empties to a trigger point to mark that window. This allows for the count to end up matching the size of the signal.
Kiyota teaches,
wherein the oscillator is subsequently enabled again and the first asynchronous counter counts back down to zero during a first time, and wherein during the first time a pulse is generated as an input to a subsequent neuron. (Kiyota, claim 1, “a down counter… counting down the number… said first state signal being used to generate a start of said variable width pulse; and a detection circuit… producing a second state signal indicating an end of said variable width pulse.” note: the stored number is counted back down, and the countdown itself produces a pulse. It begins when the countdown starts and ends when the count reaches its target.
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Du, Tadros, Yamaguchi, and Kiyota because Du saves the count as a number, but does not say how to turn it back into a pulse for the next neuron. Kiyota’s down counter counts the number back down and makes a pulse as long as that number, so that the pulse comes out to the same width that was stored.
Regarding claim 68,
Du teaches,
wherein when the first activation pulse is high, the first activation pulse enables the oscillator, (Du, page 18-19, section 3.5.1, “When an input signal is asserted on the enable signal of the inverters, the ring oscillates and the phase along the ring advances” note: when the input pulse is high, the ring runs.)
and wherein when the first activation pulse is low, the first activation pulse disables the oscillator and the first asynchronous counter stops, the first asynchronous counter having stored a number representing a pulse width of the first activation pulse, (Du, page 19, section 3.5.1, “the phase in the GRO is held while the input is low, storing accumulated phase corresponding to the input pulse width” note: when the pulse goes low the phase is held, so the oscillation stops and the counter stops. The number remaining in the counter is, one corresponding to the input pulse width. The longer the pulse was held high, the further the phase advanced and the greater the number accumulated. Therefore, the counter stored a number representing the pulse width of the received pulse.)
the first asynchronous counter further retaining the stored number for a period of time. (Du, page 12, section 2.3.1, “converting the time domain signal to a digital value, which is stored in the counter.” And page 19, section 3.5.1, “As the input falls low, the nodes are frozen and the charge on the nodes are held, even if they are not fully 1. Thus, the phase in the GRO is held while the input is low,” note: It establishes that the digital value produced by the conversion lives in the counter and is stored there. Also, once the input falls, the circuit is frozen and holds its state, so the counter is no longer incremented. Therefore, the number that is stored in the counter is retained for a period of time)
Du does not teach,
The apparatus of claim 67, wherein during a discharge period a neuron generates the first activation pulse,
Yamaguchi teaches,
The apparatus of claim 67, wherein during a discharge period a neuron generates the first activation pulse, (Yamaguchi, page 7, section 3.2, “In the neuron circuit, dendrite lines are initialized and reset at ground level by Srst before inputting signals Si to the synapse part. Next, input PWM signals are given during input time period Tin, and capacitance Cdi and Cn are charged. Then, dendrite lines are separated by neuron parts with Sn. At the same time, the current source In is connected to capacitance Cn, and thus Cn is charged. When the node voltage of Cn, V± n , reaches the threshold voltage of the comparator, the output signal S± out is generated.” and page 4, section 2, “pulse width of the output signal as a result of weighted-sum calculation” note: The neuron generating its output signal over the interval of the capacitor’s transient, the signal being produced when the capacitor node reaches the comparator threshold. It also shows the width of that output pulse is et by the charge accumulated on the capacitor.)
Regarding claim 69,
Du teaches,
The apparatus of claim 68, wherein the period of time is seconds. (Du, page 12, section 2.3.1, “converting the time domain signal to a digital value, which is stored in the counter. Due to the gating of the inverters, the internal nodes will hold their charge and the GRO will hold its phase for as long as the enable signal is held low” note: the converted value is inside the counter and is stored there. The circuit holds its state for as long as the enable signal is held low. Therefore, the counter could retain a number for seconds.)
Regarding claim 70,
Du teaches,
The apparatus of claim 67, wherein the first asynchronous counter counts up during the first activation pulse (Du, page 19, section 3.5.1, “storing accumulated phase corresponding to the input pulse width… the input to the counter will toggle from low to high, incrementing the MAC out value” note: The counter climbs for as long as the pulse is high and ends up holding that pulse’s width.)
to enable the delay line elements and generate a second activation pulse equal to the first activation pulse. (Du, page 17, section 3.3, “a pulse is generated with width n x τ, where n is the number of delay elements”)
Du does not teach,
and counts down as the apparatus applies the first activation pulse to the subsequent neuron
Kiyota teaches,
and counts down as the apparatus applies the first activation pulse to the subsequent neuron (Kiyota, claim 1, “a down counter… said first state signal being used to generate a start of said variable width pulse; and a detection circuit… producing a second state signal indicating an end of said variable width pulse.”)
Regarding claim 72,
Yamaguchi teaches,
The apparatus of claim 66, wherein the second counter counting up is enabled by an accumulator capacitor discharge cycle (Yamaguchi, page 3, section 2, “The total charge amount Q stored at the node of capacitor C charged by N SCSs with inputs Si, each of which has pulse width of Wi, is expressed by N X Q= i=1 WiIi, (1) where Q can be considered as the weighted-sum calculation result” and abstract, “our time-domain analog circuits use transient operation in charging/discharging processes to capacitor” note: the capacitor of Yamaguchi is an accumulator capacitor. The charge Q that it holds is the accumulated weighted-sum result. The timed interval over which the neuron operates runs across the capacitor’s transient. The counting interval is controlled by the capacitor’s charge/discharge cycle.)
and disabled when a comparator flips state according to a threshold voltage, (Yamaguchi, page 3-4, section 2, “The VPC part consists of an SCS, two switches, and a comparator with an input capacitance Cn… only Cn can be charged up to the threshold voltage Vθ of the comparator… When Vn > Vθ, the comparator output Sout = 1,” and page 7, section 3.2, “When the node voltage of Cn, V± n , reaches the threshold voltage of the comparator, the output signal S± out is generated” note: The interval isn’t a fixed length. It runs until the capacitor node crosses the threshold voltage. The comparator is changing state at that threshold, crossing it terminates it.)
Kiyota teaches,
and wherein the first asynchronous counter counting down is enabled by a start-of-inference signal for a subsequent layer of the ANN. (Kiyota, claim 1, “a down counter… said down counter counting down the number of clock signals indicated by said data signal, when said enable signal is received” note: The down counter of Kiyota begins counting down only upset receiving of an enable signal.)
Claim(s) 64 is/are rejected under 35 U.S.C. 103 as being unpatentable over Du in view of Tadros and in further view of Shimomura and Kiyota.
Regarding claim 64,
Du teaches,
The apparatus of claim 59, wherein the apparatus receives a first activation pulse, (Du, page 19, section 3.5.1, “the phase in the GRO is held while the input is low, storing accumulated phase corresponding to the input pulse width” note: receiving an input pulse)
wherein the apparatus stores a width of the first activation pulse via the first asynchronous counter, (Du, page 19, section 3.5.1, “the phase in the GRO is held while the input is low, storing accumulated phase corresponding to the input pulse width” and page 12, section 2.3.1, “converting the time domain signal to a digital value, which is stored in the counter” note: while the pulse is on, the rung runs and the counter continues, when the pulse ends, the ring freezes. It stores the width of the received pulse through the counter)
and wherein the apparatus transmits the first activation pulse to a subsequent layer of the ANN (Du, page 17, section 3.3, “a pulse is generated with width n x τ, where n is the number of delay elements” note: A number applied to the delay element produces a pulse with corresponding width)
Du does not teach,
by counting down on the first asynchronous counter.
Kiyota teaches,
by counting down on the first asynchronous counter. (Kiyota, claim 1, “a down counter… said down counter counting down the number of clock signals indicated by said data signal, when said enable signal is received… said first state signal being used to generate a start of said variable width pulse; and a detection circuit… detecting when said output signals indicate that the counted number is a particular number and producing a second state signal indicating an end of said variable width pulse.” note: a number is loaded into a counter and counted backwards, and the counting down itself produces a pulse. Reading a stored count back out, by counting down, as a pulse of matching width)
It would be obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Du, Tadros, Shimomura, and Kiyota because Du explains saving a pulse’s width as a number and it can turn a number back into a pulse, but does not say how to connect the two. Kiyota does this by its down counter counts the saved number back down, and counting down makes a pulse that long. This allows for the pulse to be used so that the saved width can be send onto the next layer.
Regarding claim 71,
Du teaches,
The apparatus of claim 66, wherein the first asynchronous counter is paired with the second counter (Du, page 12, section 2.3.1, “the counters at each node can be removed, and a single counter can be used at any given node” note: the limitation requires two counters, a first and a second. Du has a counter at each node of the ring, that means there’s more than one counter.)
the second counter counts up to further store the width of the first activation pulse. (Du, page 12, section 2.3.1, “the phase of the GRO will advance through the circuit as shown in Figure 5, incrementing the counter at each point” and page 19, section 3.5.1, “the phase in the GRO is held while the input is low, storing accumulated phase corresponding to the input pulse width” note: the limitation requires storing the width of the first activation pulse. Du stores that input pulse width in the counter.)
Kiyota teaches,
configured oppositely so that as the first asynchronous counter counts down (Kiyota, claim 1, “a down counter… said down counter counting down the number of clock signals indicated by said data signal, when said enable signal is received,”)
Conclusion
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/U.P.T./Examiner, Art Unit 2124
/MIRANDA M HUANG/Supervisory Patent Examiner, Art Unit 2124
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