Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, and 13-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by UEDA (WO 2008044276 A1)(cited by the applicant), hereafter referred to as “Ueda”.
Regarding claims 1 and 14, 15, in the embodiment of Fig. 5, Ueda discloses:
An amplifier circuit and power amplifier (Fig. 5, power amplifying device, as per claim 14) comprising:
an input terminal (RF input side);
an output terminal (RF output);
one or a plurality of transistors (amplification transistor 107) provided on a path that couples the input terminal and the output terminal (as shown in Fig. 5);
an amplitude detection circuit (average processing unit 103 and peak detection unit 104) configured to detect a signal amplitude of an input signal at the input terminal (paragraph [0025]-[0026], 103 and 104 detects average power or peak power (i.e. the signal amplitude)); and
an impedance circuit (amplifier control unit 109) configured to change an impedance and set operating conditions of the one or the plurality of transistors on a basis of a detection result of the amplitude detection circuit (paragraph [0026], amplifier control unit 109 adjusts the amplification factor of the variable gain amplifier 105 and the power supply voltage of the transistor 107 based on the input average power and peak power (i.e. 103 and 104)).
Regarding claim 4, in the embodiment of Figs. 5 and 6, Ueda discloses:
the impedance circuit includes a varactor (variable capacitor C110, [0033] formed by a parallel capacitor and a varactor diode), and is configured to change the impedance by causing a capacitance value in the varactor to vary on the basis of the detection result (paragraph [0033], Fig. 5 load impedance can be varied by changing the capacitance of C110 in Fig. 6).
Regarding claim 13, in the embodiment of Fig. 5, Ueda discloses:
the one or the plurality of transistors includes a final-stage transistor (amplifier transistor 107 is part of the output of the amplifier as per paragraph [0029]) including a drain (107 drain), the amplifier circuit includes a second matching circuit (output matching circuit 108) that is provided on a path coupling the drain of the final-stage transistor and the output terminal and is configured to change an impedance, and the impedance circuit includes the second matching circuit (paragraph [0022], output matching circuit 108 includes an impedance variable circuit and has a function of changing the load impedance based on a control signal from the amplifier control unit 109).
Claims 1, 4-6, 14 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Harris et al. (US 8855584 B2), hereafter referred to as “Harris”.
Regarding claims 1 and 14, 15, in the embodiment of Figs. 7 and 9, Harris discloses:
An amplifier circuit and power amplifier (Figs. 7 and 9, transmission circuitry as per claim 14) comprising:
an input terminal (RF input signal, RFin);
an output terminal (RF output signal, RFout);
one or a plurality of transistors (power amplifier circuitry 24, transistors form the power amplifier circuitry 24 as per column 17 lines 65-66) provided on a path that couples the input terminal and the output terminal (as shown in Figs. 7 and 9);
an amplitude detection circuit (processing circuitry 32) configured to detect a signal amplitude of an input signal at the input terminal (column 10, lines 24-33, the processing circuitry 32 may also dynamically monitor the RF input signal RFIN to detect amplitude, or phase of the RFIN.) (detected average power or peak power (i.e. the signal amplitude)); and
an impedance circuit (impedance control circuitry 30) configured to change an impedance and set operating conditions of the one or the plurality of transistors on a basis of a detection result of the amplitude detection circuit (column 9 lines 52-63, As RF input signal and conditions change, power amplifier circuitry 24 impedance can change and the impedance control circuitry 30 dynamically adjusts variable impedance elements).
Regarding claims 4-6, in the embodiment of Figs. 7 and 9, Ueda discloses:
the impedance circuit includes a varactor, a plurality of capacitors (Figs. 7 and 9, varactors V1-V6 , shown to be controlled by impedance control circuitry 30 and consist a plurality of capacitors, as per claim 5), and a plurality of inductors (Fig. 9, inductors L1 and L2, per claim 6) and is configured to change the impedance by causing a capacitance value in the varactor to vary on the basis of the detection result (column 14 lines 27-35, impedance control signals set the varactors capacitance values, and variable impedance network include inductors (e.g. L1) per column 9 lines 10-20).
Allowable Subject Matter
Claims 2-3 and 7-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2:
the cited prior art of record, UEDA and Harris et al., either singly or in proper combination, does not teach or make obvious, along with the other claimed features, “the amplitude detection circuit includes a separation device that separates an alternating-current signal from the input signal, and is configured to detect the signal amplitude of the input signal by detecting a signal amplitude of the alternating-current signal.”
Regarding claim 7:
the cited prior art of record, UEDA and Harris et al., either singly or in proper combination, does not teach or make obvious, along with the other claimed features, “a first transistor and a second transistor, the first transistor includes a drain and a gate led to the input terminal, and the second transistor includes a gate, a drain led to the output terminal, and a source led to the drain of the first transistor.”
Claims 3, and 8-12 are objected to as being dependent on objected claims 2 and 7.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALANE LIENG whose telephone number is (571)272-5739. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CST.
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/MALANE LIENG/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843