DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1, 11 and 20.
Pending: 1-6, 8-14 and 17-23.
Canceled: 7, 15 and 16.
Information Disclosure Statement
Applicant’s IDS(s) submitted on 11/9/2023 and 7/11/2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has/have considered by the examiner and made of record.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 11 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Prechtl et al., US PG pub. 20160071967 A1.
Re: Independent Claim 11, Prechtl discloses a circuit for a high electron mobility transistor (200, fig. 9) having an adjustable threshold voltage, the circuit comprising:
a high electron mobility transistor (200, fig. 9) having source (206, fig. 9), drain (208, fig. 9), gate (204, fig. 9), and a field plate (212, fig. 9) terminal,
the high electron mobility transistor (200, fig. 9) including:
a substrate (102, fig. 2);
a gallium nitride (GaN (106 form into 100, ¶0029)) channel layer;
an aluminum gallium nitride (AlGaN (118, fig. 9;¶0040)) barrier layer overlaying the GaN (106 form into 100, ¶0029) channel layer, wherein a two-dimensional electron gas (202, fig. 9) (2DEG) is interposed between the GaN (106 form into 100, ¶0029) channel layer and the AlGaN (118, fig. 9;¶0040) barrier layer; and a buried field plate (212, fig. 9) underlying the 2DEG (202, fig. 9), the buried field plate (212, fig. 9) coupled to the field plate (212, fig. 9) terminal and configured to adjust a threshold voltage of the high electron mobility transistor (200, fig. 9) responsive to a bias signal (¶0053) received at the field plate (212, fig. 9) terminal.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 8-10, 12-14 and 17-19 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Prechtl et al., US PG pub. 20160071967 A1; in view of Kelly et al. , US Patent 5801573 A.
Re: Independent Claim 1, Prechtl discloses a transistor (200, fig. 9) having a threshold voltage for switching the transistor (200, fig. 9) from a first conductive state to a second conductive state (¶0053; switching to on/off state), the transistor (200, fig. 9) including:
a first region (region 100 between 122 and 118, fig. 9) formed by a first compound semiconductor material (106 form into 100, ¶0029);
a second region (118, fig. 9) formed by a second compound semiconductor material (118, fig. 9;¶0040), the second region (118, fig. 9) overlying the first region (region 100 between 122 and 118, fig. 9) and forming a two-dimensional electron gas (202, fig. 9) (2DEG) at a junction with the first region (region 100 between 122 and 118, fig. 9); and a buried field plate (212, fig. 9) disposed proximate to the first region (region 100 between 122 and 118, fig. 9) so that the 2DEG (202, fig. 9) is interposed between the buried field plate (212, fig. 9) and the second region (118, fig. 9); and
a bias voltage (¶0053) to the buried field plate (212, fig. 9) responsive to an input signal received at the transistor (200, fig. 9).
Prechtl is silent regarding: a control circuit configured to adjust the threshold voltage of the transistor (200, fig. 9) by providing a bias voltage.
Kelly discloses a control circuit (5, fig. 1) can be used to configured to providing a bias voltage to transistor device (column 6, lines 4-11).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a control circuit for providing bias voltage for adjusting the threshold voltage and to signal to the transistor to switch turn on and off therefore the device knows to turn on and it can safely and efficiently handle power.
Re: Claim 2, Prechtl and Kelly discloses all the limitations of claim 1 on which this claim depends. Prechtl further discloses: wherein the transistor (200, fig. 9) includes: a gate (204, fig. 9) terminal overlying an area of the second region (118, fig. 9) formed by the second compound semiconductor material (118, fig. 9;¶0040);
source (206, fig. 9) and drain (208, fig. 9) terminals coupled to the 2DEG (202, fig. 9); and
a control terminal (field plate 212 not buried in the first and second region is the control terminal) coupled to the buried field plate (212, fig. 9) to provide the bias voltage (¶0053), the control terminal (field plate 212 not buried in the first and second region is the control terminal) being separate from the gate (204, fig. 9), source (206, fig. 9), and drain (208, fig. 9) terminals.
Re: Claim 3, Prechtl and Kelly discloses all the limitations of claim 1 on which this claim depends. Prechtl is silent regarding: wherein the transistor (200, fig. 9) is configured to amplify the input signal, and the control circuit is configured to adjust the threshold voltage of the transistor (200, fig. 9) responsive to at least one of:an amplitude of the input signal; a magnitude of a change to the input signal; or a frequency of the input signal.
Kelly discloses wherein the transistor (P, fig. 2) is configured to amplify (fig. 3a) the input signal (column 5, lines 60-67; column 6, lines 1-3) and the control circuit (5, fig. 2) is configured to adjust the threshold voltage of the transistor (P, fig. 2) responsive to at least one of: an amplitude of the input signal (column 6, lines 7-11); a magnitude of a change to the input signal; or a frequency of the input signal.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a control circuit for providing bias voltage for adjusting the threshold voltage and to signal to the transistor to switch turn on and off therefore the device knows to turn on and it can safely and efficiently handle power.
Re: Claim 4, Prechtl and Kelly discloses all the limitations of claim 1 on which this claim depends. Prechtl is silent regarding: wherein the control circuit is configured to obtain a sample of the input signal, and adjust an amplitude of the bias voltage (¶0053) based on the obtained sample.
Kelly discloses control circuit (5, fig. 2) is configured to obtain a sample of the input signal bias voltage based on the obtained sample (column 6, lines 7-11).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a control circuit for detect signal and configure the input signal bias voltage since this can prevent parasitic modes if the threshold voltage is not properly set it may result in high gate leakage current.
Re: Claim 5, Prechtl and Kelly discloses all the limitations of claim 1 on which this claim depends. Prechtl further discloses: wherein the transistor (200, fig. 9) comprises a gallium nitride (¶0003) high electron mobility transistor (200, fig. 9).
Re: Claim 6, Prechtl and Kelly discloses all the limitations of claim 5 on which this claim depends. Prechtl further discloses: wherein the first compound semiconductor material (106 form into 100, ¶0029) comprises a gallium nitride material and the second compound semiconductor material (118, fig. 9;¶0040) comprises an aluminum gallium nitride material.
Re: Claim 8, Prechtl and Kelly discloses all the limitations of claim 1 on which this claim depends. Prechtl further discloses: wherein the semiconductor device includes a silicon carbide substrate (102, fig. 2), and buried field plate (212, fig. 9) is formed in the silicon carbide substrate (102, fig. 2) (¶0066).
Re: Claim 9, Prechtl and Kelly discloses all the limitations of claim 1 on which this claim depends. Prechtl further discloses: wherein the buried field plate (212, fig. 9) is formed in a buried field plate (212, fig. 9) layer, the buried field plate (212, fig. 9) layer including an electrically active region (122, fig. 9; ¶0064) of an n- type material defining the buried field plate (212, fig. 9), and an electrically inactive region (120, fig. 9) of the n-type material proximate the electrically active region (122, fig. 9; ¶0064).
Re: Claim 10, Prechtl and Kelly discloses all the limitations of claim 1 on which this claim depends. Prechtl further discloses: wherein the buried field plate (212, fig. 9) is formed in a buried field plate (212, fig. 9) layer, the buried field plate (212, fig. 9) layer including an electrically active region (218, fig. 9; ¶0064) of a p- type material defining the buried field plate (212, fig. 9), and an electrically inactive region (120, fig. 9) of the p-type material proximate the electrically active region (218, fig. 9; ¶0064).
Re: Claim 12, Prechtl discloses all the limitations of claim 11 on which this claim depends. Prechtl is silent regarding: control circuitry coupled to the field plate (212, fig. 9) terminal and configured to automatically adjust the bias signal responsive to a signal applied at the gate (204, fig. 9) of the high electron mobility transistor (200, fig. 9).
Kelly discloses a control circuit (5, fig. 1) can be used to configured to providing a bias voltage to transistor device (column 6, lines 4-11).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a control circuit for providing bias voltage for adjusting the threshold voltage and to signal to the transistor to switch turn on and off therefore the device knows to turn on and it can safely and efficiently handle power.
Re: Claim 13, Prechtl and Kelly discloses all the limitations of claim 12 on which this claim depends. Prechtl is silent regarding: wherein the control circuitry is configured to automatically adjust the bias signal responsive to the signal applied at the gate (204, fig. 9) of the high electron mobility transistor (200, fig. 9) by adjusting the bias signal to increase the threshold voltage responsive to an increase in an amplitude of the signal applied to the gate (204, fig. 9) of the high electron mobility transistor (200, fig. 9).
Kelly discloses wherein the control circuitry (5, fig. 2) is configured to automatically adjust the bias signal responsive to the signal applied at the gate of the high electron mobility transistor (p, fig. 2) by adjusting the bias signal to increase the threshold voltage responsive to an increase in an amplitude of the signal applied to the gate of the high electron mobility transistor (column 6, lines 7-11).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a control circuit for detect signal and configure the input signal bias voltage since this can prevent parasitic modes if the threshold voltage is not properly set it may result in high gate leakage current.
Re: Claim 14, Prechtl and Kelly discloses all the limitations of claim 12 on which this claim depends. Prechtl further discloses: wherein the high electron mobility transistor (200, fig. 9) includes a silicon carbide substrate (102, fig. 2), and the buried field plate (212, fig. 9) is formed in a patterned region in the silicon carbide substrate (102, fig. 2;¶0066).
Re: Claim 17, Prechtl and Kelly discloses all the limitations of claim 12 on which this claim depends. Prechtl is silent regarding: wherein the control circuitry is configured to adjust the bias signal to voltage of the high electron mobility transistor (200, fig. 9) responsive to at least one of:an amplitude of the signal applied at the gate (204, fig. 9) of the high electron mobility transistor (200, fig. 9);
a magnitude of a change in the signal applied at the gate (204, fig. 9) of the high electron mobility transistor (200, fig. 9); or a frequency of the signal applied at the gate (204, fig. 9) of the high electron mobility transistor (200, fig. 9).
Kelly discloses wherein the transistor (P, fig. 2) is configured to amplify (fig. 3a) the input signal (column 5, lines 60-67; column 6, lines 1-3) and the control circuit (5, fig. 2) is configured to adjust the threshold voltage of the transistor (P, fig. 2) responsive to at least one of: an amplitude of the input signal (column 6, lines 7-11); a magnitude of a change to the input signal; or a frequency of the input signal.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a control circuit for providing bias voltage for adjusting the threshold voltage and to signal to the transistor to switch turn on and off therefore the device knows to turn on and it can safely and efficiently handle power.
Re: Claim 18, Prechtl and Kelly discloses all the limitations of claim 12 on which this claim depends. Prechtl further discloses: wherein the buried field plate (212, fig. 9) is formed in a buried field plate (212, fig. 9) layer of the high electron mobility transistor (200, fig. 9), the buried field plate (212, fig. 9) layer including an electrically active region (122, fig. 9; ¶0064) of an n-type material defining the buried field plate (212, fig. 9), and an electrically inactive region (120, fig. 9) of the n-type material proximate the electrically active region (122, fig. 9; ¶0064).
Re: Claim 19, Prechtl and Kelly discloses all the limitations of claim 12 on which this claim depends. Prechtl further discloses: wherein the buried field plate (212, fig. 9) is formed in a buried field plate (212, fig. 9) layer of the high electron mobility transistor (200, fig. 9), the buried field plate (212, fig. 9) layer including an electrically active region (218, fig. 9; ¶0064) of a p-type material defining the buried field plate (212, fig. 9), and an electrically inactive region (120, fig. 9) of the p-type material proximate the electrically active region (218, fig. 9; ¶0064).
Claim(s) 20-23 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Haeberlen et al., US PG pub. 20150256155 A1; in view of Prechtl et al., US PG pub. 20160071967 A1.
Re: Independent Claim 20, Haeberlen discloses method of operating a high electron mobility transistor (2, fig. 11), the method comprising:
detecting a signal (43, fig. 11) applied to a gate (23, fig. 11) of the high electron mobility transistor (2, fig. 11); and adjusting a threshold voltage (¶0053) of the high electron mobility transistor (2, fig. 11) responsive to the detected signal by:
determining a field plate (24, fig. 11) bias voltage to apply to a buried field plate (24, fig. 11) underlying a two-dimensional electron gas (2DEG) of the high electron mobility transistor (2, fig. 11) adjust the threshold voltage by selectively depleting the 2DEG; and
adjusting the threshold voltage (¶0053) by applying the field plate (24, fig. 11) bias voltage to the buried field plate (24, fig. 11).
Haeberlen is silent regarding: the field plate (24, fig. 11) is a buried field plate.
Prechtl discloses in figure 9 a field plate (212) voltage to apply to a buried field plate (212) underlying a two-dimensional electron gas (202) (2DEG) of the high electron mobility transistor (200).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include buried field plate so that increase breakdown voltage and reduce parasitic capacitance.
Re: Claim 21, Haeberlen and Prechtl discloses all the limitations of claim 20 on which this claim depends. Haeberlen further discloses: wherein determining the field plate (24, fig. 11) bias voltage to apply to a field plate (24, fig. 11) includes:
adjusting the field plate (24, fig. 11) bias voltage from a first value (¶0048) corresponding to a first threshold voltage of the high electron mobility transistor (2, fig. 11) to a second value (¶0048) to corresponding to a second threshold value (¶0048) of the high electron mobility transistor (2, fig. 11) responsive to a change in an amplitude of a voltage of the signal applied to a gate (23, fig. 11).
Haeberlen is silent regarding: the field plate (24, fig. 11) is a buried field plate.
Prechtl discloses in figure 9 a field plate (212) voltage to apply to a buried field plate (212) underlying a two-dimensional electron gas (202) (2DEG) of the high electron mobility transistor (200).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include buried field plate so that increase breakdown voltage and reduce parasitic capacitance.
Re: Claim 22, Haeberlen and Prechtl discloses all the limitations of claim 20 on which this claim depends. Haeberlen further discloses: wherein determining the field plate (24, fig. 11) bias voltage to apply to a field plate (24, fig. 11) includes:
adjusting the field plate (24, fig. 11) bias voltage from a first value (¶0048) corresponding to a first threshold voltage of the high electron mobility transistor (2, fig. 11) to a second value (¶0048) to corresponding to a second threshold value (¶0048) of the high electron mobility transistor (2, fig. 11) responsive to a change in a frequency of the signal applied to a gate (23, fig. 11).
Haeberlen is silent regarding: the field plate (24, fig. 11) is a buried field plate.
Prechtl discloses in figure 9 a field plate (212) voltage to apply to a buried field plate (212) underlying a two-dimensional electron gas (202) (2DEG) of the high electron mobility transistor (200).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include buried field plate so that increase breakdown voltage and reduce parasitic capacitance.
Re: Claim 23, Haeberlen and Prechtl discloses all the limitations of claim 20 on which this claim depends. Haeberlen further discloses: wherein applying the field plate (24, fig. 11;264, fig. 3) bias voltage to the field plate (24, fig. 11) includes applying the field plate (24, fig. 11) bias voltage to a field plate (24, fig. 11) terminal connected to the buried field plate (24, fig. 11), the field plate (24, fig. 11) terminal being electrically isolated (230, fig. 3) from source, drain, and gate (23, fig. 11) terminals of the high electron mobility transistor (2, fig. 3 and fig. 11).
Haeberlen is silent regarding: the field plate (24, fig. 11) is a buried field plate.
Prechtl discloses in figure 9 a field plate (212) voltage to apply to a buried field plate (212) underlying a two-dimensional electron gas (202) (2DEG) of the high electron mobility transistor (200).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include buried field plate so that increase breakdown voltage and reduce parasitic capacitance.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Shindome et al., US PG pub. 20180269290 A1”) discloses a nitride semiconductor device includes a first semiconductor layer including a nitride semiconductor, a second semiconductor layer contacting the first semiconductor layer and including a nitride semiconductor, a source electrode, a drain electrode, a first gate electrode, a second gate electrode provided on an opposite side, a first insulating layer and a second insulating layer. The gate electrode has a protrusion portion inside the semiconductor layer. A distance between the first gate electrode and the protrusion portion of the second gate electrode is shorter than a distance between the source electrode and the second insulating layer, and shorter than a distance between the drain electrode and the second insulating layer.
* (“Nakano et al., US PG pub. 20020185681 A1”) discloses a power MOS transistor formed of an array of source cells and drain cells on an IC chip substrate has a plurality of substrate contact cells, each formed external to the source cells, having respective substrate potential-setting electrodes to which an externally supplied substrate bias voltage can be applied, enabling the substrate potential to be set independently of the source potential of the transistor. It thereby becomes possible to modify the threshold voltage of the transistor or maintain a constant potential difference between the substrate potential and that of a gate input signal. Since the requirement for a substrate contact region within each source cell is eliminated, and the number of substrate contact cells can be fewer than that of the source cells, the chip area occupied by the transistor can be reduced by comparison with a prior art configuration providing such a substrate potential control capability.
* (“Rode et al., US Patent 11502191 B2”) discloses IC structures that implement field plates for III-N transistors in a form of electrically conductive structures provided in a III-N semiconductor material below the polarization layer (i.e., at the “backside” of an IC structure). In some embodiments, such a field plate may be implemented as a through-silicon via (TSV) extending from the back/bottom face of the substrate towards the III-N semiconductor material. Implementing field plates at the backside may provide a viable approach to changing the distribution of electric field at a transistor drain and increasing the breakdown voltage of an III-N transistor without incurring the large parasitic capacitances associated with the use of metal field plates provided above the polarization material. In addition, backside field plates may serve as a back barrier for advantageously reducing drain-induced barrier lowering.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898