Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendments and Arguments
Amendments and arguments provided on 02/11/2026 have been fully considered and are not found to place the application in a condition for allowance.
The applicant asserts that Vobs line does not provide a voltage similar to Vinit2 of the instant application because per Chae, Vobs can be varied but the Vinit2 “should be a constant voltage”. The Office respectfully disagrees and maintains that Vobs voltages provide an initialization or resetting voltage to N1. First, the claims nor the specifications include the language wherein Vinit2 is a constant voltage. Second, as seen in fig. 6A for example, Vobs is set to a constant voltage Vob1 during ACTP1, gradually changes to Vob2 during DIMP1 and then it is maintained at the constant level of Vob2. Accordingly, Vobs may be viewed as a constant voltage except for a specific period. When M4 is turned on according to S1i signal, N1 is set/reset/initialized to the voltage carried by Vobs. Accordingly, the Office maintains that the voltage of Vobs is analogous to Vinit2.
The applicant further asserts that the circuit of Chae “does not require the addition of such ‘second reset module’”. The Office respectfully finds this argument moot because Chae clearly teaches the “second reset module” as claimed. As noted above, N1 is set/reset to a specific voltage Vobs when M4 is turned on, accordingly this feature is taught by Chae.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 5 and 7-9 are rejected under 35 U.S.C. 103 as being unpatentable over Chae et al., US 2022/0358884 A1, hereinafter “Chae”, in view of Xia et al., US 2022/0366834 A1, hereinafter “Xia”.
Regarding claim 1, Chae teaches a pixel circuit (fig. 3, PX1, ¶ 69), comprising: a drive transistor (M1, ¶ 73) having a gate, a first electrode and a second electrode connected with a first node (N3), a second node (N1) and a third node (N2), respectively, wherein the drive transistor is configured to provide a drive signal to a light-emitting device (LD, ¶ 71-73); a data writing module (M2) connected with a first scan control signal terminal (S4i), a data signal terminal (Dj) and the second node (¶ 74), wherein the data writing module is configured to write a data signal provided by the data signal terminal to the second node under control of a first scan control signal provided by the first scan control signal terminal (¶ 74); a compensation adjustment module (M3) connected with a second scan control signal terminal (S2i), the first node, and the third node, wherein the compensation adjustment module is configured to control a conduction or disconnection between the first node and the third node under control of a second scan control signal provided by the second scan control signal terminal (¶ 75); a first reset module (M7) connected with a first reset control signal terminal (S3i), the first node and a first initialization signal terminal (Vint1, ¶ 84); wherein in one refresh frame period, when the compensation adjustment module is turned off, the first reset module is configured to write a first initialization signal provided by the first initialization signal terminal into the first node under control of a first reset control signal (fig. 10, see P2 period before P3 starts wherein while S2i is off, S3i is on); when the compensation adjustment module is turned on, the first reset module is configured to write the first initialization signal provided by the first initialization signal terminal into the first node and the third node under control of the first reset control signal (fig. 10, see the period wherein P2 and P3 overlap during which both S2i and S3i are turned on; also see ¶ 219), wherein the first reset module comprises a first transistor (fig. 3, M7), the gate of the first transistor is connected with the first reset control signal terminal, the first electrode of the first transistor is connected with the first initialization signal terminal, and the second electrode of the first transistor is connected with the gate of the drive transistor (fig. 3, see M7 configuration); the compensation adjustment module comprises a second transistor (M3), a gate of the second transistor is connected with the second scan control signal terminal, a first electrode of the second transistor is connected with the gate of the drive transistor, and a second electrode of the second transistor is connected with the second electrode of the drive transistor (fig. 3, see M3 configuration); wherein the pixel circuit further comprises a second reset module (fig. 3, M4, ¶ 76-77) connected with a second reset control signal terminal (S1i), a second initialization signal terminal (Vobs) and the second node and/or the third node (N1); the second reset module is configured to write a second initialization signal provided by the second initialization signal terminal to at least one of the second node and the third node under the control of the second reset control signal (¶ 76-78), in a first display mode (see fig. 5), the first display mode comprises one refresh frame period (fig. 5, ACTP) and at least on hold frame period (fig. 5, BLKP), and the hold frame period comprises an adjustment phase (see S1i active periods, ¶ 105-106).
Chae does not specifically teach that the first transistor and the second transistor are transistors of P-type low temperature polysilicon (LTPS) material, and the first transistor and the second transistor are dual-gate transistors with nodes of channel connection region.
Xia, however, clearly teaches that the first transistor (fig. 10, T1) and the second transistor (fig. 10, T2) are transistors of P-type low temperature polysilicon (LTPS) material (¶ 112), and the first transistor and the second transistor are dual-gate transistors (¶ 48) with nodes of channel connection region (fig. 10, see N5 and N6, ¶ 46 and 54).
It would have been obvious to one of ordinary skill in the art before the filing date of the invention to combine the teachings of Chae in view of Xia. The references provide similar pixel circuits and Xia clearly teaches in ¶ 111 that “When the transistors are of the same type, manufacturing difficulty of the display panel can be reduced”. Further, Xia teaches in ¶ 71 that such a dual-gate configuration provides stability or “causes the potential of the first node N1 to maintain dynamic balance”. Accordingly, one would have been motivated to make such a combination in order to facilitate the manufacturing of the pixel circuit while enhancing stability, which per ¶ 102 of Xia enhances the quality of the display device by reducing flicker.
Regarding claim 2, Chae teaches that in one refresh frame period, the time for which the second scan control signal controls the compensation adjustment module to be turned on is greater than or equal to four times the time for which the first scan control signal controls the data writing module to be turned on (fig. 10, see the turn-on periods of S2i and S4i).
Regarding claim 3, Chae teaches that in one refresh frame period, after the data writing module is turned off under control of the first scan control signal (fig. 10, see turning off of S4i at the rising edge of S4i), the compensation adjustment module continues to be turned on under control of the second scan control signal (fig. 10, see S2i), the time for which the second scan control signal controls the compensation adjustment module to continue to be turned on is greater than or equal to three times the time for which the first scan control signal controls the data writing module to be turned on (see fig. 10).
Regarding claim 5, Chae teaches that the data writing module comprises a fourth transistor (M2), a gate of the fourth transistor is connected with the first scan control signal terminal, a first electrode of the fourth transistor is connected with the data signal terminal, and a second electrode of the fourth transistor is connected with the first electrode of the drive transistor (fig. 3, see M2 configuration).
Regarding claim 7, Chae teaches that the pixel circuit further comprises a light-emitting control module, the light-emitting control module comprises a fifth transistor (fig. 3, M5) and a sixth transistor (fig. 3, M6); a gate of the fifth transistor is connected with a light-emitting control signal terminal (Ei), a first electrode of the fifth transistor is connected with a first power supply voltage terminal (VDD), and a second electrode of the fifth transistor is connected with the first electrode of the drive transistor (N1); a gate of the sixth transistor is connected with the light-emitting control signal terminal, a first electrode of the sixth transistor is connected with the second electrode of the drive transistor, a second electrode of the sixth transistor is connected with a first electrode of the light-emitting device (fig. 3, see M6 configuration), and the connecting node is a fourth node (N4); the light-emitting control module is configured to control a conduction or disconnection between the first power supply voltage terminal and the second node, and to control a conduction or disconnection between the third node and the fourth node under a light-emitting control signal provided by the light-emitting control signal terminal, and to provide a drive signal generated by the drive module to the light-emitting device (fig. 3, ¶ 81-82).
Regarding claim 8, Chae teaches that the pixel circuit further comprises a third reset module (fig. 3, M8) connected with a third reset control signal terminal (S1i), the fourth node (N4) and a third initialization signal terminal (Vint2); the third reset module is configured to write a third initialization signal into the fourth node under control of the third reset control signal (¶ 85-86).
Regarding claim 9, Chae teaches that the second reset control signal terminal and the third reset control signal terminal are controlled in response to a same gate signal, and the gate signal is the third reset control signal (see fig. 3 wherein both M4 and M8 are controlled by S1i).
Conclusion
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/SEPEHR AZARI/ Primary Examiner, Art Unit 2621