DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Claims
Claims 1, 3-8, 11-13, 15-21 and 24-26 are pending in the application and are currently being examined. Claims 1, 3, 6, 7, 11-13, 16-20, and 24 have been amended. Claims 2, 9, 10, 14, 22, and 23 have been canceled. New claims 25 and 26 have been added.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 7/23/2026 is being considered by the examiner.
Response to Arguments
Applicant’s arguments, see pages 12-14, filed 7/22/2026, with respect to the rejection(s) of claim(s) 1-8, 11-21, and 24 under U.S.C. 35 §102 and U.S.C. §103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in light of the amendments to the claims.
With respect to the objections to the specification, Examiner agrees that the amendments to the specification are sufficient and subsequently the objections have been withdrawn.
With respect to the objections to the drawings, Examiner agrees that the amendments to the drawings are sufficient and subsequently the objections have been withdrawn.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 3-5, 8, 11, 13, and 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fricker et al. (US 2019/0027466 A1, hereafter Fricker) in view of Gong et al. (US 2020/0227338 A1, hereafter Gong), and further in view of Kumar et al. (US 2021/0280495 A1, hereafter Kumar).
Regarding claim 1, Fig. 1 of Fricker teaches an electronic assembly comprising:
a system on a wafer (SoW) (100, [0029]) having a first side (top side of the plan view), the SoW comprising an array of integrated circuit dies (circuit layer, 125, [0037]);
Fricker is silent on a heat removing structure coupled to the first side of the SoW; and
a thermal interface structure comprising a thermal interface layer and an adhesion layer, the thermal interface layer positioned between the first side of the SoW and the heat removing structure, and the adhesion layer positioned between the heat removing structure and the thermal interface layer.
However, Fig. 2 of Gong teaches a similar device with a heat removing structure (240, [0033]) coupled to the first side of the electronic component (220); and
a thermal interface structure (101, [0021]) comprising a thermal interface layer (105, [0021]) and an adhesion layer (110, [0021]), the thermal interface layer (105) positioned between the first side of the electronic component (220) and the heat removing structure (240), and the adhesion layer (110) positioned between the heat removing structure (240) and the thermal interface layer (105).
While Gong specifies the heat removing structure is utilized on a system on chip device ([0032]), one of ordinary skill in the art would know to utilize the method of Gong on a system on a wafer, as the increased number of chips would create an increase in heat and thus require a heat removing structure. Kumar teaches in [0020] that a cooling structure, such as the one taught by Gong, would be utilized to prevent die damage in thermal enabling load systems. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system on wafer to include the cooling structure as taught by Gong in order to protect the dies in a packaged device from thermal damage, as taught by Kumar.
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Regarding claim 3, Fricker in view of Gong in view of Kumar teaches the assembly of Claim 1. Gong further teaches, wherein the thermal interface layer (101, [0021]) comprises a vertically aligned graphite layer ([0025]) that is aligned generally perpendicular to the first side of the system on wafer (100 of Fricker, [0029]). As the layer 105 can be the same size as layer 220 (described as the footprint of TIM stack 101, which includes layer 105, [0033]), this allows for vertical alignment of the layers (most directly shown in the combination of Fig. 1B and Fig. 2). With the layer 105 being deposited on top of layer 220, the alignment is also perpendicular to electronic component 220.
Regarding claim 4, Fricker in view of Gong in view of Kumar teaches the assembly of Claim 1. Gong further teaches wherein the thermal interface layer (101, [0021]) comprises a carbon nanotube layer ([0025]).
Regarding claim 5, Fricker in view of Gong in view of Kumar teaches the assembly of Claim 1. Gong further teaches, wherein a thickness of the thermal interface layer (101, [0021]) is greater than a thickness of the adhesion layer (110, [0021]) ([0023]).
Regarding claim 8, Fricker in view of Gong in view of Kumar teaches the assembly of Claim 1. Gong further teaches, wherein the adhesion layer (110, [0021]) comprises a metal adhesion layer ([0030]).
Regarding claim 11, Fricker in view of Gong in view of Kumar teaches the assembly of Claim 1. Gong further teaches, Fig. 1B further teaches a second adhesion layer (110, [0021]) between the first side of the SoW (top side in the plan view of 100 in Fricker, [0029]) and the thermal interface layer (105, [0021]).
Regarding claim 13, Fricker teaches a method of manufacturing an electronic assembly, the method comprising:
a first side of a system on a wafer (SoW) (top side of the plan view, 100, [0029]), the SoW comprising an array of integrated circuit dies (circuit layer, 125, [0037]);
Fricker is silent on providing (a) a thermal interface layer between a first side of a system on a wafer (SoW) and a heat removing structure and (b) an adhesion layer between the thermal interface layer and the heat removing structure, the SoW comprising an array of integrated circuit dies; and
applying pressure to bond the SoW and the heat removing structure by way of the thermal interface layer.
However, Fig. 2 of Gong teaches a similar method providing (a) a thermal interface layer (105, [0021]) between a first side (see annotated Fig. 2) of an electronic component (220, [0032]) and a heat removing structure (240, [0033]) and (b) an adhesion layer (110, [0021]) between the thermal interface layer (105) and the heat removing structure (240); and
applying pressure ([0041]) to bond the electronic component (220) and the heat removing structure (240) by way of the thermal interface layer (105).
While Gong specifies the heat removing structure is utilized on a system on chip device ([0032]), one of ordinary skill in the art would know to utilize the method of Gong on a system on a wafer, as the increased number of chips would create an increase in heat and thus require a heat removing structure. Kumar teaches in [0020] that a cooling structure, such as the one taught by Gong, would be utilized to prevent die damage in thermal enabling load systems. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system on wafer to include the cooling structure as taught by Gong in order to protect the dies in a packaged device from thermal damage, as taught by Kumar.
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Regarding claim 15, Fricker in view of Gong in view of Kumar teaches the method of Claim 13. Gong further teaches wherein a thickness of the thermal interface layer (101, [0021]) is greater than a thickness of the adhesion layer (110, [0021]) ([0023]).
Regarding claim 16, Fricker in view of Gong in view of Kumar teaches the method of Claim 13. Gong further teaches, wherein the adhesion layer (110, [0021]) comprises one of:
a horizontally aligned graphite layer that is aligned generally parallel with a first side of the SoW (100 of Fricker, [0029]);
a metal adhesion layer; or
a thermal grease layer. Gong teaches a metal adhesion layer in ([0030]).
Regarding claim 17, Fricker in view of Gong in view of Kumar teaches the method of Claim 13. Gong further teaches in Fig. 1B a second adhesion layer (110, [0021]) between the SoW (100 of Fricker, [0029]) and the thermal interface layer (105, [0021]), wherein the adhesion layer and the second adhesion layer comprise a same material. As both adhesion layers are denoted with 110, it can be reasonably assumed they comprise the same material.
Claim(s) 6 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fricker in view of Gong in view of Kumar as applied to claim 1 above, and further in view of Tseng et al. (US 2018/0247912 A1, hereafter Tseng).
Regarding claim 6, Fricker in view of Gong in view of Kumar teaches the assembly of Claim 1, Fig. 1B of Gong further teaches wherein the adhesion layer (110, [0021]) comprises a horizontally aligned layer that is aligned generally parallel to the first side of the SoW (100 of Fricker, [0029]). A horizontally aligned layer merely requires deposition atop another layer in a stack, and the adhesion layer is atop the electronic component, making it horizontally aligned.
Fricker in view of Gong in view of Kumar fails to teach the adhesion layer to be a graphite layer. However, Tseng teaches graphite being used as an adhesive to increase thermal conductivity of the adhesive layer ([0023]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the adhesive layer of Fricker in view of Gong in view of Kumar to be formed of graphite in order to form a conductive adhesive layer.
Regarding claim 7, Fricker in view of Gong in view of Kumar teaches the assembly of Claim 1, Fig. 1B of Gong further teaches, wherein the thermal interface layer (105, [0021]) comprises a vertically aligned graphite layer ([0025]) that is aligned generally perpendicular to the first side of the SoW (100 of Fricker, [0029]), and the adhesion layer (110, [0021]) comprises a horizontally aligned layer that is aligned generally parallel to the first side of the SoW (100 of Fricker, [0029]). As the layer 105 can be the same size as layer 220 (described as the footprint of TIM stack 101, which includes layer 105, [0033]), this allows for vertical alignment of the layers (most directly shown in the combination of Fig. 1B and Fig. 2). With the layer 105 being deposited on top of layer 220, the alignment is also perpendicular to electronic component 220. Similarly, a horizontally aligned layer merely requires deposition atop another layer in a stack, and the adhesion layer is atop the electronic component, making it horizontally aligned.
Gong fails to teach the adhesion layer to be a graphite layer. However, Tseng teaches graphite being used as an adhesive to increase thermal conductivity of the adhesive layer ([0023]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the adhesive layer of Fricker in view of Gong in view of Kumar to be formed of graphite in order to form a conductive adhesive layer.
Claim(s) 12 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fricker in view of Gong in view of Kumar as applied to claims 1 and 13 above, and further in view of Wan et al. (US 2020/0111720 A1, hereafter Wan).
Regarding claim 12, Fricker in view of Gong in view of Kumar teaches the assembly of Claim 1. Fig. 1B of Gong further teaches a control board (230, [0032]) coupled to a second side (see annotated Fig. 2) of the SoW (100 of Fricker, [0029]) opposite the first side (see annotated Fig. 2).
Gong fails to teach a second heat removing structure between the second side of the SoW and the control board.
However, Wan teaches a similar device in which a heat removing structure is between an electronic component and a control board (Fig. shows 112 and 607 not in contact, though [0056] says they can be in thermal contact with one another). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Fricker in view of Gong in view of Kumar to include the second heat removing structure between the electronic component and the control board to get the expected result of increased heat dissipation in the device.
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Regarding claim 18, Fricker in view of Gong in view of Kumar teaches the method of Claim 13. Fig. 1B of Gong further teaches the method of Claim 13, further comprising a control board (230, [0032]) coupled to a second side (see annotated Fig. 2) of the SoW (100 of Fricker, [0029]) opposite the first side (see annotated Fig. 2).
Gong fails to teach a second heat removing structure between the second side of the SoW and the control board.
However, Wan teaches a similar device in which a heat removing structure is between an electronic component and a control board (Fig. shows 112 and 607 not in contact, though [0056] says they can be in thermal contact with one another). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Gong to include the second heat removing structure between the electronic component and the control board to get the expected result of increased heat dissipation in the device.
Claim(s) 19-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fricker in view of Gong, in view of Kumar in further view of Bet-Shliemoun (US 2015/0279761 A1, hereafter Bet-Shliemoun).
Regarding claim 19, Fig. 1 of Fricker teaches a system on wafer (SoW) assembly comprising:
a SoW (100, [0029]) having a first side (top side of the plan view), the SoW comprising an array of integrated circuit dies (circuit layer, 125, [0037]).
Fricker is silent on a heat removing structure coupled to the SoW;
a thermal interface structure disposed between and bonding the first side of the SoW and the heat removing structure, the thermal interface structure comprising a thermal interface material.
However, Fig. 2 of Gong teaches a similar device with a heat removing structure (240, [0033]) coupled to the first side of the electronic component (220); and
a thermal interface structure (101, [0021]) disposed between and bonding the first side of the electronic component (220) and the heat removing structure (240), the thermal interface structure (101) comprising a thermal interface material (105, [0021]).
While Gong specifies the heat removing structure is utilized on a system on chip device ([0032]), one of ordinary skill in the art would know to utilize the method of Gong on a system on a wafer, as the increased number of chips would create an increase in heat and thus require a heat removing structure. Kumar teaches in [0020] that a cooling structure, such as the one taught by Gong, would be utilized to prevent die damage in thermal enabling load systems. Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the system on wafer to include the cooling structure as taught by Gong in order to protect the dies in a packaged device from thermal damage, as taught by Kumar.
Fricker in view of Gong in view Kumar fail to teach a groove between the SoW and the heat removing structure, at least a portion of the thermal interface material is disposed in the groove.
However, Fig. 2 of Bet-Shliemoun teaches a similar wafer assembly comprising:
a groove (tracks 134, 136, [0024]) between the wafer (124) and the heat removing structure (120), at least a portion of the thermal interface material (131) is disposed in the groove (134, 136).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Fricker in view of Gong in view Kumar to include the groove of Bet-Shliemoun in order to increase the effective surface area for heat transfer, as Bet-Shliemoun teaches in [0024].
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Regarding claim 20, Fricker in view of Gong in view Kumar in view of Bet-Shliemoun teaches the assembly of Claim 19, wherein the groove (tracks 136, [0024]) is in a surface of the SoW (100 of Fricker, [0029]).
Regarding claim 21, Fricker in view of Gong in view Kumar in view of Bet-Shliemoun teaches the assembly of Claim 19, wherein the groove (tracks 134, [0024]) is in a surface of the heat removing structure (120, [0022]).
Regarding claim 25, Fricker in view of Gong in view of Kumar in view of Bet-Shliemoun teaches the assembly of Claim 19. Gong further teaches, wherein the thermal interface structure (101, [0021]) comprises a thermal interface layer (101 comprises 101) comprises a vertically aligned graphite layer ([0025]) that is aligned generally perpendicular to the first side of the system on wafer (100 of Fricker, [0029]). As the layer 105 can be the same size as layer 220 (described as the footprint of TIM stack 101, which includes layer 105, [0033]), this allows for vertical alignment of the layers (most directly shown in the combination of Fig. 1B and Fig. 2). With the layer 105 being deposited on top of layer 220, the alignment is also perpendicular to electronic component 220.
Claim(s) 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fricker in view of Gong in view Kumar in view of Bet-Shliemoun as applied to claim 19 above, and further in view of Wan.
Regarding claim 24, Fricker in view of Gong in view Kumar in view of Bet-Shliemoun teaches the assembly of Claim 19, further comprising a control board (116, [0022]) coupled to a second side (see annotated Fig. 2) of the wafer (124, [0023]) opposite the first side (see annotated Fig. 2).
Bet-Shliemoun fails to teach a second heat removing structure between the second side of the electronic component and the control board.
However, Wan teaches a similar device in which a heat removing structure is between an electronic component and a control board (Fig. shows 112 and 607 not in contact, though [0056] says they can be in thermal contact with one another). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Fricker in view of Gong in view Kumar in view of Bet-Shliemoun to include the second heat removing structure between the electronic component and the control board to get the expected result of increased heat dissipation in the device.
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Claim(s) 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fricker in view of Gong in view of Kumar as applied to claim 1 above, and further in view of Lai et al. (US 2020/0251397 A1, hereafter Lai).
Regarding claim 26, Fricker in view of Gong in view of Kumar teaches the assembly of Claim 1. Fricker further teaches the SoW can have fan-out connections for interconnecting the dies [0053]. However, Fricker in view of Gong in view of Kumar fail to teach SoW is an Integrated Fan-Out wafer comprising a plurality of routing layers over the array of integrated circuit dies.
However, Lai teaches in Fig. 10 a similar SoW to Fricker in view of Gong in view of Kumar in which the SOW is an integrated SoW is an Integrated Fan-Out wafer [0012] comprising a plurality of routing layers (1072, [0069]) over the array of integrated circuit dies (50, [0069]). Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Fricker in view of Gong in view of Kumar to include a Fan-Out wafer comprising a plurality of routing layers in order to get the expected result of communication to other dies within the device or other components outside the wafer assembly.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SAMMANTHA K SALAZ whose telephone number is (571)272-2484. The examiner can normally be reached Monday - Friday 8:00am-5:00pm.
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/SAMMANTHA K SALAZ/Examiner, Art Unit 2892
/LEX H MALSAWMA/Primary Examiner, Art Unit 2892
