DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/06/2026 has been entered.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "312" and "313" have both been used to designate the same part on Figures 1-3 and 6. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claims 8 and 10 are objected to because of the following informalities:
As per claim 8, the limitation “the second circuit units” should be “the plurality of second circuit units”.
As per claim 10, the limitation “the second output units” should be “the plurality of second output units”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-10 and 14-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 recites the limitation “the winding line segments”. There is insufficient antecedent basis for this limitation in the claim.
Claim 8 recites the limitation “the first circuits units”. There is insufficient antecedent basis for this limitation in the claim.
Claim 10 recites the limitation “the first output units”. There is insufficient antecedent basis for this limitation in the claim.
Claim 14 recites the limitation “the first circuit units”. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-13, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kang (US 20230040529).
As per claims 1 and 18, Kang discloses (a display device (Abstract), comprising) a display panel (Fig. 1, #100; [0084]), wherein the display panel (#100) comprises a display region (#DA), a bonding region (Figs. 6-7; i.e., region with display driver #200), and a circuit region (i.e., region with demultiplexer #400 and region with contact pads #CTP) located between the display region (#DA) and the bonding region ([0084]-0085]);
the display panel (#100) further comprises:
a driver assembly (#200) disposed in the bonding region and comprising a first output unit (#210; [0093]);
a multiplex circuit (#400) disposed in the circuit region and comprising a first circuit unit (#ST1; [0106]);
a connection line connected between the driver assembly (#200) and the multiplex circuit (#400) and comprising a first connection line (#FOL) connected between the first circuit unit (#ST1) and the first output unit (#210; [0133]); and
a plurality of pixel units (#SP) disposed in the display region (#DA) and connected to the multiplex circuit (#400; [0103]-[0106]);
wherein the first connection line (#FOL) comprises a winding line segment (#CL1b) distributed in the display region ([0105]-[0106]; [0133]-[0134]);
wherein (Fig. 7 discloses) the first connection line (#FOL) further comprises a first line segment (i.e., first line segment of #FOL) extending from the bonding region (i.e., region with display driver #200) to the circuit region (i.e., region with demultiplexer #400) and connected to the first output unit (#210), and a second line segment (#CL1c) extending from a boundary of the display region (#DA) to the circuit region (i.e., region with contact pads #CTP) and connected to the first circuit unit (#ST1), and the winding line segment (#CL1b) is directly connected between the first line segment (i.e., first line segment of #FOL) and the second line segment (#CL1c; [0106]);
wherein (Fig. 7 discloses) the first line segment (i.e., first line segment of #FOL) is located in the circuit region (i.e., region with demultiplexer #400) and out of the display region (#DA), and the winding line segment (#CL1b) is located in the display region (#DA) and out of the circuit region (i.e., region with demultiplexer #400).
However, Kang does not teach the second line segment is located in the circuit region and out of the display region. Official Notice is taken that it would have been an obvious to one of ordinary skill to have the second line segment is located in the circuit region and out of the display region since it has been held that mere rearrangement of parts of an invention in a way that does not modify the operation of the device is not a patentable improvement. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) and In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975).
As per claims 3 and 20, Kang discloses the display panel (device) according to claim 1 (claim 18) , wherein (Fig. 7 discloses) the first line segment (i.e., first line segment of #FOL) and the second line segment (#CL1c) extend from a first direction (i.e., Y direction), and the first direction is a direction pointing from the bonding region to the display region, the first line segment and the second line segment are staggered along the first direction (i.e., Y direction), the winding line segment (#CL1b) is distributed in a bending shape in the display region ([0105]-[0106]).
As per claim 4, Kang discloses the display panel according to claim 1, wherein (Fig. 7 discloses) the first output unit (#210) and the first circuit unit (#ST1) are staggered along a first direction (i.e., Y direction) pointing from the bonding region to the display region.
As per claim 5, Kang discloses the display panel according to claim 1, wherein the multiplex circuit (#400) comprises a plurality of second circuit units (#ST2), the first circuit unit (#ST1) and the plurality of second circuit units (#ST2) are arranged along a second direction (i.e., X direction), the second direction (i.e., X direction) intersects a first direction (i.e., Y direction) pointing from the bonding region to the display region, the driver assembly (#200) comprises a plurality of second output units (#220-260), the first output unit (#210) and the plurality of second output units (#220-260) are arranged along the second direction (i.e., X direction), the connection line further comprises a plurality of second connection lines (#FOL);
wherein the plurality of second connection lines (#FOL) extend along the first direction (i.e., Y direction) and are connected between the plurality of second circuit units (#ST2) and the plurality of second output units (#220-260).
As per claim 6, Kang discloses the display panel according to claim 5, wherein (Fig. 7 discloses) the first connection line of the connection line is multiple (#FOL), and the winding line segments (#CL1) of the plurality of first connection lines are not intersected.
As per claim 7, Kang discloses the display panel according to claim 6, wherein the connection line comprises at least one winding line set (#CL1a-c), each of the at least one winding line set comprises a plurality of the winding line segments, and in each of the at least one winding line set, the plurality of winding line segments are sleeved one by one ([0106]).
As per claim 8, Kang discloses the display panel according to claim 5, wherein (Fig. 7 discloses) a length of the bonding region (i.e., region with display driver #200) along the second direction (i.e., X direction) is less than the circuit region (i.e., region with demultiplexer #400) along a length of the second direction (i.e., X direction), and the circuit region (i.e., region with demultiplexer #400) comprises a first sub-region (i.e., upper region) and a second sub-region (i.e., lower region), the second sub-region (i.e., lower region) and the bonding region (i.e., region with display driver #200) are aligned with each other along the first direction (i.e., Y direction), and the first sub-region (i.e., upper region) is connected to the second sub-region (i.e., lower region) along the second direction (i.e., X direction);
wherein the first circuit units (#ST1) are distributed in the first sub-region (i.e., upper region), and the second circuit units (#ST2) are distributed in the second sub-region (i.e., lower region).
As per claim 9, Kang discloses the display panel according to claim 8, wherein (Fig. 7 discloses) the plurality of second output units (#220-260) comprise an edge second output unit (#220) located at an end portion of the driver assembly (#200), the first output unit (#210) connected to the first circuit unit (#ST1) away from a side of the second sub-region is located on a side of the first output unit (#210) connected to the first circuit unit (#ST1) near a side of the second sub-region in which the side of the first output unit (#ST1) is away from a side of the edge second output unit (#220).
As per claim 10, Kang discloses the display panel according to claim 9, wherein (Fig. 6 discloses) in the driver assembly (#200), in the plurality of second output units (#220-260) near the edge second output unit (#220), one of the first output units (#230) is located between adjacent two of the second output units (#220, 240), and in the second output units (#230-260) away from the edge second output unit (#220), the second output units (#230-260) are disposed adjacently.
As per claim 11, Kang discloses the display panel according to claim 8, wherein (Fig. 7 discloses) a length of the winding line segment (#CL1) of the first connection line connected to the first circuit unit (#ST1) away from a side of the second sub-region is greater than a length of the winding line segment of the first connection line connected to the first circuit unit near a side of the second sub-region.
As per claim 12, Kang discloses the display panel according to claim 5, wherein (Fig. 6 discloses) the plurality of second circuit units (#ST2) are aligned with the plurality of second output units (#220-260) along the first direction (i.e., Y direction).
As per claim 13, Kang discloses the display panel according to claim 5, wherein (Fig. 3 discloses) the plurality pixel units (#SP) comprises a plurality of pixel unit sets (#SPR, SPG, SPB) arranged along the second direction (i.e., X direction), and each of the plurality of pixel unit sets comprises the plurality of the pixel units arranged along the first direction (i.e., Y direction);
wherein (Fig. 7 discloses) one of the plurality of pixel unit sets (#SPR, SPG, SPB) along the first direction (i.e., Y direction) is aligned with one of the first circuit units (#ST1) or one of the plurality of second circuit units (#ST2).
Claims 14-17 are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of Fujii (US 20160071459).
As per claim 14, Kang discloses the display panel according to claim 13, wherein one of the plurality of data line sets (Fig. 7, #DL) along the first direction (i.e., Y direction) is connected to a corresponding one of the first circuit units or a corresponding one of the plurality of second circuit units (#ST2; [0133]-[0134]).
However, Kang does not explicitly teach the display panel further comprises a plurality of data line sets, one of the plurality of data line sets is connected to one of the plurality of pixel unit sets, each of the plurality of data line sets comprises at least two data lines extending along the first direction, and the at least two data lines are connected to the plurality of pixel units of a corresponding one of the plurality of pixel unit sets.
Fujii teaches the display panel (Fig. 3, #600) further comprises a plurality of data line sets (#D1-Dm), one of the plurality of data line sets is connected to one of the plurality of pixel unit sets (#R, G, B pixels), each of the plurality of data line sets comprises at least two data lines extending along the first direction (i.e., Y direction), and the at least two data lines are connected to the plurality of pixel units of a corresponding one of the plurality of pixel unit sets ([0075]-[0084]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the display panel of Kang configured according to Fujii so as to provide data signals having a voltage signal level are applied to pixels connected to an immediately preceding scan line in response to a gate-on signal applied to the scan line (Fujii: [0085]).
As per claim 15, Kang in view of Fujii discloses the display panel according to claim 14, wherein the display panel (Kang: Fig. 8, #100) comprises a substrate (Kang: #SUB), and a thin film transistor layer disposed on the substrate (Kang: [0113]-[0116]), the first circuit unit (Fujii: #Mr1) comprises a plurality of first multiplex thin film transistors located in the thin film transistor layer, and the second circuit unit (Fujii: #Mg1) comprises a plurality of second multiplex thin film transistors located in the thin film transistor layer (Fujii: [0081]-[0082]; where the thin film transistor layer is inherently present);
wherein one of the first connection lines (Kang: #FOL) is connected to source electrodes of the plurality of first multiplex thin film transistors (Kang: #ST1), one of the at least two data lines (Fujii: #D1) is connected to a drain electrode of one of the plurality of first multiplex thin film transistors (Fujii: #Mr1), one of the second connection lines (Kang: #FOL) is connected to source electrodes of the plurality of second multiplex thin film transistors (Fujii: #Mg1), one of the at least two data lines (Fujii: #D2) is connected to a drain electrode of one of the plurality of second multiplex thin film transistors (Fujii: #Mg1).
As per claim 16, Kang in view of Fujii discloses the display panel according to claim 15, wherein the display panel further comprises a conductive layer (Kang: #CL1b) disposed on a side of the thin film transistor layer (Kang: #TFT) away from the substrate (Kang: #SUB) and a light emitting device layer (Kang: #ED) disposed on a side of the conductive layer away from the thin film transistor layer (Kang: [0122]-[0124]);
wherein the conductive layer (Kang: #CL1b) comprises the first line segment, the second line segment, and the winding line segment (Kang: [0122]).
As per claim 17, Kang in view of Fujii discloses the display panel according to claim 15, wherein the second line segment (Kang: #FOL1) extends from a boundary of the display region (Kang: #DA) to the first circuit unit (Kang: #ST1) and is connected to source electrodes of the first multiplex thin film transistors (Kang: #ST1).
However, the prior art of Kang and Fujii do not teach the first line segment partially overlaps the second circuit unit. Official Notice is taken that it would have been an obvious to one of ordinary skill to have the first line segment partially overlaps the second circuit unit since it has been held that mere rearrangement of parts of an invention in a way that does not modify the operation of the device is not a patentable improvement. In re Japikse, 181 F.2d 1019, 86 USPQ 70 (CCPA 1950) and In re Kuhle, 526 F.2d 553, 188 USPQ 7 (CCPA 1975).
Response to Arguments
Applicant’s arguments with respect to claims 1 and 18 have been considered but are moot because of the new grounds of rejection as presented above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nelson Lam whose telephone number is (571)272-8044. The examiner can normally be reached 1pm-9pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ke Xiao can be reached at 571 272-7776. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Nelson Lam/Examiner, Art Unit 2627
/KE XIAO/Supervisory Patent Examiner, Art Unit 2627
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