Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
To facilitate consideration of any amendment that may be presented in response to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application that clearly support the amendment.
DETAILED ACTION
Claims 1--20 are pending in this application. Claims 1 and 14 are independent.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The Information Disclosure Statements (IDS) submitted on 11/16/23 by the applicant have been received and fully considered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20, as best understood (see the 112(b) rejection above), are rejected under 35 U.S.C. 103 as being unpatentable over Choi et a. (US 10,643,705) in view of Miller (US 2011/0303354), and further in view of Wang (US 11,526,285).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Claim 1
• Yu (’255) discloses a memory cell array unit organized in a matrix, with global/local bit lines and global/local word lines (col. 5, lines 10–40; Fig. 3). Each unit has selection circuits (connection units) coupling local word/bit lines to global lines.
• Stansfield (’351) teaches controlling global/local bit line discharge with biasing and adjacency logic (col. 7, lines 15–40). This directly suggests the second connection unit selecting a bit line “based on address information” from nearby memory units, to manage hierarchical selection and avoid conflicts.
• Thus, the combination yields: (i) multiple units in matrix form; (ii) global BL/WL; (iii) memory cell arrays at intersections; (iv) connection units; and (v) selection based on adjacent-unit info. Motivation: predictable improvement in array scalability and read stability.
Claim 2
• Scheuerlein (’925) discloses storing set/reset bias info in control logic to determine which word lines to enable (¶ [55]–[65]).
• Combined with Yu’s storage/address units, this teaches a storage unit holding set/reset info, with word-line connection set accordingly.
Claim 3
• Scheuerlein further teaches setting a bias condition of selected word lines based on read data and stored info to improve PCM reliability (¶ [67], Fig. 4).
• Thus, first connection unit applying bias condition based on storage unit and read data is directly suggested.
Claim 4
• Stansfield discloses adjusting bit-line bias condition depending on adjacent word-line biasing, to prevent sneak currents (col. 9, lines 20–45).
• This corresponds to the second connection unit biasing the selected bit line “based on bias of the selected word line obtained from adjacent memory units.”
Claim 5
• Yu discloses hierarchical arrangement: multiple first WL/BL within each unit, and second WL/BL overlapping with adjacent units (col. 5–6, Figs. 3–4). Connection units (switches) couple WLs and BLs to global lines.
• Thus, Yu provides third/fourth connection units for WLs, fifth/sixth for BLs, exactly as claimed.
Claim 6
• Combination of Scheuerlein + Stansfield shows setting WL/BL bias based on stored set/reset info, read data, and adjacent-unit bias conditions. Motivation: reduce sneak current errors and improve read accuracy in high-density cross-point memory.
As for claim 2, the PCM-based memory device for DNN according to claim 1, wherein the memory controller maps a resistance state level with the highest stability to a resistance state level with the lowest stability among the plurality of resistance state levels of the memory cell.
Choi discloses a PCM-based memory device comprising a cell array with multi-level storage of weights. Miller discloses mapping bit patterns to memory states according to frequency of occurrence, thereby optimizing reliability. Miller further teaches explicitly mapping frequent patterns to the most stable states first (Miller, ¶ [68]).
Citation of Relevant Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Applicants are directed to consider additional pertinent prior art included on the Notice of References Cited (PTOL 892) attached herewith.
Conclusion
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HIEN N. NGUYEN
Primary Examiner
Art Unit 2824
/HN/
September 30, 2025
/HIEN N NGUYEN/Primary Examiner, Art Unit 2824