DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 2013/03/16, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 2025/07/29 and 2026/06/29 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: "Battery Pack Voltage Measurement Circuit Having Overvoltage-Protected Switch and Method of Operating the Circuit to Measure Battery Pack Voltage".
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 3, 5 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites the limitation "R3" in Equation 1. There is insufficient antecedent basis for this limitation in the claim: R3 is never introduced as an element of Claim 1 or Claim 3, and is not tied to any claimed structure.
Claim 5 recites the limitation " the relay resistor" in the third limitation. There is insufficient antecedent basis for this limitation in the claim: Claim 5 only introduces "a relay element," never "a relay resistor".
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 1 – 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over BOLDUC (US 2015/0130471 A1), in view of KISHINO (JP 2014-153129 A).
In re claim 1, BOLDUC discloses a battery pack voltage measurement circuit (¶[0022]: battery pack voltage measurement) comprising:
a first resistor (FIG. 3: high-side resistor 76);
a relay circuit (FIG. 3: evaluation switch 75);
a second resistor (FIG. 3: low-side resistor 77); and
an ADC output circuit (FIG. 3; ¶[0026]: A/D input 81 of battery monitoring IC 66), wherein the relay circuit, the first resistor, the ADC output circuit, and the second resistor are sequentially connected in series between a power supply voltage terminal to which a voltage of a battery pack is applied and a ground voltage terminal (FIG. 3; ¶s [0023, 0025]: switch 75, resistors 76/77, and A/D input 81 connected in series between positive bus 61 and negative bus 62).
BOLDUC does not expressly disclose wherein the relay circuit comprises a relay element and a relay resistor in parallel.
KISHINO teaches wherein the relay circuit comprises a relay element and a relay resistor in parallel (FIG. 1; ¶[0019]: resistor R1 in parallel with switch 30a).
It would have been obvious for a PHOSITA to add a relay resistor in parallel with the relay element, as taught by KISHINO's voltage-limiting circuit, and to rearrange the first and second resistors relative to the relay element as an obvious rearrangement of parts, in order to limit the voltage the relay element experiences while open and thereby permit use of a lower-voltage-rated relay element.
In re claim 2, BOLDUC is silent to wherein when the relay element is turned OFF, a voltage applied to both ends of the relay element is the same as a voltage applied to both ends of the relay resistor.
KISHINO teaches wherein
when the relay element is turned off (¶[0026]; FIG. 2(a): switches 30a/30b in disconnected “off” state), a first voltage applied to both ends of the relay element is the same as a second voltage applied to both ends of the relay resistor (¶[0019]; FIG. 1: R1 connected in parallel to switch 30a; voltage across parallel elements necessarily equal).
It would have been obvious for a PHOSITA to recognize that the relay resistor necessarily equalizes the voltage across the relay element and the relay resistor when the relay element is open, as an inherent electrical consequence of the parallel connection KISHINO teaches.
In re claim 3, BOLDUC is silent to wherein a resistance value
R
r
of the relay resistor to satisfy the following,
R
r
(
R
1
+
R
2
+
R
3
)
×
V
0
<
V
l
i
m
[Equation 1]
wherein,
R
1
and
R
2
are resistance values of the first and second resistors, respectively,
V
l
i
m
is an allowable voltage value of the relay element, and
V
0
is a voltage value of the battery pack.
KISHINO teaches the following equation
V
s
1
=
B
×
R
1
R
1
+
R
2
+
R
3
[Equation 1.1]
(¶s [0026 – 0027]: where
V
s
1
is the voltage applied to switch 30a,
R
1
is the resistor connected in parallel with switch 30a (the relay resistor),
R
2
and
R
3
are the other two resistors in the series voltage-limiting circuit, and
B
is the battery voltage).
It would have been obvious for a PHOSITA to size the relay resistor's value relative to the first and second resistors according to KISHINO's disclosed voltage-ratio relationship, in order to keep the voltage across the relay element below its allowable rating.
In re claim 4, BOLDUC is silent to wherein a resistance value
R
r
of the relay resistor to satisfy the following,
R
r
(
R
1
+
R
2
+
R
c
+
R
r
)
×
V
0
<
V
l
i
m
[Equation 2]
wherein,
R
1
,
R
2
, and
R
c
are first and second resistors and a resistance value of the ADC output circuit, respectively,
V
l
i
m
is an allowable voltage value of the relay element, and
V
0
is a voltage value of the battery pack.
KISHINO teaches the following equation
V
r
11
=
B
×
R
11
R
11
+
R
12
+
R
21
+
R
22
+
R
31
+
R
32
+
R
33
[Equation 2.1]
(¶s [0028 – 0029]: where
V
r
11
is the voltage applied across resistor
R
1
,
R
1
one of the two sub-resistors,
R
11
/
R
12
, that together form the parallel relay-protection resistor,
R
12
is its companion sub-resistor,
R
21
/
R
22
and
R
31
/
R
32
/
R
33
are the further sub-divided resistors making up the circuit's other two series resistor groups, and
B
is the battery voltage.).
It would have been obvious for a PHOSITA to apply KISHINO's more detailed multi-resistor voltage-ratio equation when sizing the relay resistor relative to the ADC output circuit's resistance, in order to keep the voltage across the relay element below its allowable rating.
In re claim 5, BOLDUC discloses a method for operating a battery pack voltage measurement circuit (Claim 5: electric-vehicle battery monitoring method), the method comprising:
dropping a voltage applied to measure a battery pack voltage (FIG. 4 step 102; ¶[0025]: resistors 76, 77 divide bus voltage);
determining an “on” state of a relay element (FIG. 4 steps 101–102; ¶[0026]: main micro commands/confirms activation of switch 75); and
detecting the battery pack voltage (FIG. 4 step 105; ¶[0026]: main micro converts digital value to battery pack voltage).
BOLDUC is silent to the method determining an “on” state of a relay element according to the battery pack voltage; setting a first voltage across the relay element to be the same as a second voltage across the relay resistor based on the result of determining the “on” state of the relay element.
KISHINO teaches a method comprising
determining an “on” state of a relay element according to the battery pack voltage (Equation 1; ¶s [0019, 0026 – 0027]: relay resistor R1 in parallel with the switch supplies a battery-voltage-dependent signal irrespective of switch state);
setting a first voltage across the relay element to be the same as a second voltage across the relay resistor (FIG. 1; ¶[0019]: R1 in parallel with switch 30a) based on the result of determining the “on” state of the relay element (FIG. 1, FIG. 2(a); ¶s [0019, 0026]: R1's parallel connection to switch 30a equalizes their voltages whenever switch 30a is off).
It would have been obvious for a PHOSITA to determine the relay element's on-state using the battery-voltage-dependent signal inherently produced by the relay resistor connected in parallel with the relay element, as KISHINO's Equation 1 ties that signal to the battery voltage while the switch is off.
In re claim 6, BOLDUC discloses a battery pack voltage measurement circuit (¶[0022]: battery pack voltage measurement) comprising:
a voltage drop circuit (FIG. 3: high-side resistor 76);
a relay circuit (FIG. 3: evaluation switch 75); and
an ADC output circuit (FIG. 3; ¶[0026]: A/D input 81 of battery monitoring IC 66, which receives the divided voltage and outputs the resulting digital value), wherein the voltage drop circuit, the relay circuit, and the ADC output circuit are connected in series between a power supply voltage terminal to which a voltage of a battery pack is applied and a ground voltage terminal (FIG. 3; ¶s [0023, 0025]: resistor 76 (voltage drop circuit), switch 75 (relay circuit), and A/D input 81 (ADC output circuit) connected in series, positive bus 61 to negative bus 62).
BOLDUC does not expressly disclose wherein the relay circuit comprises a relay element and a relay resistor in parallel.
KISHINO teaches wherein
the relay circuit comprises a relay element and a relay resistor in parallel (FIG. 1; ¶[0019]: resistor R1 in parallel with switch 30a).
It would have been obvious for a PHOSITA to add a relay resistor in parallel with the relay element, as taught by KISHINO's voltage-limiting circuit, and to rearrange the voltage drop circuit relative to the relay element as an obvious rearrangement of parts, in order to limit the voltage the relay element experiences while open and thereby permit use of a lower-voltage-rated relay element.
In re claim 7, BOLDUC does not expressly disclose wherein the voltage drop circuit comprises a resistor connected between the power supply voltage terminal and the relay circuit.
BOLDUC discloses wherein
the voltage drop circuit comprises a resistor connected between the relay circuit and the ADC output circuit (FIG. 3: resistor 76 connected in series with switch 75, between positive bus 61 and the A/D tap), wherein the voltage drop circuit is configured to drop a voltage applied to the power supply voltage terminal (¶[0025]: resistor 76 drops a portion of the voltage present at the power supply voltage terminal as current flows through the series divider).
It would have been obvious for a PHOSITA to position the resistor between the power supply voltage terminal and the relay circuit, as an obvious rearrangement of parts, since series voltage division is unaffected by the order of a resistor relative to a relay element.
In re claim 8, BOLDUC does not expressly disclose a resistor connected between the relay circuit and the ADC output circuit.
BOLDUC discloses the circuit further comprising:
a resistor connected between the ADC output circuit and the ground voltage terminal (FIG. 3: resistor 77 connected in series between the A/D tap and negative bus 62), wherein the resistor is configured to drop and divide a voltage applied to the relay circuit (¶[0025]: resistor 77 drops and further divides the voltage received from the relay circuit via resistor 76, completing the series divider to the ADC output circuit).
It would have been obvious for a PHOSITA to position the resistor between the relay circuit and the ADC output circuit, as an obvious rearrangement of parts, since series voltage division is unaffected by the order of a resistor relative to the ADC output circuit.
Prior Art Disclaimer
The prior art applied in this Office Action includes foreign patent documents that were originally published in languages other than English. Machine-generated translations of these documents were utilized to assess their relevance and content.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
KIM et al. (US 2020/0083732 A1): KIM discloses a resistor string connected in parallel across a switch (cathode switch 110) to enable voltage-based diagnosis of the switch's weld state, providing an alternative teaching for the parallel relay-resistor arrangement.
KAWAMURA (JP 2015-141028 A): KAWAMURA discloses balance resistors connected in parallel with each of several series-connected semiconductor relays, expressly to achieve high breakdown voltage without a high-breakdown-voltage relay — mirroring the applicant's own stated advantage.
LUO (US20190064285A1): LUO discloses a relay diagnosis circuit with a switch and two-resistor-network series divider between a battery pack voltage output and a reference terminal, feeding an ADC and processor, comparable to claims 1, 5, and 6's basic series elements.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHANN DJANAL-MANN whose telephone number is (571)272-4697. The examiner can normally be reached Monday - Thursday 8:00 - 17:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Drew Dunn can be reached at (571) 272-2312. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D. JOHANN DJANAL-MANN/ Examiner, Art Unit 2859
/DREW A DUNN/ Supervisory Patent Examiner, Art Unit 2859
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