DETAILED ACTION/EXAMINER’S COMMENT
This Office action responds to the amendments filed on 06/24/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Amendment Status
Applicant’s response filed on 06/24/2026 in reply to the non-final rejection mailed on 03/25/2026, has been entered. The present Office action is made with all previously suggested amendments being fully considered. Claims 21-23 are added. Accordingly, pending in this Office action are claims 1-23. Claim(s) 3-5, 8, & 11-15 are canceled. Claims 1, 2, 6, 7, 9, 10, & 16-23 will be examined in this Office action.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1, 2, 6, 7, 9, 10, & 16-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation “the chip support body protruding to an opposite side of the flexible substrate layer more than the chip support body protrudes to the plurality of chip-use terminals” in lines 21-23.
The first portion of the claim limitation “an opposite side of the flexible substrate layer” is unclear as to which side of the flexible substrate layer 10 is considered the “opposite side” as there is no side of the flexible substrate layer referenced as the opposite side or the context for an opposite side to be understood. Applicant’s drawings (see, e.g., figs. 1, 6, & 20) and specification (see, e.g., para.0030-0035, para.0126-00130) defines the flexible substrate layer 10 as an element of the organic EL display panels 50a & 50d. From the plan view of the figures, the flexible substrate layer is entirely beneath all elements claimed and the opposite side of the flexible substrate layer lacks context to establish where it is in the claimed device. As show in figs. 10-13, the chip support body Sa/Saa is vertically above the flexible substrate layer 10 and protrudes in all directions. The opposite side limitation is unclear as to where the chip support body is to protrude to.
The second portion of the claim limitation “the chip support body protrudes to the plurality of chip-user terminals” is unclear based on the previous limitations in the claim.
The limitations “a plurality of chip-use terminals is provided in a single row” & “the plurality of chip-use terminals includes, at least, a first chip-use terminal and a second chip-use terminal adjacent to the first chip-use terminal” do not allow for the first chip-use terminal and the second chip-use terminal to be one terminal 18g and one terminal 18h, respectively (or any other combination of terminals), because the single row for the other chip-use terminals in the plurality of chip-use terminals would be a diagonal line only including one terminal 18j.
Lines 20-21 establish “a chip support body is provided between the first chip-use terminal and the second chip-use terminal” positioning the chip support body to be between two chip-use terminals of the plurality of chip-use terminals in a single row.
The second portion of the claim limitation “the chip support body protrudes to the plurality of chip-use terminals” is unclear as to how the chip support body positioned in the single row of the plurality of chip-use terminals and is protruding to the same plurality of chip-use terminals it is a part of. The specifications do not mention where the chip support body is protruding to.
Finally, there is no support in the specification or figures that explains the relationship between chip support body protruding to the opposite side “more” than the chip support body protrudes to the plurality of chip-use terminals.
Claims 2, 6, 7, 9, 10, & 16-23 are rejected as depending on Claim 1.
Claim 2 recites the limitation “wherein the plurality of chip-use terminals is input terminals” and further shows the issues of the Claim 1 limitation. For the plurality of chip-use terminals to be input terminals 18j the first chip-use terminal and the second chip-use terminals must be 18j and an adjacent 18j and the chip support body Sb only has portions protruding away from the plurality of first chip-use terminals.
Claim 6 recites the limitation “wherein the non-overlapping portion has a larger width than a width of any other portion.” The current claim language does not define or explain what element the “any other portion” is supposed to be a part of and limit.
Claim 16 recites the limitation “wherein the plurality of chip-use terminals is provided in the single row along a shorter side of the chip-mounting portion.” The limitation is unclear as to whether it intends to redefine the position of the single row along the shorter side of the chip-mounting portion. Were that the case, the first chip-use terminal and second chip-use terminal would have to be one of three elements 18g, 18h, or 18j each. However, any selection of the three elements for the first chip-use terminal and the second chip-use terminal, as required by Claim 1, would not form the single row which all the chip-use terminals of the plurality of chip-use terminals are required to be in.
Response to Arguments
Applicant's arguments filed 06/24/2026, see pages 7-9, with regards to the rejection of claims 2-5, 8-12, 15, & 16 under 35 U.S.C. 112 (b) have been fully considered but are moot in view of the cancellation of claims 3-5, 8, & 11-15 and further rejections made under 35 U.S.C. 112 (b) in this Office action, see paragraphs xx. above.
Applicant’s arguments, see pages 9-12, with respect to the prior art rejections of claims 1, 2, 3, 6, 7, & 12-20 under 35 U.S.C. 103 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. In shows a similar structure to the display device of the application suitable for modifications to includes structures such as the chip support body. Yamashita (see, e.g., figs. 18-19) show a chip support body with an overlapping and non-overlapping portion with a chip mounting area to a display device. Moh (see, e.g., fig. 2) shows configurations for input and output pads of a display device. Ohara (see, e.g., fig. 4) shows configurations for a thin film transistor within a display device.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO JOSE RAMOS-DIAZ whose telephone number is (571) 270-5855. The examiner can normally be reached Mon-Fri 8am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Loke can be reached on 571-272-1657. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FERNANDO JOSE RAMOS-DIAZ/Examiner, Art Unit 2818
/STEVEN H LOKE/Supervisory Patent Examiner, Art Unit 2818
