The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
Applicant’s amendments and remarks filed 4/6/26 are acknowledged. Claims 1, 5, 6, and 10 have been amended. Claims 1 – 10 are pending.
Response to Amendments / Arguments
Applicant's amendments have obviated the previously raised rejections of claims 5 and 10 under 35 USC 112.
Applicant’s arguments regarding the amended claims versus the previously raised claim rejections under 35 USC 103 based on the Makino – Fujita combination have been fully considered but they are not persuasive, as detailed below.
Amended claim 1:
(a) Applicant argues (pp. 9 – 10 of Remarks) that the Makino – Fujita combination does not meet the limitations recited by amended claims 1 and 6.
The Examiner respectfully disagrees and notes the following:
(i) Notwithstanding Applicant’s remarks drawn to both Makino and Fujita, Applicant for the most part attempts to critique the references individually by pointing out alleged deficiencies of the individual references, instead of addressing the entire applied prior art combination. In this regard, Applicant is reminded that it is the Makino – Fujita combination, not the individual references, that is to teach expressly or render obvious all of the limitations recited by the claim. Applicant should address deficiencies (e.g., missing elements), if any, of the entire combination, not the individual references (MPEP 2145, Section IV).
(ii) As was detailed in the Office Action of 1/5/26, the essence of the Makino – Fujita combination is that a flip-chip mounting technique disclosed by Fujita (the teachings of the reference) is applicable to any particular design of a lithium niobate modulator chip, including a design disclosed by Makino in Fig. 6B.
(iii) An optical waveguide device (modulator) of the Makino – Fujita combination is illustrated in Figure A of the Office Action of 1/5/26 (and reproduced for the rejections provided below) and comprises the design of Makino in Fig. 6B, the design having (with reference to the notations used in Fig. 6B of Makino) a groove 123a penetrating through the upper cladding layer 123, and a bottom of the groove 123a exposes the optical waveguide layer 122 (“In the configuration example in FIG. 6B, an entire area of the portions (the recesses 123a) of the buffer layer 123 where the electrodes 111 are provided is etched. Further, the electrodes 111 are formed on the thin-film LN layer 122 (steps 122b) by vapor deposition, etc.” at para. 0061 of Makino, emphasis added). Thus, the device modulator of the Makino – Fujita combination fully meets the structural limitations recited by amended claim 1 and would be manufactured by a method fully meeting the step limitations recited by claim 6.
In light of the foregoing analysis, independent claims 1 and 6 are rejected as provided below, and so are the dependent claims for which Applicant does not provide any additional substantial arguments and which therefore stand or fall together with the respective independent claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 – 3, 5 – 8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Makino (US 2022/0050351 A1) in view of Fujita et al (JP 2006-284838).
Regarding claim 1, Makino discloses (Figs. 1 and 6B; Abstract; para. 0024 – 0029 and 0056 – 0069) an optical waveguide device (an optical waveguide Mach-Zehnder modulator whose general view is shown in Fig. 1 and cross-section (of one interferometer arm 102) in Fig. 6B), comprising:
an optical waveguide lamination 121,122,123 (as illustrated in Fig. 6B) that is disposed on an underlay 120 and comprises a lower cladding layer 121, an optical waveguide layer 122 and an upper cladding layer 123 (para. 0029) which are stacked in a first (vertical) direction, wherein the first (vertical) direction is perpendicular to a plane (a horizontal plane that is perpendicular to the plane of Fig. 6B and parallel to the top surface of 120, see Figure A below) in which the underlay 120 is located; and
a conductive structure 111 (modulating electrodes; para. 0027 and 0028) that is electrically connected with to the optical waveguide layer 122 and used for conducting an electric signal (a modulating voltage; para. 0028) to the optical waveguide layer 122, and
a groove 123a penetrating through the upper cladding layer 123, and a bottom of the groove 123a exposes the optical waveguide layer 122 (“In the configuration example in FIG. 6B, an entire area of the portions (the recesses 123a) of the buffer layer 123 where the electrodes 111 are provided is etched. Further, the electrodes 111 are formed on the thin-film LN layer 122 (steps 122b) by vapor deposition, etc.” at para. 0061 of Makino, emphasis added).
Makino does not detail that the disclosed optical modulation module can be used/deployed in an optical waveguide device by being flip-chip mounted to a circuit board (substrate) with electrical traces that are connected to a conductive structure and provide an electric signal for electro-optic modulation. However, Fujita discloses (Figs. 1 – 4; para. 0014 – 0018 and 0021) an optical waveguide device that comprises an optical waveguide Mach-Zehnder modulator (whose general view is shown in Fig. 3 as the same general modulator type as that in Makino) which is flip-chip mounted to a circuit board 20 with electrical traces that are connected to a conductive structure 14,15,16 (electrodes) and provide an electric signal for electro-optic modulation (as shown in Fig. 1). The optical waveguide device comprises a substrate 21 and an optical modulation module 10 (Mach-Zehnder modulator) electrically connected (by solder bumps 24,25,26) with the substrate 21;
wherein the optical modulation module 10 comprises:
an underlay 11, comprising a first (bottom) surface and a second (upper) surface which are provided opposite to each other, wherein the first (bottom surface) surface is relatively close to the substrate 21, and the second (upper) surface is relatively far away from the substrate 21;
an optical waveguide lamination 12,13, which comprises a lower cladding layer (defined by an upper portion of 11), an optical waveguide 13b,13c and an upper cladding layer 12 which are stacked in a first (vertical) direction, wherein the first (vertical) direction is perpendicular to a plane (a horizontal plane perpendicular to the plane of Fig. 1) in which the underlay 11 is located; and
a conductive structure 14,15,16,24,25,26 (modulating electrodes and solder bumps).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the optical waveguide device/modulator in Fig. 6B of Makino can be used/deployed in an optical waveguide device, in accordance with the teachings of Fujita, by being flip-chip mounted to a circuit board with electrical traces that are connected to conductive structure and provide the electric signal for electro-optic modulation. The motivation for such flip-chip packaging arrangement is that the modulator footprint can be miniaturized (para. 0009 and 0013 of Fujita). Furthermore, multiple devices can be integrated on the same circuit board.
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The optical waveguide device of the Makino – Fujita combination is illustrated in Figure A below which is produced by flipping the modulator embodiment in Fig. 6B of Makino upside down and mounting it on a circuit board by using solder bumps 24,25,26, as taught by Fujita.
Figure A. The optical waveguide device of the Makino – Fujita combination. The entire modulator cross-section (both interferometer arms 102,103 in Fig. 1 of Makino) is shown.
As seen in Figure A, the optical waveguide device of the Makino – Fujita combination comprises:
a substrate 21 and an optical modulation module electrically connected with the substrate 21 (by solder bumps 24,25,26, as identified in Fig. 1 of Fujita);
wherein the optical modulation module comprises:
an underlay 120, comprising a first (lower) surface and a second (upper) surface which are provided opposite to each other, wherein the first (lower) surface is relatively close to the substrate 21, and the second (upper) surface is relatively far away from the substrate 21;
an optical waveguide lamination 121,122,123, which is located between the first (lower) surface of the underlay 120 and the substrate 21, and comprises a lower cladding layer 121, an optical waveguide layer 122 and an upper cladding layer 123 which are stacked in a first (vertical) direction, wherein the first (vertical) direction is perpendicular to a plane in which the underlay 120 is located (a horizontal plane perpendicular to the plane of Figure A), and the lower cladding layer 121 is located between the first (lower) surface of the underlay 120 and the optical waveguide layer 122 (as seen in Figure A); and
a conductive structure 11,25,26, which is located between the optical waveguide layer 122 and the substrate 21, and is electrically connected with the optical waveguide layer 122, being used for conducting an electric signal (voltage for electro-optic modulation) to the optical waveguide layer 122.
In light of the foregoing analysis, the Makino – Fujita combination teaches expressly or renders obvious all of the recited limitations.
Alternatively, the teachings of Makino (use of a thin film of electro-optic material for modulators) can be applied to modify the modulator structure of Fujita (a modulator in bulk electro-optic material) and provide an additional/alternative ground of rejections.
As an aside and relevant comment to the claims, it is also noted that the optical waveguide device of the Makino – Fujita combination, as illustrated in Figure A, has essential structural features substantially similar/identical to those in Fig. 1a of the instant application, i.e., an optical modulation module 120 flipped chip mounted on a substrate 110 (circuit board) and electrically connected to it by using solder bumps 126 (para. 0092 of the instant specification).
Regarding claim 6, the teachings of Makino and Fujita combine (see the arguments and motivation for combining, as provided above for claim 1) to teach expressly or render obvious all of the recited step limitations of a corresponding method of manufacturing the contemplated optical waveguide device, as detailed above for claim 1, including a step of forming a groove 123a penetrating through the upper cladding 123, wherein the bottom of the groove 123a exposes the optical waveguide layer 122 (according to Fig. 6B of Makino; “In the configuration example in FIG. 6B, an entire area of the portions (the recesses 123a) of the buffer layer 123 where the electrodes 111 are provided is etched. Further, the electrodes 111 are formed on the thin-film LN layer 122 (steps 122b) by vapor deposition, etc.” at para. 0061, emphasis added).
As an aside, the following is also noted:
(i) The modulator cross-section in Fig. 6B of Makino is substantially similar/identical to the modulator cross-section in Fig. 4f of the instant application, aside from solder bumps 126 (which correspond to solder bumps 24,25,26 in Fig. 1 of Fujita).
(ii) The step limitations include only the generic steps of “providing” and “forming” without any particular processes defined.
Regarding claims 2 and 7, the Makino – Fujita combination considers (Figs. 3 and 4 of Fujita) that the conductive structure comprises:
an input bonding pad (defined by the left ends of electrodes 14,15,16 for coupling to traces 24-1,25-1,26-1 by solder bumps 24-a,25-a,26-a), an electrode layer 14,15,16, and an output bonding pad (defined by the right ends of electrodes 14,15,16 for coupling to traces 24-2,25-2,26-2 by solder bumps 24-b,25-b,26-b) provided in parallel in a second (horizontal) direction, wherein the second (horizontal) direction is perpendicular to the first (vertical) direction, and the second (horizontal) direction is parallel to a (horizontal) plane where the underlay is located (120 in Figure A which corresponds to 11 in Fig. 1 of Fujita).
Further for claim 7, the manufacturing method of the Makino – Fujita combination comprises the steps of:
forming the groove (opening) penetrating through the upper cladding layer 123 (as identified in Fig. 6B of Makino) in the first (vertical) direction and extending in the second (horizontal) direction, wherein the second (horizontal) direction is perpendicular to the first (vertical) direction, and is parallel to a plane where the underlay 120 is located;
the forming a conductive structure that fills the groove comprises:
depositing a conductive material (of electrodes 111) into the groove, so as to form the input bonding pad (defined by the left ends of electrodes 14,15,16 for coupling to traces 24-1,25-1,26-1 by solder bumps 24-a,25-a,26-a), the electrode layer 111, and the output bonding pad (defined by the right ends of electrodes 14,15,16 for coupling to traces 24-2,25-2,26-2 by solder bumps 24-b,25-b,26-b) provided in parallel in the second (horizontal) direction.
As an aside, it is noted that input/output pads can be defined by end portions the electrodes 14,15,16 without any reshaping thereof or the electrode ends may be (re)shaped to accommodate particular electrical connections (e.g., as pad portions 34 in Fig. 6 of Fujita), both design choices are well known in the art of waveguide modulators.
Regarding claims 3 and 8, the Makino – Fujita combination considers (Figs. 3 and 4 of Fujita) that the conductive structure comprises:
a first one of first fixing assembly 24-a,25-a,26-a, which is located between the input bonding pad (defined by the left ends of electrodes 14,15,16 for coupling to traces 24-1,25-1,26-1 by solder bumps 24-a,25-a,26-a) and the substrate 21, and which is used for fixedly connecting the input bonding pad and the substrate 21 (according to Figs. 1, 3, and 4 of Fujita); and
a second one of first fixing assembly 24-b,25-b,26-b, which is located between the output bonding pad (defined by the right ends of electrodes 14,15,16 for coupling to traces 24-2,25-2,26-2 by solder bumps 24-b,25-b,26-b) and the substrate 21, and which is used for fixedly connecting the output bonding pad and the substrate 21 (according to Figs. 1, 3, and 4 of Fujita).
Further for claim 8, the Makino – Fujita combination renders obvious that the solder bumps 24-a,25-a,26-a, 24-b,25-b,26-b (the first fixing assembly) can first be attached to either the substrate 21 (as inn Figs. 1 and 4 of Fujita) or the left and right ends of electrodes 14,15,16 (the input and output bonding pads) before the substrate 21 and the optical modulation module are bonded by the solder bumps disposed therebetween. Both sequences work equally well. The second sequence (the solder bumps 24-a,25-a,26-a, 24-b,25-b,26-b are first attached to the left and right ends of electrodes 14,15,16) fully meets all of the recited step limitations, including the step of inverting the substrate to enable the first surface to be relatively close to the substrate, the step defining flip-chip mounting of the optical modulation module 10 to the substrate 21, as taught in Fig. 1 of Fujita.
Regarding claim 5, the Makino – Fujita combination considers that a compositive material of the optical waveguide layer (122 in Fig. 6B of Makino; 1,13 in Fig. 1 of Fujita) can comprise lithium niobate or lithium tantalate (para. 0029 and 0030 of Makino; para. 0001 and 0007 of Fujita);
and a compositive material of the lower cladding layer (121 in Fig. 6B of Makino) and the upper cladding layer (123 in Fig. 6B of Makino) comprises silicon oxide or silicon dioxide (para. 0031 and 0043 of Makino).
Regarding claim 10, in the manufacturing method of the Makino – Fujita combination, the forming an optical waveguide lamination 121,122,123 on the first surface of the underlay 120 comprises (with reference to Fig. 6B of Makino):
forming the lower cladding layer 121 on the first surface of the underlay 120;
forming an optical waveguide material layer 122 on the lower cladding layer 121;
removing a part (to shape thinner slabs) of the optical waveguide material layer 122 by etching so as to form the optical waveguide layer 122 (its ridge portion 122a); and
forming the upper cladding layer 123 covering the optical waveguide layer 122.
Claims 4 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Makino in view of Fujita, and further in view of Evans et al (US 2017/0194310 A1).
Regarding claims 4 and 9, the Makino – Fujita combination considers that the contemplated optical modulation module is driven by a driver and terminated by a resistance element (para. 0022 and 0035 of Makino) and that the driver may be integrated on the same substrate as the optical modulation module (para. 0017 of Fujita). While the Makino – Fujita combination does not expressly illustrate such integrated arrangement, Evans discloses (Figs. 1A, 2A, and 9A; para. 0048 – 0054, 0067 – 0069, and 0124 – 0126) an integrated arrangement that comprises an optical modulation module (identified as 104 in Fig. 1A; 204 in Fig. 2A; para. 0048) electrically connected with a substrate (110 in Fig. 1A; 202 in Fig. 2A; 902 in Fig. 9A) using bonding pads 108a and a fixing assembly 108b, the latter being solder bumps (para. 00448). Evans expressly teaches and explicitly illustrates that the optical modulation module is co-packaged/integrated on the same substrate with a driving assembly (210 in Fig. 2A; 914 in Fig. 9A) and a terminating resistance element (216 in Fig. 2A).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the optical modulation module of the Makino – Fujita combination can be co-packaged/integrated on the same substrate with a driving assembly and a terminating resistance element, as generally suggested by the Makino – Fujita combination and expressly taught (and explicitly illustrated) by Evans, so that a compact integrated system can be enabled and provide both improved reproducibility and enhanced heat dissipation from the terminating resistance element (para. 0035, 0068, and 0069 of Evans).
The Makino – Fujita – Evans combination considers that the optical modulation module, its driving assembly and terminating resistance element can be co-packaged/integrated on the same substrate by being flip-chip mounted and fixedly connected by corresponding solder bumps (fixing assemblies) and bonding pads (as taught by Fujita and Evans). Hence, the Makino – Fujita – Evans combination considers that the conductive structure further comprises:
a driving assembly (driver circuit), which is electrically connected (via solder bumps and traces on the substrate) with the optical modulation module through the input bonding pad, and which is used for applying a driving signal (modulating voltage) to the optical modulation module;
a resistance element (for terminating the optical modulation module), which is electrically connected with the optical modulation module through the output bonding pad;
a second fixing assembly (a second set/group of solder bumps), which is located between the driving assembly and the substrate, and which is used for fixedly connecting the driving assembly and the substrate; and
a third fixing assembly (a third set/group of solder bumps), which is located between the resistance element and the substrate, and which is used for fixedly connecting the resistance element and the substrate.
Conclusion
Applicant's arguments and amendments filed 4/6/26 have been fully considered but they are not persuasive and have failed to place the instant application in condition for allowance. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT TAVLYKAEV whose telephone number is (571)270-5634. The examiner can normally be reached 10:00 am - 6:00 pm, Monday - Friday.
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/ROBERT TAVLYKAEV/Primary Examiner, Art Unit 2896
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