Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgements
2. Applicant’s arguments/remarks, dated 02/25/2026, are acknowledged. Amended claim 1, cancelled claims 2-20, and newly added claims 21-39 are acknowledged. Accordingly, claims 1, and 21-39 are pending and have been examined.
Response to Arguments
3. Applicant’s arguments, with respect to the rejection of claim 1 under 35 U.S.C. 102 (a)(1) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of Sony Develops World's First*1Stacked CMOS Image Sensor Technology with 2-Layer Transistor Pixel (further referred to as Sony).
4. Applicant, on pg. 9 of 10, states that a first control circuit and a second control circuit are shown as being on different semiconductor chips; which is in contrast to amended claim 1 which requires that the first control circuit and the second control circuit be on the same second substrate.
Response to argument:
5. Though Uchida teaches a first semiconductor chip and a second semiconductor chip, as specified in [0041-0042] and depicted in Figures 4 and 10, with varying placements of pixel groups and scanning circuits, Uchida doesn’t explicitly teach a first substrate for the different pixel groups as limited above and a second substrate for the placement of the control circuit units as specified above.
However, Sony teaches a stacked image sensor wherein a logic chip of signal processing circuits is stacked together with a pixel chip. Sony, as depicted on pg. 2, shows two different designs wherein in either case the circuitry for signal processing is its own layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the taught image sensor in accordance with Uchida could have been designed in accordance with the teaching of Sony, allowing for a wider placement of photodiodes in a first layer which provides better resolution.
Claim Rejections - 35 USC § 103
6. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 1, 21-39 are rejected under 35 U.S.C. 103 as being unpatentable over Uchida (US 2017/0187973 A1) in view of Sony and further view of Kobayashi et al. (US 2022/0303485 A1).
8. Regarding claim 1, an imaging element (…Uchida teaches an image sensor 107, in [0030]; Fig. 2…) comprising:
a first substrate (see below regarding a first substrate) including
(i) a first pixel that includes a first photoelectric conversion section that converts light into a charge and outputs a first signal used for image generation, the first signal being based on the charge converted by the first photoelectric conversion section (…wherein [0030] teaches image sensor 107 (Fig. 2); further [0034], in accordance with Fig. 3B, teaches normal image capturing pixels (which in Fig. 2 appear as non-hatched pixels) which photoelectrically converts optical signal to a voltage value; also taught as p11 of a pixel array 200…),
(ii) a second pixel that includes a second photoelectric conversion section that converts light into a charge and outputs a second signal used for image generation, the second signal being based on the charge converted by the second photoelectric conversion section (…wherein [0034], in accordance with Fig. 3C teaches a focus detecting pixel with a particular arrangement of a light-shielding layer 311, corresponding to pixels p12 and p31 in Fig. 2…); and
(iii) a third pixel that includes a third photoelectric conversion section converts light into a charge and outputs a third signal used for focus detection of an optical system the third signal being based on the charge converted by the third photoelectric conversion section; and (…wherein [0034], in accordance with Fig. 3D teaches a focus detecting pixel with a particular arrangement of a light-shielding layer 311, corresponding to pixels p31 in Fig. 2…); and
a second substrate (see below regarding second substrate) that is laminated with the first substrate and includes:
(i) a first control circuit unit including
(a) a first pixel control unit, which outputs a first control signal for controlling an accumulation time during which the charge converted by the first photoelectric conversion section is accumulated, and (b) a second pixel control unit, which outputs a second control signal for controlling an accumulation time during which the charge converted by the second photoelectric conversion section is accumulated (…wherein [0035] teaches a vertical scanning circuit 201b for driving the focusing pixels (Fig. 3C and 3D); wherein Vb1-Vbn (Fig. 2) provide driving signals in respective rows wherein the focusing pixels are placed…); and
(ii) a second control circuit unit that outputs a third control signal for controlling an accumulation time during which the charge converted by the third photoelectric conversion section is accumulated (…wherein [0035] teaches a vertical scanning circuit 201a for driving image capturing pixels (Fig. 3B); wherein Va1-Van (Fig. 2) provide driving signals in respective rows wherein the pixels are placed…).
Though Uchida teaches a first semiconductor chip and a second semiconductor chip, as specified in [0041-0042] and depicted in Figures 4 and 10, with varying placements of pixel groups and scanning circuits, Uchida doesn’t explicitly teach a first substrate for the different pixel groups as limited above and a second substrate for the placement of the control circuit units as specified above.
However, Sony teaches a stacked image sensor wherein a logic chip of signal processing circuits is stacked together with a pixel chip. Sony, as depicted on pg. 2, shows two different designs wherein in either case the circuitry for signal processing is its own layer.
Further, Kobayashi teaches lamination between of image sensor substrates.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the taught image sensor in accordance with Uchida could have been designed in accordance with the teaching of Sony and Kobayashi, allowing for a wider placement of photodiodes in a first layer which provides better resolution.
9. Regarding claim 21, Uchida in view of Sony and Kobayashi teaches the imaging element according to claim 1, wherein
the first control circuit unit is disposed at a position facing the first pixel, the second pixel, and the third pixel in a laminating direction in which the first substrate and the second substrate are laminated (…Sony teaches a stacked relationship between the logic chip and pixel chip, as such the logic chip and its circuitries would face the pixel layer in the stacking direction.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the taught image sensor in accordance with Uchida could have been designed in accordance with the teaching of Sony, allowing for a wider placement of photodiodes in a first layer which provides better resolution…).
10. Regarding claim 22, Uchida in view of Sony and Kobayashi teaches the imaging element according to claim 21 (see claim 21 above) wherein
the first control circuit unit is disposed at a position facing the first photoelectric conversion section, the second photoelectric conversion section, and the third photoelectric conversion section in the laminating direction (…wherein as mapped in claim 21 Sony teaches a stacked image sensor wherein the logic chip portion is facing the photodiodes/pixel chip.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that the taught image sensor in accordance with Uchida could have been designed in accordance with the teaching of Sony, allowing for a wider placement of photodiodes in a first layer which provides better resolution…).
11. Regarding claim 23, Uchida in view of Sony and Kobayashi teaches the imaging element according to claim 22, wherein
the second control circuit unit is disposed outside the first control circuit unit on the second substrate (…Uchida, as depicted in Fig. 2, teaches circuits 201a and 201b disposed separately. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to design a logic chip of Sony’s teaching in which Uchida’s scanning circuits are implemented in a separate substrate, allowing for a wider placement of photodiodes in a first layer which provides better resolution…).
12. Regarding claim 24, Uchida in view of Sony and Kobayashi teaches the imaging element according to claim 22, further comprising:
a first control line that is electrically connected to the first pixel and through which the first control signal is output (…wherein Uchida, in [0031], teaches by changing a signal
tx to high level, accumulated charge at photodiode 301 is transferred; [0035] further
teaches driving signal group Va1 is constituted by driving signals resa1 , txa1 , and sela1
(with respect to the normal pixels)…);
a second control line that is electrically connected to the second pixel and through which the second control signal is output (…similarly, [0035] teaches driving signal group
Vb 1 is constituted by driving signals resb1 , txb1 , and selb1 (with respect to the focus
detection pixels as depicted in Fig. 3C)…); and
a third control line that is electrically connected to the third pixel and through which the third control signal is output (…similarly, [0035] teaches driving signal group Vb 1 is constituted by driving signals resb1 , txb1 , and selb1 (with respect to the focus
detection pixels as depicted in Fig. 3D)…).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to design a logic chip of Sony’s teaching in which Uchida’s scanning circuits are implemented in a separate substrate, allowing for a wider placement of photodiodes in a first layer which provides better resolution…).
13. Regarding claim 25, Uchida in view of Sony and Kobayashi teaches the imaging element according to claim 24 (see claim 24 above), wherein
the second control circuit unit is disposed outside the first control circuit unit on the second substrate (…Uchida, as depicted in Fig. 2, teaches circuits 201a and 201b disposed separately. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to design a logic chip of Sony’s teaching in which Uchida’s scanning circuits are implemented in a separate substrate, allowing for a wider placement of photodiodes in a first layer which provides better resolution…).
14. Regarding claim 26, Uchida in view of Sony and Kobayashi teaches the imaging element according to claim 22 (see claim 22 above), wherein
the first photoelectric conversion section, the second photoelectric conversion section, and the third photoelectric conversion section are disposed along a row direction (…Uchida teaches pixel region PA, in [0032] in accordance with Fig. 2, wherein the pixels are viewed as being formed in a horizontal direction…).
15. Regarding claim 27, Uchida in view of Sony and Kobayashi teaches the imaging element according to claim 26 (see claim 26 above), wherein
the third photoelectric conversion section is disposed between the first photoelectric conversion section and the second photoelectric conversion section in the row direction (…wherein Uchida, in [0034], teaches the focus detecting pixels in accordance with Fig. 3C (p12 and p31) Fig. 3D (p33), as being arrayed discretely. Fig. 2 lays out the pixel region PA, extends to a last top row ending with pk1 and last bottom ending with pkn; wherein pixels p11, p12, p31, and p33 would accordingly further populate the pixel region PA. As such, the pixel p33 of a particular row can fall in between a pixel p12 or p31 of a particular row (with respect to the entire pixel region PA)…).
16. Regarding claim 28, Uchida in view of Sony and Kobayashi teaches the imaging element according to claim 26 (see claim 26 above), further comprising:
a first control line that is electrically connected to the first pixel and through which the first control signal is output (…Uchida in [0035] teaches driving signal group Va for driving supplied to the “normal pixels” (p11); wherein Fig. 2 shows a line 3(Va1) connecting scanning circuit 201a connecting to p11…);
a second control line that is electrically connected to the second pixel and through which the first control signal is output (…Uchida in [0035] teaches driving signal group Vb for driving supplied to the focus detect pixels; wherein Fig. 2 shows a line 3(Vb1) connecting scanning circuit 201b connecting to p31…);
a third control line that is electrically connected to the third pixel and through which the first control signal is output (…Uchida in [0035] teaches driving signal group Vb for driving supplied to the focus detect pixels; wherein Fig. 2 shows a line 3(Vb3) connecting scanning circuit 201b connecting to p33…).
17. Regarding claim 29, Uchida in view of Sony and Kobayashi teaches the imaging element according to claim 1 (see claim 1 above), wherein
the second control circuit unit is disposed outside the first control circuit unit on the second substrate (…Uchida, as depicted in Fig. 2, teaches circuits 201a and 201b disposed separately. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to design a logic chip of Sony’s teaching in which Uchida’s scanning circuits are implemented in a separate substrate, allowing for a wider placement of photodiodes in a first layer which provides better resolution…).
18. Regarding claim 30, Uchida in view of Sony and Kobayashi teaches the imaging element according to claim 1 (see claim 1 above), wherein
the first substrate includes a fourth pixel that includes a fourth photoelectric conversion section that converts light into a charge and outputs a fourth signal used for focus detection of the optical system, the fourth signal being based on the charge converted by the fourth photoelectric conversion section, (…wherein additional pixels, as part of PA region, includes a fourth pixel for outputting photoelectric signals; Fig. 2…), and
the second control circuit unit outputs a fourth control signal for controlling an accumulation time during which the charge converted by the fourth photoelectric conversion section is accumulated (…wherein vertical scanning circuit 201b outputs numerous driving signals through driving signal group Vb1-Vbn…).
19. Regarding claim 31, Uchida in view of Sony and Kobayashi teaches the imaging element according to claim 30 (see claim 30 above), wherein
the second control circuit unit is disposed outside the first control circuit unit on the second substrate (…Uchida, as depicted in Fig. 2, teaches circuits 201a and 201b disposed separately. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to design a logic chip of Sony’s teaching in which Uchida’s scanning circuits are implemented in a separate substrate, allowing for a wider placement of photodiodes in a first layer which provides better resolution…).
20. Regarding claim 32, Uchida in view of Sony and Kobayashi teaches the imaging element according to claim 30 (see claim 30 above), wherein
the first photoelectric conversion section, the second photoelectric conversion section, the third photoelectric conversion section, and the fourth photoelectric conversion section are disposed along a row direction (…Uchida teaches pixel region PA, in [0032] in accordance with Fig. 2, wherein the pixels are viewed as being formed in a horizontal direction…); and
the second control circuit unit outputs the third control signal for controlling the accumulation time during which the charge converted by the third photoelectric conversion section is accumulated and the fourth control signal for controlling the accumulation time during which the charge converted by the fourth photoelectric conversion section is accumulated (…wherein vertical scanning circuit 201b outputs numerous driving signals through driving signal group Vb1-Vbn (in which the fourth pixel is further viewed as being a pixel that is particularly of the focus pixels…).
21. Regarding claim 33, Uchida in view of Sony and Kobayashi teaches the imaging element according to claim 32 (see claim 32 above), wherein
the second control circuit unit is disposed outside the first control circuit unit on the second substrate (…Uchida, as depicted in Fig. 2, teaches circuits 201a and 201b disposed separately. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to design a logic chip of Sony’s teaching in which Uchida’s scanning circuits are implemented in a separate substrate, allowing for a wider placement of photodiodes in a first layer which provides better resolution…).
22. Regarding claim 34, Uchida in view of Sony and Kobayashi teaches the imaging element according to claim 32, further comprising:
a first control line that is electrically connected to the first pixel and through which the first control signal is output (…Uchida in [0035] teaches driving signal group Va for driving supplied to the “normal pixels” (p11); wherein Fig. 2 shows a line 3(Va1) connecting scanning circuit 201a connecting to p11…);
a second control line that is electrically connected to the second pixel and through which the second control signal is output (…Uchida in [0035] teaches driving signal group Vb for driving supplied to the focus detect pixels; wherein Fig. 2 shows a line 3(Vb1) connecting scanning circuit 201b connecting to p31…); and
a third control line that is electrically connected to the third pixel and the fourth pixel and through which the third control signal is output (…Uchida in [0035] teaches driving signal group Vb for driving supplied to the focus detect pixels; wherein Fig. 2 shows a line 3(Vb3) connecting scanning circuit 201b connecting to p33; a fourth pixel corresponding to another pixel that is in the same row and type as p33 but in a different column…).
23. Regarding claim 35, Uchida in view of Sony and Kobayashi teaches the imaging element according to claim 34 (see claim 34 above), wherein
The second control circuit unit is disposed outside the first control circuit unit on the second substrate (…Uchida, as depicted in Fig. 2, teaches circuits 201a and 201b disposed separately. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to design a logic chip of Sony’s teaching in which Uchida’s scanning circuits are implemented in a separate substrate, allowing for a wider placement of photodiodes in a first layer which provides better resolution…).
24. Regarding claim 36, Uchida in view of Sony and Kobayashi teaches the imaging element according to claim 32 (see claim 32 above), wherein
the second photoelectric conversion section is disposed between the third photoelectric conversion section and the fourth photoelectric conversion section in the row direction; and
the third photoelectric conversion section is disposed between the first photoelectric conversion section and the second photoelectric conversion section in the row direction (…as mapped in claim 32 Uchida teaches pixel region PA, in [0032] in accordance with Fig. 2, wherein the pixels are viewed as being formed in a horizontal direction of different rows; because the array of pixel extends to a row ending in pkn; each photoelectric conversion section is relatively between each photoelectric conversion section…).
25. Regarding claim 37, Uchida in view of Sony and Kobayashi teaches the imaging element according to claim 36 (see claim 36 above), further comprising:
a first control line that is electrically connected to the first pixel and through which the first control signal is output (…Uchida in [0035] teaches driving signal group Va for driving supplied to the “normal pixels” (p11); wherein Fig. 2 shows a line 3(Va1) connecting scanning circuit 201a connecting to p11…);
a second control line that is electrically connected to the second pixel and through which the second control signal is output (…Uchida in [0035] teaches driving signal group Vb for driving supplied to the focus detect pixels; wherein Fig. 2 shows a line 3(Vb1) connecting scanning circuit 201b connecting to p31…); and
a third control line that is electrically connected to the third pixel and the fourth pixel and through which the third control signal is output (…Uchida in [0035] teaches driving signal group Vb for driving supplied to the focus detect pixels; wherein Fig. 2 shows a line 3(Vb3) connecting scanning circuit 201b connecting to p33; a fourth pixel corresponding to another pixel that is in the same row and type as p33 but in a different column…).
26. Regarding claim 38, Uchida in view of Sony and Kobayashi teaches the imaging element according to claim 37 (see claim 37 above), wherein
the second control circuit unit is disposed outside the first control circuit unit on the second substrate (…Uchida, as depicted in Fig. 2, teaches circuits 201a and 201b disposed separately. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to design a logic chip of Sony’s teaching in which Uchida’s scanning circuits are implemented in a separate substrate, allowing for a wider placement of photodiodes in a first layer which provides better resolution…).
27. Regarding claim 39, Uchida in view of Sony and Kobayashi teaches an imaging device (…wherein Uchida, in [0025], teaches an image capturing device 100; Fig. 1…) comprising:
the imaging element according to claim 1 (…wherein image sensor 107 is part of image capturing device 100 Fig. 1…).
Conclusion
28. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SURAFEL YILMAKASSAYE whose telephone number is (703)756-1910. The examiner can normally be reached Monday-Friday 8:30am-5:00pm.
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/SURAFEL YILMAKASSAYE/Examiner, Art Unit 2639
/TWYLER L HASKINS/Supervisory Patent Examiner, Art Unit 2639
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