DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co. , 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim 1 is rejected under 35 U.S.C. 10 3 as being unpatentable over Shieh ( WO 99/12010 A1 ) in view of Shrivastava ( US 2016/0041570 A1) , and further in view of Lee (2012/0099388 A1) , all three are cited by the applicant . Regarding C laim 1 , A circuit for device temperature protection : Shieh discloses an integrated temperature limit sensor constituting a circuit for device temperature protection, which provides a logic signal change upon reaching a predetermined high or low temperature limit, usable for alarm control, equipment shutdown, and equipment protection. See Shieh, Abstract; p. 2. Fig. 4 of Shieh reproduced for ease of reference. a Proportional-To-Absolute-Temperature (PTAT) voltage generator : Shieh explicitly discloses a PTAT voltage generator comprising bipolar transistors Q5 and Q6 (Q6 having an emitter area eight times that of Q5), resistor R6, and current mirror transistors Q1–Q4. The differential V_BE between Q5 and Q6, given by V_BEQ5 − V_BEQ6 = (KT/ q)· ln(J_Q5/J_Q6), generates a current I_R6 = (KT/ q·ln (J_Q5/J_Q6))/R6 that is proportional to absolute temperature (PTAT). This PTAT current is mirrored through Q3 and passed through resistors R5 (and R6) to generate voltage V_R at the comparator's negative input. Shieh expressly identifies V_R as "a voltage proportional to absolute temperature." See Shieh at pp. 6–8; Figs. 2–4. Lee confirms this structural element: Lee's PTAT current generator (110) uses an identical bipolar transistor differential structure (BJT1 of size k, BJT2 of size 1, and operational amplifier OP) to generate a PTAT current. See Lee at § 0031– § 0040; Fig. 5. A t least one comparator : Shieh explicitly discloses comparator COMP, which receives voltage V_R (the PTAT voltage) at its negative input and voltage V_D (the forward-biased pn junction/diode-connected transistor Q7 voltage) at its positive input. COMP outputs a logic signal indicating whether the device temperature has exceeded the preset trip-point limit. See Shieh at pp. 7–10; Figs. 2–4. T he PTAT voltage generator is configured to apply offset cancellation in a first clock phase : Shieh does not explicitly disclose that the PTAT voltage generator applies offset cancellation in a first clock phase. Shrivastava explicitly teaches this limitation. Shrivastava discloses a PTAT-based analog circuit in which a clock circuit (335) sends a clock signal having a first clock phase φ₁ and a second clock phase φ₂ to the PTAT/bandgap circuit. See § 0041; Fig. 3. The first charge pump circuit (410), which is operatively coupled to the first BJT Q1 and to the PTAT current source, has a first configuration during φ₁ in which capacitor Cf is connected to sample and store the input voltage Vin on its top plate while its bottom plate is connected to ground. See § 0042; Fig. 5A–B. This φ₁ configuration is explicitly the offset-canceling/sampling phase of the switched-capacitor circuit: systematic offset errors of the voltage source and switch circuitry are captured and stored on Cf during φ₁, so that when φ₂ arrives and the stored charge is transferred, the net effect is that the offset error is cancelled. This is a well-recognized and standard function of switched-capacitor sampling in precision analog circuits. Furthermore, the PTAT current source (1110) in Shrivastava is directly integrated with the clock oscillator (1120), making the PTAT circuit and the two-phase clock architecture inseparable. See § 0060– § 0061; Fig. 11. Shrivastava explicitly motivates the two-phase switched-capacitor approach by stating that it achieves the same circuit constants as resistor-based approaches but with "significantly lower area" and improved accuracy — directly addressing the same accuracy concern that Shieh raises. See § 0046. Lee further confirms and reinforces the motivation to apply offset cancellation to the PTAT generator: Lee's offset circuit (122) explicitly cancels offset voltage in the PTAT current path using operational amplifier 123 comparing Vref against feedback voltage Vfeed to supply corrective OFFSET signal to node ND. Lee teaches: "The offset circuit 122...is configured to generate the output voltage VOUT having...a constant level by controlling the output voltage VOUT of the node NC." See Lee at § 0034– § 0036; Figs. 4, 7. One of ordinary skill in the art, having read Lee's explicit disclosure of offset cancellation as a necessary design element in PTAT-based circuits, combined with Shrivastava's specific teaching of a two-phase clocked mechanism for implementing offset cancellation in the first clock phase, would have been motivated and able to configure Shieh's PTAT voltage generator to apply offset cancellation in a first clock phase. T he at least one comparator is configured to evaluate an output of the PTAT voltage generator in a second clock phase : Shieh does not explicitly disclose that the comparator evaluates in a second clock phase. Shrivastava discloses that during the second clock phase φ₂ , the stored charge on capacitor Cf is transferred to node 1 which connects to output capacitor C_L, and the BJT's base-emitter voltage is established as the output of the PTAT circuit — this is the evaluation phase in which the PTAT output is finalized and available to downstream circuitry. See § 0042; Fig. 5C ("During operation in clock phase φ₂, node 2 is connected to Vin and node 1 to the output capacitor C_L , t he voltage at node 1 goes to 2*Vin"). Applying this teaching to Shieh, one of ordinary skill in the art would configure Shieh's comparator COMP to evaluate V_R (the PTAT voltage output) during the second clock phase φ₂, after the offset cancellation has been applied to the PTAT generator during φ₁. Motivation to Combine: One of ordinary skill in the art would have been motivated to combine Shieh with Shrivastava and Lee for the following clear and specific reasons: A ll three references share the same technical field of PTAT-based analog integrated circuit design for temperature-dependent applications. Shieh itself expressly identifies accuracy of the trip-point setting as the primary design objective (p. 4), and Shrivastava explicitly proposes a two-phase clocked switched-capacitor architecture as the solution to achieving that accuracy in PTAT circuits ( § 0046). Lee independently confirms that offset cancellation is a standard, recognized design requirement in PTAT-based circuits for semiconductor devices ( § 0034– § 0036). Shrivastava is a successfully fabricated and tested circuit (Fig. 16), giving one of ordinary skill a reasonable expectation of success in applying Shrivastava's architecture to Shieh's circuit. T he combination requires only adding a clock circuit and phase-controlled switched-capacitor elements to Shieh's existing PTAT generator and comparator — a straightforward engineering modification for which Shrivastava provides detailed implementation guidance (Figs. 5A–C, 6, 13A–B, 14A–C). Claim 2 additionally requires that the PTAT voltage generator comprises an OTA, and that offset cancellation is applied by chopper stabilization of the OTA . Shieh discloses a PTAT voltage generator in which operational amplifier-like feedback is implicitly present in the current mirror balancing. Shrivastava explicitly discloses an amplifier/OTA in the PTAT circuit path, specifically the differential amplifier AMP in the charge pump circuit (Figs. 6, 13A) and the current-controlled oscillator's amplifier stage, confirming that an OTA is a recognized component of a PTAT voltage generator. See Shrivastava § 0047; Figs. 6, 8A. Lee further explicitly discloses an operational amplifier (OP) as a core component of its PTAT current generator (110), which balances the currents through BJT1 and BJT2 to establish the PTAT current. See Lee § 0038– § 0040; Fig. 5. Regarding chopper stabilization of the OTA : Shrivastava discloses that switches (417) are implemented as transmission gates (M_NS and M_PS) that are opened and closed in alternating clock phases φ₁ and φ₂ (see § 0066; Fig. 13A–B), which constitutes chopper-style operation of the amplifier/switch network. The function of these clocked switches is to reverse the signal path connections in alternating clock phases, which is the standard mechanism of chopper stabilization. One of ordinary skill in the art implementing the two-phase clocked PTAT circuit of Shrivastava in combination with Shieh's OTA-based PTAT generator would have recognized chopper stabilization — periodically reversing the OTA's input connections in synchrony with the clock phases — as the standard and well-established method for applying the phase-based offset cancellation of claim 1 to an OTA, and would have applied it as a routine design choice to reduce low-frequency 1/f noise and DC offset in the OTA within Shieh's PTAT generator. Claim 3 additionally requires that the comparator is configured to apply offset cancellation by auto-zeroing during the first clock phase . Shieh discloses comparator COMP in the temperature limit sensor. Shrivastava discloses that during the first clock phase φ₁, the switched-capacitor circuit is in its sampling configuration in which internal errors are captured and stored for subsequent cancellation. See § 0041– § 0042; Fig. 5A–B. Auto-zeroing is a specific, well-known implementation of offset cancellation for comparators in which the comparator's own input offset voltage is sampled and stored on a capacitor during the first clock phase (φ₁), so that it is subtracted from the comparator's input during the second clock phase (φ₂) — resulting in offset-free comparison. This technique is directly analogous to and consistent with the switched-capacitor offset sampling that Shrivastava applies to the PTAT generator during φ₁. Lee's offset circuit (122) explicitly applies offset correction to the output comparison node using a comparator (operational amplifier 123) that compares Vref against the feedback voltage and supplies a corrective OFFSET signal. See Lee § 0035– § 0036; Figs. 4, 7. One of ordinary skill in the art, reading Lee's explicit teaching of offset correction at the comparator stage in a PTAT-based circuit, combined with Shrivastava's two-phase clocking architecture, would have recognized auto-zeroing during φ₁ as the natural, standard method for applying offset cancellation to Shieh's comparator COMP, and would have implemented it as a routine design choice motivated by the accuracy goals shared by all three references. Claim 4 additionally requires a latch configured to latch an output from the at least one comparator at an end of the second clock phase. Shieh discloses that comparator COMP produces a logic output ("Out") that drives downstream logic circuitry including transistor M1, and the comparator output is used to trigger a circuit state change. See Shieh, Figs. 2–4; pp. 9–11. Shrivastava explicitly discloses that during the second clock phase φ₂ the output voltage is transferred to and held on output capacitor C_L , which stores and holds the evaluated voltage output at the end of φ₂. See § 0042; Figs. 5C, 6. An output capacitor C_L that stores the evaluated output at the end of φ₂ performs the identical function of a latch — it captures and holds the comparator's evaluation result at the end of the second clock phase, preventing the output from changing until the next evaluation cycle begins. Furthermore, Lee discloses a current control circuit (121) in which the output node NC feeds the output voltage VOUT, which is maintained at a constant level — implying that the output is captured and held by the downstream circuitry. See Lee § 0033; Fig. 4. A latch at the output of a clocked comparator is a standard and ubiquitous component in clocked analog circuit design, and configuring a latch to hold the comparator output at the end of φ₂ — as specifically taught by Shrivastava's C_L output capacitor — represents a routine and obvious design choice in the context of the combined references. Claim 5 additionally requires that the PTAT voltage generator comprises a bipolar core configured to generate a current for generating the output of the PTAT voltage generator . This limitation is explicitly and fully disclosed by Shieh. Shieh's PTAT voltage generator is built around a bipolar core consisting of bipolar transistors Q5 and Q6. Their differential base-emitter voltage relationship generates the PTAT current I_R6 = (KT/ q·ln (J_Q5/J_Q6))/R6, which constitutes the current for generating the PTAT output V_R of the PTAT voltage generator. See Shieh at pp. 6–8; Figs. 2–4. Shrivastava fully confirms and corroborates this element: Shrivastava discloses first and second BJT transistors Q1 and Q2 (where Q2 has a device width M times greater than Q1) as the bipolar core of the PTAT circuit, which generate V_BE1 and V_BE2, respectively. The difference ΔV_BE between these voltages is the PTAT signal used to generate V_REF. See Shrivastava § 0038– § 0039; Figs. 4, 7A–B. Lee similarly discloses bipolar transistors BJT1 and BJT2 of different sizes (BJT1 being K times larger than BJT2) as the bipolar core that generates the PTAT current through the differential path current mechanism. See Lee § 0038– § 0040; Fig. 5. Claim 6 additionally requires that the PTAT voltage generator comprises first and second transistors configured as a current mirror to mirror the current. This limitation is explicitly disclosed by Shieh. Shieh discloses transistors Q1 and Q2 (and Q3, Q4) configured as a current mirror that mirrors the PTAT current generated by the bipolar core (Q5/Q6/R6) to generate voltage V_R at the comparator input. Specifically, transistors Q1/Q2 form a current mirror biasing the circuit, and Q3/Q4 mirror the PTAT current to the voltage generation branch and to the diode-connected reference transistor Q7 branch, respectively. See Shieh at pp. 6–8; Figs. 2–4. Lee further and explicitly discloses that its current control circuit (121) comprises a plurality of PMOS transistors (PM21–PM32) configured as current mirrors in parallel, which replicate and scale the PTAT current from the PTAT current generator (110) to generate the internal voltage. See Lee § 0041– § 0049; Fig. 6. Shrivastava discloses PMOS transistors P1, P2, P3 in a current mirror configuration replicating the BGR/PTAT current. See Shrivastava § 0047; Fig. 8A. All three references fully disclose and confirm this limitation. Claim 7 additionally requires that the PTAT voltage generator comprises a notch filter configured to filter an output from the OTA , with the output of the notch filter coupled to the gates of the first and second transistors. Neither Shieh, Shrivastava, nor Lee explicitly discloses a notch filter at the output of the OTA in the PTAT generator. However, in a chopper-stabilized OTA circuit (as recited in claim 2, upon which claim 7 depends by virtue of claim 6's dependence chain), the chopping action introduces ripple at the chopper clock frequency at the OTA output. The output of the notch filter is stated to be coupled to the gates of the first and second transistors of the current mirror (claim 6 — Q1/Q2 in Shieh, or PMOS transistors in Shrivastava/Lee). Shrivastava explicitly discloses that the clock signals passing through the PTAT circuit must be carefully managed to avoid voltage errors at the gate nodes of the mirror transistors. Shrivastava discloses output load capacitors C_L connected to the base-emitter clamp nodes, which function as low-pass filtering elements to smooth the switched-capacitor output. See Shrivastava Figs. 4, 6, 13A. A notch filter (or low-pass filter) placed between the OTA output and the mirror transistor gates to suppress chopper-clock ripple is a standard and well-recognized companion component in any chopper-stabilized OTA design. One of ordinary skill in the art implementing chopper stabilization of the OTA in claim 2's context would have been expected as a matter of routine engineering to include a notch filter tuned to the chopper clock frequency to prevent chopper-induced ripple from disrupting the gate voltage of the current mirror transistors. This represents a standard, conventional design choice requiring no inventive step. Claim 8 additionally requires that the PTAT voltage generator comprises a chopper coupled to a first output and a second output of the current mirror , where the second output corresponds to a mirrored current. Shieh discloses a current mirror (Q1/Q2 and Q3/Q4) with multiple outputs: a first output driving the PTAT voltage generation path (through R5 via Q3 to generate V_R), and a second output providing mirrored current through Q4 and R4 to bias the diode-connected reference transistor Q7. See Shieh at pp. 6–8; Figs. 2–4. Shrivastava explicitly discloses switches (417 — transmission gates M_NS and M_PS) coupled to the outputs of the charge pump circuits associated with the current mirror and the bipolar core, which are opened and closed in alternating clock phases. See § 0066; Figs. 13A–B. These clocked switches are positioned precisely between the current mirror outputs and the downstream nodes (BJT bias nodes and voltage generation nodes), and they function as choppers by reversing connections in alternating phases. Shrivastava further discloses at § 0066 that these switches are implemented as transmission gates to pass voltages up to V_BE through both PMOS and NMOS components — confirming that a "chopper" at the current mirror outputs is explicitly disclosed in the context of the PTAT circuit. One of ordinary skill in the art combining Shieh's current mirror (with its first output to V_R generation path and second output to the reference bias path) with Shrivastava's clocked transmission gate switches at the current mirror output nodes would have recognized that positioning a chopper at both the first and second outputs of Shieh's current mirror — connecting them to the PTAT voltage resistor and the bipolar core respectively in φ₂, and reversing in φ₁ for offset cancellation — is the standard and obvious implementation of chopper stabilization in a current mirror-based PTAT circuit. Claim 9 specifies that in the second clock phase , the chopper (i) couples the first output of the current mirror to a resistor to generate a voltage corresponding to the PTAT output, and/or (ii) couples the second output of the current mirror to the bipolar core. Shieh discloses the functional state of these connections in steady-state (non-clocked) operation: the first output of the current mirror (Q3) passes through resistors R5/R6 to generate V_R (the PTAT voltage output), and the second output (through Q4/R4) biases the reference side of the circuit. See Shieh Figs. 2–4; pp. 6–8. Shrivastava explicitly discloses that during the second clock phase φ₂ , the circuit is in its evaluation configuration in which charge is transferred and the BJT bias voltages are established at the output. See § 0042; Fig. 5C. Specifically, during φ₂ the output capacitor C_L receives the transferred voltage (the PTAT output), and the first BJT Q1 (the bipolar core) receives its bias current via the charge transfer from the current path. This maps directly onto the recited configuration: first output to resistor (for V_R generation) and second output to bipolar core, both occurring during φ₂. One of ordinary skill in the art applying Shrivastava's two-phase clocking to Shieh's current mirror would have implemented the second clock phase φ₂ to route the current mirror's first output through the PTAT voltage resistor (R3/R5 of Shieh) and route the second output to the bipolar core (Q5/Q6 of Shieh) — as this is the standard "evaluation" state of a two-phase chopper-stabilized current mirror circuit, and is directly consistent with Shrivastava's φ₂ operating configuration. Claim 10 specifies that in the first clock phase , the chopper (i) couples the second output of the current mirror to the resistor, and/or (ii) couples the first output to the bipolar core. This claim recites the complementary switching state of the chopper relative to claim 9 — specifically, the φ₁ configuration in which the connections of the chopper are reversed relative to φ₂. In a two-phase chopper-stabilized circuit, the first clock phase reverses the connections of the second clock phase, thereby enabling the circuit to sample and cancel systematic offset errors that arise from component mismatch in the current mirror. Shrivastava explicitly discloses that during the first clock phase φ₁ , the switched-capacitor circuit is in its first (sampling/charging) configuration — the connections from the charge pump circuits to the BJT nodes are in their first (sampling) arrangement, complementary to the φ₂ evaluation arrangement. See § 0041; Figs. 5A–B. This is the standard definition of the offset-canceling clock phase in a two-phase chopper circuit — the connections are reversed relative to φ₂ so that systematic offset voltages are captured for subsequent cancellation. One of ordinary skill in the art implementing the two-phase chopper of claims 8–9 in Shieh's circuit (in view of Shrivastava) would have understood that the first clock phase φ₁ requires the complementary switching state: second output of the mirror to the resistor (instead of first output) and first output to the bipolar core (instead of second output) — this being the fundamental definition of two-phase chopper operation and following directly and obviously from claim 9's φ₂ configuration. Claim 11 additionally requires a plurality of comparators , each configured to evaluate a respective output of the PTAT voltage generator in the second clock phase by comparing that output to a respective reference voltage. Shieh discloses a single comparator COMP. Lee directly and explicitly discloses the use of multiple transistor stages in parallel (PM21, PM23, PM25, PM27, PM29, PM31 of current control circuit 121) controlled by respective selection signals (selb0–selb5), each generating a respective current magnitude corresponding to different temperature compensation levels, and comparing these against respective voltage levels. See Lee § 0042– § 0049; Fig. 6. Lee further discloses in its FIG. 9 embodiment (circuit 300) a plurality of voltage comparison operations — the temperature compensation voltage generator (320), voltage controller (330), and internal voltage generator (340) collectively generate and compare multiple voltage levels including VTEMP (temperature compensation voltage), VSTEP (step voltage), and VOUT (internal voltage), corresponding to different threshold levels. See Lee § 0060– § 0071; Fig. 9. Shrivastava further discloses that the bandgap reference circuit generates multiple voltage outputs V_BE1 and V_BE2 from the two BJTs Q1 and Q2, which are compared separately and combined in the summing circuit (432). See Shrivastava § 0044– § 0046; Figs. 4, 10A–C. One of ordinary skill in the art, motivated to detect multiple temperature thresholds in Shieh's temperature protection circuit (to provide, for example, both a warning level and a shutdown level), would have found it obvious to implement a plurality of comparators — as explicitly taught by Lee's multiple comparison stages and Shrivastava's multiple voltage outputs — each comparing a respective PTAT voltage tap against a respective reference voltage, all operating in the second clock phase of the two-phase clocked architecture of Shrivastava. Claim 12 additionally requires that in the second clock phase, the chopper couples the first output of the current mirror to a series of resistors to generate voltages corresponding to the respective outputs of the PTAT voltage generator (for comparison by the plurality of comparators of claim 11). Shieh discloses resistors R5 and R7 connected in series in the PTAT voltage path (R7 providing hysteresis, R5 setting the main PTAT voltage level), providing different voltage tap points along the resistor chain. See Shieh Fig. 2; pp. 9–11. Lee explicitly discloses an offset circuit (122) comprising a series of resistors R11–R16 connected in series between nodes ND and NE, with NMOS transistors (NM21–NM25) connected in parallel across respective resistor segments to provide selectable voltage taps at different resistance values. See Lee § 0051– § 0052; Fig. 7. This series resistor structure with selectable taps is directly analogous to and explicitly teaches "a series of resistors" generating multiple voltage levels corresponding to different PTAT outputs. Shrivastava discloses in its FIG. 10A–C embodiment (reference generation circuit 1000) that a series of capacitors C_b1, C_b2, C_b3 connected as a voltage-multiplying chain generates multiple scaled PTAT voltage levels (1×ΔV_BE, 2×ΔV_BE, 3×ΔV_BE), which are then combined to generate V_REF. See § 0055– § 0057; Figs. 10A–C. During φ₂ (the evaluation phase), the chopper connects the current mirror's first output through this series capacitor/resistor network to generate multiple scaled PTAT voltage levels. Combining these teachings, one of ordinary skill in the art implementing claim 12's plurality of comparators (claim 11) with the chopper architecture of claims 8–9 would have found it obvious — as directly taught by Lee's series resistor chain and Shrivastava's series capacitor voltage-multiplying chain — to configure the chopper's φ₂ state to couple the first current mirror output to a series of resistors, generating multiple PTAT voltage taps for comparison by the respective plurality of comparators of claim 11. Claim 13 recites a device comprising the circuit of claim 1, wherein the comparator is configured to compare an output of the PTAT voltage generator to a reference voltage to determine whether a temperature of the device has exceeded a limit. Shieh explicitly discloses comparator COMP comparing V_R (PTAT voltage output) against V_D ( forward-biased pn junction voltage as reference voltage) to determine whether the temperature has reached the preset limit, and outputting a logic signal accordingly. See Shieh Abstract; pp. 7–12; Figs. 2–4. Shieh expressly teaches that this comparison determines whether the device temperature "has exceeded a limit" and can trigger "alarm control, equipment control, shutdown, etc." See Shieh p. 2. The "device" incorporating the temperature protection circuit is explicitly described in Shieh as electronic equipment whose temperature is being monitored. See Shieh p. 2. Lee further explicitly discloses that the internal voltage generator is used within a semiconductor memory device in which the PTAT-based circuit generates internal voltages and provides temperature-dependent comparison outputs for device operation — demonstrating that integrating a PTAT-based temperature protection circuit within a larger device is well-established and standard practice. See Lee § 0002– § 0013; Figs. 4, 9. Shrivastava similarly integrates the PTAT-based bandgap reference circuit within a complete device system comprising an energy harvesting source, boost converter, and DC-DC regulator (Fig. 1), confirming that PTAT-based circuits are routinely integrated as components of larger semiconductor devices. See Shrivastava § 0033; Fig. 1. Claim 14 is a method of temperature protection of a device, the method comprising: (1) configuring a PTAT voltage generator in a circuit to apply offset cancellation in a first clock phase; and (2) configuring at least one comparator in the circuit to evaluate an output of the PTAT voltage generator in a second clock phase. Claim 14 is the method counterpart to apparatus claim 1. The full analysis provided for claim 1 applies here with equal force, transposed to the method context. Specifically: A method of temperature protection of a device : Shieh discloses an integrated temperature limit sensor providing a logic signal change when the device reaches a high or low temperature limit — explicitly a method of temperature protection. See Shieh Abstract; p. 2. C onfiguring a PTAT voltage generator in a circuit to apply offset cancellation in a first clock phase : As detailed under claim 1, this step is rendered obvious by the combination of Shieh's PTAT voltage generator (Q5/Q6/R6/Q1–Q4) with Shrivastava's explicit teaching of a first clock phase φ₁ during which the switched-capacitor circuit is in its sampling/offset-canceling configuration ( § 0041– § 0042; Figs. 5A–B), further in view of Lee's explicit teaching that offset cancellation is a necessary and standard design step in PTAT-based circuit configuration ( § 0034– § 0036). One of ordinary skill in the art would have performed the step of "configuring" Shieh's PTAT generator to apply offset cancellation in φ₁ by incorporating Shrivastava's two-phase switched-capacitor architecture and Lee's offset correction approach into Shieh's circuit as a routine design modification motivated by the shared accuracy objective. C onfiguring at least one comparator in the circuit to evaluate an output of the PTAT voltage generator in a second clock phase : As detailed under claim 1, this step is rendered obvious by Shrivastava's explicit teaching that during the second clock phase φ₂, the stored/corrected PTAT output is transferred and evaluated ( § 0042; Fig. 5C). One of ordinary skill in the art would have performed the step of configuring Shieh's comparator COMP to evaluate V_R during φ₂, after V_R has been offset-corrected during φ₁, as a straightforward consequence of applying Shrivastava's two-phase clocking to Shieh's comparator stage. Motivation to Combine (Method Context) : All motivations identified for claim 1 apply equally to claim 14. Additionally, the method claim is specifically supported by Shrivastava's disclosure of a specific implemented, tested, and fabricated two-phase clocked PTAT circuit (Fig. 16), which demonstrates that performing the steps of "configuring" the PTAT generator and comparator to operate in two clock phases is not only obvious but has been actually performed in the prior art with demonstrated success. One of ordinary skill would have had every reason and the complete technical guidance needed to perform these configuration steps in Shieh's temperature protection circuit. Claim 15 additionally recites: Applying offset cancellation by chopper stabilization of an OTA in the PTAT voltage generator; and/or Applying offset cancellation to the at least one comparator by auto-zeroing during the first clock phase. Claim 15 is the method counterpart to apparatus claims 2 and 3. The analyses provided for those apparatus claims apply here with equal force . In particular, A pplying the offset cancellation by chopper stabilization of an OTA in the PTAT voltage generator : As established under claim 2, Lee explicitly discloses an OTA (operational amplifier OP) as a core component of the PTAT current generator that establishes the PTAT current by equalizing the voltages across the differential BJT branches. See Lee § 0038– § 0040; Fig. 5. Shrivastava discloses clocked transmission gate switches (417 — M_NS and M_PS) that open and close in synchrony with clock phases φ₁ and φ₂, performing chopper-style operation on the voltage path connected to the BJT base nodes and thus to the OTA output. See Shrivastava § 0066; Figs. 13A–B. Performing the step of applying chopper stabilization to the OTA of Shieh's PTAT generator (configured as in claim 14's method) follows directly and obviously from combining Lee's OTA-based PTAT generator architecture with Shrivastava's clocked switch/chopper implementation. The step of chopper stabilization of an OTA is a well-recognized, standard method for reducing DC offset and 1/f noise in operational amplifiers, and applying it to the OTA of Shieh's PTAT generator — motivated by Shieh's stated goal of improved trip-point accuracy, Lee's teaching of offset correction necessity, and Shrivastava's explicit chopper-switch implementation — represents a routine and obvious design step. Also in A pplying offset cancellation to the at least one comparator by auto-zeroing during the first clock phase : As established under claim 3, Lee explicitly discloses an offset correction step at the comparator (operational amplifier 123) level: "The operational amplifier 123 compares a potential of a node NE...and the reference voltage Vref not influenced by a temperature change, and supplies an offset voltage OFFSET to a node ND." See Lee § 0035. This is the explicit step of applying offset cancellation to the comparator stage in a PTAT-based circuit. Shrivastava's two-phase architecture provides the φ₁ clock phase in which this step is performed. Auto-zeroing the comparator during φ₁ — sampling its own offset voltage on a storage capacitor and subtracting it during the φ₂ evaluation phase — is the standard, well-known method for performing comparator offset cancellation in a two-phase clocked circuit, directly suggested by the combination of Lee's explicit comparator offset correction step with Shrivastava's φ₁ sampling architecture. One of ordinary skill in the art performing the method of claim 14 would have applied auto-zeroing to Shieh's comparator COMP during φ₁ as an obvious and routine step to achieve the accuracy goals explicitly stated in all three references. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Enter examiner's name" \* MERGEFORMAT HAFIZUR RAHMAN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-0659 . The examiner can normally be reached FILLIN "Work schedule?" \* MERGEFORMAT M-F: 10-6 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-1769 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. /HAFIZUR RAHMAN/ Primary Examiner, Art Unit 2843.