DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant claims the benefit as a 371 national stage application which claims benefit of prior filed Patent Cooperation Treaty (PCT) application No. PCT/EP2022/064964 which claims the benefit of prior-filed to U.S. provisional patent application No. 63/195,692,filed 06/01/2021, which is acknowledged.
Drawings
The drawings were received on 11/27/2023. These drawings are acceptable.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on the following date(s): 11/27/2023 has been considered by the examiner.
Claim Interpretation
Per the guidance provided in MPEP 2111, the examiner makes record of the broadest reasonable interpretation (BRI) used for claim limitation terms in light of applicant specification.
Noted portions of MPEP 2111:
During patent examination, the pending claims must be "given their broadest reasonable interpretation consistent with the specification." The Federal Circuit’s en banc decision in Phillips v. AWH Corp., 415 F.3d 1303, 1316, 75 USPQ2d 1321, 1329 (Fed. Cir. 2005) expressly recognized that the USPTO employs the "broadest reasonable interpretation" standard:
The Patent and Trademark Office ("PTO") determines the scope of claims in patent applications not solely on the basis of the claim language, but upon giving claims their broadest reasonable construction "in light of the specification as it would be interpreted by one of ordinary skill in the art." In re Am. Acad. of Sci. Tech. Ctr., 367 F.3d 1359, 1364[, 70 USPQ2d 1827, 1830] (Fed. Cir. 2004). Indeed, the rules of the PTO require that application claims must "conform to the invention as set forth in the remainder of the specification and the terms and phrases used in the claims must find clear support or antecedent basis in the description so that the meaning of the terms in the claims may be ascertainable by reference to the description." 37 CFR 1.75(d)(1).
See also In re Suitco Surface, Inc., 603 F.3d 1255, 1259, 94 USPQ2d 1640, 1643 (Fed. Cir. 2010); In re Hyatt, 211 F.3d 1367, 1372, 54 USPQ2d 1664, 1667 (Fed. Cir. 2000).
….
Under a broadest reasonable interpretation (BRI), words of the claim must be given their plain meaning, unless such meaning is inconsistent with the specification. The plain meaning of a term means the ordinary and customary meaning given to the term by those of ordinary skill in the art at the relevant time. The ordinary and customary meaning of a term may be evidenced by a variety of sources, including the words of the claims themselves, the specification, drawings, and prior art. However, the best source for determining the meaning of a claim term is the specification - the greatest clarity is obtained when the specification serves as a glossary for the claim terms. Phillips v. AWH Corp., 415 F.3d 1303, 1315, 75 USPQ2d 1321, 1327 (Fed. Cir. 2005) (en banc) ("[T]he specification ‘is always highly relevant to the claim construction analysis. Usually, it is dispositive; it is the single best guide to the meaning of a disputed term.’" (quoting Vitronics Corp. v. Conceptronic Inc., 90 F.3d 1576, 1582 (Fed. Cir. 1996)). The words of the claim must be given their plain meaning unless the plain meaning is inconsistent with the specification. In re Zletz, 893 F.2d 319, 321, 13 USPQ2d 1320, 1322 (Fed. Cir. 1989) (discussed below); Chef America, Inc. v. Lamb-Weston, Inc., 358 F.3d 1371, 1372, 69 USPQ2d 1857 (Fed. Cir. 2004) (Ordinary, simple English words whose meaning is clear and unquestionable, absent any indication that their use in a particular context changes their meaning, are construed to mean exactly what they say…
The presumption that a term is given its ordinary and customary meaning may be rebutted by the applicant by clearly setting forth a different definition of the term in the specification. In re Morris, 127 F.3d 1048, 1054, 44 USPQ2d 1023, 1028 (Fed. Cir. 1997) (the USPTO looks to the ordinary use of the claim terms taking into account definitions or other "enlightenment" contained in the written description); But c.f. In re Am. Acad. of Sci. Tech. Ctr., 367 F.3d 1359, 1369, 70 USPQ2d 1827, 1834 (Fed. Cir. 2004) ("We have cautioned against reading limitations into a claim from the preferred embodiment described in the specification, even if it is the only embodiment described, absent clear disclaimer in the specification."). When the specification sets a clear path to the claim language, the scope of the claims is more easily determined and the public notice function of the claims is best served…
The claims in this application are given their broadest reasonable interpretation (BRI) using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art, see MPEP 2111. Examiner notes the following BRI of the noted claim terms:
The noted claim terms:
Quantum Circuit:
a framework in computer science that is used to evaluate the computational resources used in a quantum algorithm for modeling the causal relationship in quantum physics as connected qubit registers and quantum gate operators; wherein the qubit registers are represented by wires to model the state of qubit evolution according to a sequence of gates that define the quantum circuit;
Parameterized circuit: any operational element/object that is controlled/modeled with a corresponding parameter. Or a quantum circuit that incorporates a tunable parameter
Quantum bits (i.e. qbit or qubit):
are considered element that can hold the value 0 and 1 at the same time described using equation
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where the value of the bit when observed (or measured) collapsed to a state of 0 or 1;
can also be interpreted as an element for carrying information associated with a quantum process/system/algorithm that can be observed or measured.
Quantum gate:
not a physical gate line in a classical computer but refers model representation used to describe matrix operations in quantum computed as noted in the following examples:
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A qubit/qbit is considered a wire carrying information in a quantum circuit/system
Claim Objections
Claim 8 is objected to because of the following informalities: “(780)” does not be an intended part of the claim. Appropriate correction is required.
Claim 8 is objected to because of the following informalities: “(111)” does not be an intended part of the claim. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 9 , 10, 15, and 25 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 4, the limitation “quantum information are provided as meta information from an application layer via a kernel scheduler (API 5D) to an inner core of the operating system to efficiently use overall transactional computation power of the information process stack” is indefinite for the following reasons:
It is not clear what the initialization API 5D refers to and does not appear to be a term of art in quantum computer or distributed processing. The applicant should give the full name of the initialization prior to its use.
It is unclear how to asserting when/how the claimed information processing task (e.g. quantum information are provided as meta information from an application layer via a kernel scheduler (API 5D) to an inner core of the operating system) achieves or performs the claimed relative desired outcome (efficiently use overall transactional computation power of the information process stack).
How does one ascertain an inner core of an operating system? Is the claim referring to cache or a register location in memory? Or is it referring to the use of a multi-core processor as part of the computing architecture? Or is this another way of claiming the use of the operating system as done currently to instantiate a virtual environment? The intended scope is unclear.
Overall the limitation is incoherent for the noted reasons above and one of ordinary skill in the art would be unable to ascertain the intended scope of the claim limitation. The specification merely recites claim language and appears to suggests that the 5D notation is an label of some sort but fails to disclose what API 5D is or how it use in determining/ascertain its intended scope as claimed.
Examiner assumes any process to transfer quantum information to an application layer, which operates using an operating system as within the scope of the claim limitation.
Regarding claim 9, the use of the initialization MPI, it is not clear what the initialization refers to The applicant should give the full name of the initialization prior to its use. Applicant should also correct for API which is address in the claim 4 rejection.
Regarding claim 10 the limitation “when the application is being run via a virtual QPU, the system is configured to utilize advanced quantum inspired computing (AQIC) shortcuts automatically renders the claim indefinite for the following reasons:
advanced quantum inspired computing (AQIC) does not appear to be a term of art and the applicant has not clarified in the claim limitation the intended scope. One of ordinary skill in the art would be unable to ascertain the intent scope of the claimed term.
One of ordinary skill in the art would be unable to access utilize advanced quantum inspired computing (AQIC) shortcuts are per issue noted above.
Examiner assumes any process that avoid a process or parallelizes a process is within the scope of the limitation.
Regarding claim 15, the term “meta protocol controller” does not appear to be a term of art in quantum computer or distributed processing and the applicant has not clarified in the claim limitation the intended scope. One of ordinary skill in the art would be unable to ascertain the intent scope of the claimed term.
Examiner assumes and driver for processing information is within the scope of the claimed term.
Regarding claim 25, the limitation is similar with claim 4 and is rejected under similar rationale.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Katabarwa (US 20200334107, hereinafter ‘Kata’).
Regarding independent claim 2, Kata teaches a virtual quantum computer system, comprising: (in [0025] The computer program instructions may be executable by the processor [a virtual quantum computer system] to perform the benchmarking by causing the classical computer component to perform a modelling subroutine to simulate the near-term quantum device, thus creating a virtual quantum machine (VQM) [a virtual quantum computer system] to act as a model of the near-term quantum device. The modelling subroutine may perform the modelling by generating data representing the VQM based on data representing the near-term quantum device.)
a main memory; one or more memory bus systems coupled to the main memory; one or more physical processing units that have access to the main memory, preferably via at least one memory bus system; (As depicted Fig. 2B, Fig. 3:
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and in [0122] Referring to FIG. 3, a diagram is shown of a hybrid classical quantum computer (HQC) 300 implemented according to one embodiment of the present invention... The memory 310 is classical in the sense that it stores data in a storage medium in the form of bits, which have a single definite binary state at any point in time. The bits stored in the memory 310 may, for example, represent a computer program. The classical computer component 304 typically includes a bus 314. The processor 308 may read bits from and write bits to the memory 310 over the bus 314 [preferably via at least one memory bus system]. For example, the processor 308 may read instructions from the computer program in the memory 310 [a main memory; one or more memory bus systems coupled to the main memory; one or more physical processing units that have access to the main memory, preferably via at least one memory bus system], and may optionally receive input data 316 from a source external to the computer 302, such as from a user input device such as a mouse, keyboard, or any other input device. The processor 308 may use instructions that have been read from the memory 310 to perform computations on data read from the memory 310 and/or the input 316, and generate output from those instructions. The processor 308 may store that output back into the memory 310 and/or provide the output externally as output data 318 via an output device, such as a monitor, speaker, or network device [preferably via at least one memory bus system].)
a data processing unit coupled to at least one of the one or more physical processing units, the data processing unit serving as a bridge between internal systems of the virtual quantum computer system and external systems; (As depicted in Figs. 2B and 3 in [0122] Referring to FIG. 3, a diagram is shown of a hybrid classical quantum computer (HQC) 300 implemented according to one embodiment of the present invention. The HQC 300 includes a quantum computer component 102 (which may, for example, be implemented in the manner shown and described in connection with FIG. 1) and a classical computer component 306 [the data processing unit serving as a bridge between internal systems of the virtual quantum computer system and external systems]… The memory 310 is classical in the sense that it stores data in a storage medium in the form of bits, which have a single definite binary state at any point in time. The bits stored in the memory 310 may, for example, represent a computer program. The classical computer component 304 typically includes a bus 314. The processor 308 [a data processing unit coupled to at least one of the one or more physical processing units, the data processing unit serving as a bridge between internal systems of the virtual quantum computer system and external systems] may read bits from and write bits to the memory 310 over the bus 314. For example, the processor 308 [the data processing unit serving as a bridge between internal systems of the virtual quantum computer system and external systems] may read instructions from the computer program in the memory 310, and may optionally receive input data 316 from a source external to the computer 302, such as from a user input device such as a mouse, keyboard, or any other input device. The processor 308 may use instructions that have been read from the memory 310 to perform computations on data read from the memory 310 and/or the input 316, and generate output from those instructions. The processor 308 may store that output back into the memory 310 and/or provide the output externally as output data 318 via an output device, such as a monitor, speaker, or network device.)
and wherein a Bloch sphere is built into an intermediate representation of a memory pattern within the main memory in such a way that associated same state vectors lΨ> are fully represented within the memory pattern alongside or along with the classical information |0> and |1>. (in [0086] Certain implementations of quantum computers, referred as gate model quantum computers, comprise quantum gates. In contrast to classical gates, there is an infinite number of possible single-qubit quantum gates that change the state vector of a qubit. Changing the state of a qubit state vector typically is referred to as a single-qubit rotation, and may also be referred to herein as a state change or a single-qubit quantum-gate operation. A rotation, state change, or single-qubit quantum-gate operation may be represented mathematically by a unitary 2×2 matrix with complex elements. A rotation corresponds to a rotation of a qubit state within its Hilbert space [a Bloch sphere is built into an intermediate representation of a memory pattern within the main memory in such a way that associated same state vectors lΨ> are fully represented within the memory pattern alongside or along with the classical information |0> and |1>], which may be conceptualized as a rotation of the Bloch sphere [wherein a Bloch sphere is built into an intermediate representation of a memory pattern within the main memory in such a way that associated same state vectors lΨ> are fully represented within the memory pattern alongside or along with the classical information |0> and |1>]. (As is well-known to those having ordinary skill in the art, the Bloch sphere is a geometrical representation of the space of pure states of a qubit.) Multi-qubit gates alter the quantum state of a set of qubits [a Bloch sphere is built into an intermediate representation of a memory pattern within the main memory in such a way that associated same state vectors lΨ> are fully represented within the memory pattern alongside]. For example, two-qubit gates rotate the state of two qubits as a rotation in the four-dimensional Hilbert space of the two qubits. (As is well-known to those having ordinary skill in the art, a Hilbert space is an abstract vector space possessing the structure of an inner product that allows length and angle to be measured. Furthermore, Hilbert spaces are complete: there are enough limits in the space to allow the techniques of calculus to be used.) And in [0090] Some embodiments described herein generate, measure, or utilize quantum states that approximate a target quantum state [a Bloch sphere is built into an intermediate representation of a memory pattern within the main memory in such a way that associated same state vectors lΨ> are fully represented within the memory pattern alongside] (e.g., a ground state of a Hamiltonian). As will be appreciated by those trained in the art, there are many ways to quantify how well a first quantum state “approximates” a second quantum state. In the following description, any concept or definition of approximation known in the art may be used without departing from the scope hereof. For example, when the first and second quantum states are represented as first and second vectors [associated same state vectors lΨ> are fully represented within the memory pattern alongside or along with the classical information |0> and |1>], respectively, the first quantum state approximates the second quantum state when an inner product between the first and second vectors (called the “fidelity” between the two quantum states) is greater than a predefined amount (typically labeled ϵ) [associated same state vectors lΨ> are fully represented within the memory pattern alongside or along with the classical information |0> and |1>]. In this example, the fidelity quantifies how “close” or “similar” the first and second quantum states are to each other. The fidelity represents a probability that a measurement of the first quantum state will give the same result as if the measurement were performed on the second quantum state…
Examiner notes that the qbits are model as classical information states approximated quantum elements, for example, as depicted in Fig. 7
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And in [0083] Each qubit has an infinite number of different potential quantum-mechanical states. When the state of a qubit is physically measured, the measurement produces one of two different basis states resolved from the state of the qubit. Thus, a single qubit can represent a one, a zero, or any quantum superposition of those two qubit states [along with the classical information |0> and |1>]; a pair of qubits can be in any quantum superposition of 4 orthogonal basis states; and three qubits can be in any superposition of 8 orthogonal basis states. The function that defines the quantum-mechanical states of a qubit is known as its wavefunction. The wavefunction also specifies the probability distribution of outcomes for a given measurement…)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 6-7, 10-12, 16 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Rigetti et al. (US 20220084085, hereinafter ‘Rig’) in view of Yan et al. (US 20250199823, hereinafter ‘Yan’).
Regarding independent claim 1, Rig teaches a virtual quantum computer system, (in [0049] Each of the example quantum computing systems 103A, 103B operates as a quantum computing resource in the computing system 101 [a virtual quantum computer system]. The other resources 107 may include additional quantum computing resources (e.g., quantum computing systems, quantum virtual machines (QVMs) or quantum simulators) as well as classical (non-quantum) computing resources such as, for example, digital microprocessors, specialized co-processor units (e.g., graphics processing units (GPUs), cryptographic co-processors, etc.), special purpose logic circuitry (e.g., field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc.), systems-on-chips (SoCs), etc., or combinations of these and other types of computing modules.)
comprising: a main memory; one or more memory bus systems coupled to the main memory; (in [0122] FIG. 7 is a representation of an example virtualizable hybrid quantum-classical processor unit, and FIG. 8 is a representation of an example of two coherent virtualizable hybrid quantum-classical processor units. The processor units 700, 800 comprise: independent QPU cores 701, 801 where each box in the figure corresponds to a thread of execution for an array of N qubit(s); independent CPU cores 702, 802 where each box corresponds to a classical thread of execution (which may be processing an instance, doing minimum weight perfect matching, etc.); local Qache buses 703, 803 which are tightly coupled memory [comprising: a main memory; one or more memory bus systems coupled to the main memory] shared between all the QPU and CPU cores on their corresponding hybrid processing units (HPUs); processor-to-processor (system) Qache buses 804, 904 which enable coherency of the hybrid shared cache across multiple hybrid processing units; local Qache copies 705, 805, 905, which are cache copies local to a given hybrid processing unit that is managed by that hybrid processor's Quantum Memory Management Unit (QMMU) [comprising: a main memory; one or more memory bus systems coupled to the main memory] and holds coherent copies of all hybrid classical variables and state readout for the corresponding entire system; hybrid virtualization managers (hypervisors) 706, 806, 906 which load and manage jobs for execution, and part of managing these jobs includes configuring and maintaining the QMMU.…)
one or more physical processing units that have access to the main memory, preferably via at least one memory bus system; (in [0122] FIG. 7 is a representation of an example virtualizable hybrid quantum-classical processor unit, and FIG. 8 is a representation of an example of two coherent virtualizable hybrid quantum-classical processor units. The processor units 700, 800 comprise: independent QPU cores 701, 801 where each box in the figure corresponds to a thread of execution for an array of N qubit(s); independent CPU cores 702, 802 where each box corresponds to a classical thread of execution (which may be processing an instance, doing minimum weight perfect matching, etc.); local Qache buses [one or more physical processing units that have access to the main memory, preferably via at least one memory bus system] 703, 803 which are tightly coupled memory shared between all the QPU and CPU cores on their corresponding hybrid processing units (HPUs); processor-to-processor (system) Qache buses 804, 904 which enable coherency of the hybrid shared cache across multiple hybrid processing units; … [0123] The neighbor hybrid processor 809 is a second hybrid processor that sits on a cache coherent bus [one or more physical processing units that have access to the main memory, preferably via at least one memory bus system] with another hybrid processor. Examples of arbitrary parceling 810 of hybrid resources, which are arbitrary subsets of the available quantum and classical cores from the hybrid multi-processor that form the work units for execution of customer hybrid computation, are indicated in FIG. 8 for customers 1, 2 and 3 as 811, 812 and 813. All arbitrary subsets maintain tight coupling through the shared memory interface (system Qache bus) [one or more physical processing units that have access to the main memory, preferably via at least one memory bus system]. And in [0113] Commands for the waveform and readout engines (612-617) are provided by the classical compute functionality of the hybrid classical/quantum processor 611 (the “sequencers”). Soft processor(s) may be on the same FPGA as the waveform engine logic and hard processor(s) may be integrated on the same die as the FPGA/ASIC as the waveform engine. Processors are connected to the waveform engine via a high-bandwidth, low-latency (very much less than the coherence time) communications link/bus [one or more physical processing units that have access to the main memory, preferably via at least one memory bus system]…)
a data processing unit coupled to at least one of the one or more physical processing units, the data processing unit serving as a bridge between internal systems of the virtual quantum computer system and external systems; (As depicted in Fig. 1 and in [0040] The example computing system 101 can provide services to the user devices 110, for example, as a cloud-based or remote-accessed computer system, as a distributed computing resource, as a supercomputer or another type of high-performance computing resource, or in another manner. The computing system 101 or the user devices 110 may also have access to one or more other quantum computing systems (e.g., quantum computing resources that are accessible through the wide area network 115 [a data processing unit coupled to at least one of the one or more physical processing units, the data processing unit serving as a bridge between internal systems of the virtual quantum computer system and external systems], the local network 109 or otherwise). )
one or more cache coherency interconnects connecting the one or more physical processing units; (in [0122] FIG. 7 is a representation of an example virtualizable hybrid quantum-classical processor unit, and FIG. 8 is a representation of an example of two coherent virtualizable hybrid quantum-classical processor units. The processor units 700, 800 comprise: independent QPU cores 701, 801 where each box in the figure corresponds to a thread of execution for an array of N qubit(s); independent CPU cores 702, 802 where each box corresponds to a classical thread of execution (which may be processing an instance, doing minimum weight perfect matching, etc.); local Qache buses 703, 803 which are tightly coupled memory shared between all the QPU and CPU cores on their corresponding hybrid processing units (HPUs); processor-to-processor (system) Qache buses 804, 904 which enable coherency of the hybrid shared cache across multiple hybrid processing units; local Qache copies 705, 805, 905, which are cache copies local to a given hybrid processing unit that is managed by that hybrid processor's Quantum Memory Management Unit (QMMU) and holds coherent copies of all hybrid classical variables and state readout for the corresponding entire system; hybrid virtualization managers (hypervisors) 706, 806, 906 which load and manage jobs for execution, and part of managing these jobs includes configuring and maintaining the QMMU; Qache Virtualization Modules 707, 807, 907 where the QMMU maintains cache coherence [one or more cache coherency interconnects connecting the one or more physical processing units] between the local qache copy and the local qache copies of other hybrid processors [ … connecting the one or more physical processing units] on the system qache bus. As such the hybrid processor 708, 808, 908 is a collection of concurrent quantum and classical cores that can share memory and form a standalone-capable unit for hybrid quantum computation…)
and an information process stack that comprises: a hardware layer, an operating system coupled to the hardware layer and a container environment coupled to the operating system; (in [0058] In an example implementation of a cloud-based QC environment, the servers 108 may operate as a cloud provider [an information process stack that comprises: a hardware layer, an operating system coupled to the hardware layer and a container environment coupled to the operating system] that dynamically manages the allocation and provisioning of physical computing resources (e.g., GPUs, CPUs, QPUs, etc.) [a hardware layer, an operating system coupled to the hardware layer]. Accordingly, the servers 108 may provide services by defining virtualized resources for each user account. For instance, the virtualized resources may be formatted as virtual machine images, virtual machines, containers [and a container environment coupled to the operating system], or virtualized resources that can be provisioned for a user account and configured by a user. In some cases, the cloud-based QC environment is implemented using a resource such as, for example, OPENSTACK®. OPENSTACK® is an example of a software platform for cloud-based computing, which can be used to provide virtual servers and other virtual computing resources for users. Examiner notes that one of ordinary skill in art would understand that provisionally virtual machine/containers for processing information in a cloud computing environment include claimed elements)
wherein the information process stack is configured to: initialize qubits with classical meta information; initialize gate circuits between the qubits with the classical meta information; (in [0065] In some implementations, a quantum computing system can operate using gate-based models for quantum computing. For example, the qubits can be initialized in an initial state [wherein the information process stack is configured to: initialize qubits with classical meta information], and a quantum logic circuit comprised of a series of quantum logic gates can be applied to transform the qubits and extract measurements representing the output of the quantum computation. Individual qubits may be controlled by single-qubit quantum logic gates, and pairs of qubits may be controlled by two-qubit quantum logic gates (e.g., entangling gates that are capable of generating entanglement between the pair of qubits). In some implementations, a quantum computing system can operate using adiabatic or annealing models for quantum computing. For instance, the qubits [wherein the information process stack is configured to: initialize qubits with classical meta information] can be initialized in an initial state, and the controlling Hamiltonian [with classical meta information] can be transformed adiabatically by adjusting control parameters [initialize gate circuits between the qubits with the classical meta information] to another state that can be measured to obtain an output of the quantum computation [initialize gate circuits between the qubits with the classical meta information;]… )
process a given quantum circuit by transforming all qubits by unitary matrices; (in [0085] Hardware and software systems for virtualized quantum-classical computing are described as follows with reference to the figures. The system capabilities and core concepts that underpin the virtualization of quantum-classical compute systems and their provisioning to multiple simultaneous users are covered starting from the qubit level (for example, the quantum integrated circuit) and including: the dynamical creation and definition of qubit plaquettes with specific performance attributes and characteristics [process a given quantum circuit by transforming all qubits by unitary matrices]; the hosting on a single QPU multiple user instances connected to those plaquettes and the provisioning of classical resources to support each such instance in a quantum classical architecture, as demanded by the specific job or user… [0102] The algorithm may be compiled (503) through a system programming interface (403). The compilation may include: a translation of an algorithm to a set of machine executable instructions, for instance a set of executable gates and readout operations; translation of an algorithm and/or instructions to another algorithm and/or instructions, for instance reducing the number of gate operations required to approximately implement a unitary [process a given quantum circuit by transforming all qubits by unitary matrices] to optimize the algorithms efficiency; providing information about potential plaquettes available to perform the algorithm, for instance their connectivity, and/or available gate-set, and/or benchmarks; and providing information about other compilations, for instance if a requested subroutine has been compiled for use with a previous algorithm.)
measure the qubits to retrieve classical information; and process classical information. (in [0031] In some instances, a method for calculating a price for use of a configuration of qubits and qubit-qubit links on one or more quantum processor units [measure the qubits to retrieve classical information] by a user for running a computer program, may comprise: accessing a first database by a computer processor unit to collect design characteristics of the one or more quantum processor units, including inferred characteristics pertaining to the expressiveness of the one or more quantum processor units, wherein the inferred characteristics include instruction availability; accessing a second database by the computer processor unit to collect [process classical information] measurements of physical characteristics of the one or more quantum processor units [measure the qubits to retrieve classical information]; accessing a third database by the computer processor unit to collect characteristics of a specific user's request; and determining the price using data collected from the first, second and third databases. And in [0065] In some implementations, a quantum computing system can operate using gate-based models for quantum computing. For example, the qubits can be initialized in an initial state, and a quantum logic circuit comprised of a series of quantum logic gates can be applied to transform the qubits and extract measurements representing the output of the quantum computation [measure the qubits to retrieve classical information]. Individual qubits may be controlled by single-qubit quantum logic gates, and pairs of qubits may be controlled by two-qubit quantum logic gates (e.g., entangling gates that are capable of generating entanglement between the pair of qubits). In some implementations, a quantum computing system can operate using adiabatic or annealing models for quantum computing. For instance, the qubits can be initialized in an initial state, and the controlling Hamiltonian can be transformed adiabatically by adjusting control parameters to another state that can be measured to obtain an output of the quantum computation [measure the qubits to retrieve classical information; and process classical information]...)
While Rig teaches the information processing stack for processing claimed information in a distributed/cloud computing environment. One of ordinary skill in art would understand that provisioned virtual machine/containers for processing information in a cloud computing environment include claimed elements as noted above.
Additionally Yan expressly teaches that provisioned virtual machine/containers for processing information in a cloud computing environment include claimed elements information process stack that comprises: a hardware layer, an operating system coupled to the hardware layer and a container environment coupled to the operating system; (in [0038] FIG. 4 illustrates generalized hardware and software components of a general-purpose computer system, such as a general-purpose computer system having an architecture similar to that shown in FIG. 1. The computer system 400 [information process stack that comprises: a hardware layer, an operating system coupled to the hardware layer and a container environment coupled to the operating system] is often considered to include three fundamental layers: (1) a hardware layer or level 402 [information process stack that comprises: a hardware layer, an operating system coupled to the hardware layer …]; (2) an operating-system layer or level 404 [information process stack that comprises: a hardware layer, an operating system coupled to the hardware layer …]; and (3) an application-program layer or level 406. The hardware layer 402 includes one or more processors 408, system memory 410, various different types of input-output (“I/O”) devices 410 and 412, and mass-storage devices 414…. [0043] ... FIG. 5C illustrates the OSL-virtualization approach. In FIG. 5C, as in previously discussed FIG. 4, an operating system 404 runs above the hardware 402 of a host computer [information process stack that comprises: a hardware layer, an operating system coupled to the hardware layer and a container environment coupled to the operating system] The operating system provides an interface for higher-level computational entities, the interface including a system-call interface 428 and exposure to the non-privileged instructions and memory addresses and registers 426 of the hardware layer 402 [information process stack that comprises: a hardware layer, an operating system coupled to the hardware layer …]. However, unlike in FIG. 5A, rather than applications running directly above the operating system, OSL virtualization involves an OS-level virtualization layer 560 that provides an operating-system interface 562-564 to each of one or more containers 566-568 [… and a container environment coupled to the operating system]. The containers, in turn, provide an execution environment for one or more applications, such as application 570 running within the execution environment provided by container 566. The container can be thought of as a partition of the resources generally available to higher-level computational entities through the operating system interface 430. While a traditional virtualization layer can simulate the hardware interface expected by any of many different operating systems. OSL virtualization essentially provides a secure partition of the execution environment provided by a particular operating system. As one example, OSL virtualization provides a file system to each container, but the file system provided to the container is essentially a view of a partition of the general file system provided by the underlying operating system [information process stack that comprises: a hardware layer, an operating system coupled to the hardware layer and a container environment coupled to the operating system]. In essence, OSL virtualization uses operating-system features, such as name space support, to isolate each container from the remaining containers so that the applications executing within the execution environment provided by a container are isolated from applications executing within the execution environments provided by all other containers. As a result, a container can be booted up much faster than a virtual machine, since the container uses operating-system-kernel features that are already available within the host computer. Furthermore, the containers share computational bandwidth, memory, network bandwidth, and other computational resources provided by the operating system. without resource overhead allocated to virtual machines and virtualization layers...)
Yan and Rig are analogous art because both involve developing information retrieval and processing techniques using machine learning systems and algorithms.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the prior art of retrieving and processing information in distributed-computer-systems, as disclosed by Yan with the method of developing information retrieval and processing computer system with quantum and classical compute resources provisionable to multiple users in distributed computing environments as disclosed by Rig.
One of ordinary skill in the arts would have been motivated to combine the methods and systems disclosed by Yan and Rig, as noted above.; Doing so allows for implementing systems based on cloud-computing interfaces that enable easy and straightforward configuration of virtual computing facilities, flexibility in the types of applications and operating systems that can be configured, and other functionalities that are useful cloud-computing users, (Yan, 0037).
Regarding claim 6, the rejection of claim 1 is incorporated and Rig in combination with Yan teaches the system of claim 1, further comprising physical qubit registers, wherein the classical meta information required for the quantum gate circuitry is computed by a gate control unit of a native quantum processor. (in [0065] In some implementations, a quantum computing system can operate using gate-based models for quantum computing. For example, the qubits can be initialized in an initial state , and a quantum logic circuit comprised of a series of quantum logic gates [further comprising physical qubit registers, wherein the classical meta information required for the quantum gate circuitry is computed by a gate control unit of a native quantum processor] can be applied to transform the qubits and extract measurements representing the output of the quantum computation. Individual qubits may be controlled by single-qubit quantum logic gates, and pairs of qubits may be controlled by two-qubit quantum logic gates (e.g., entangling gates that are capable of generating entanglement between the pair of qubits) [further comprising physical qubit registers, wherein the classical meta information required for the quantum gate circuitry is computed by a gate control unit of a native quantum processor]. In some implementations, a quantum computing system can operate using adiabatic or annealing models for quantum computing. For instance, the qubits can be initialized in an initial state, and the controlling Hamiltonian can be transformed adiabatically by adjusting control parameters to another state that can be measured to obtain an output of the quantum computation [further comprising physical qubit registers, wherein the classical meta information required for the quantum gate circuitry is computed by a gate control unit of a native quantum processor]… )
Regarding claim 7, the rejection of claim 1 is incorporated and Rig in combination with Yan teaches the system of claim 1, further comprising a virtual quantum processor, wherein gate matrices within the main memory are constructed with the classical meta information required for the quantum gate circuit, such that processor hardware is implemented with an agnostic architecture of the information process stack, preferably above the kernel scheduler API. (in(in [0085] Hardware and software systems for virtualized quantum-classical [further comprising a virtual quantum processor,… such that processor hardware is implemented with an agnostic architecture of the information process stack, preferably above the kernel scheduler API as virtualization that occurs in a computing environment using known stacks for processing information that can run on any server environment] computing are described as follows with reference to the figures. The system capabilities and core concepts that underpin the virtualization of quantum-classical compute systems and their provisioning to multiple simultaneous users are covered starting from the qubit level (for example, the quantum integrated circuit) and including: the dynamical creation and definition of qubit plaquettes with specific performance attributes and characteristics]; the hosting on a single QPU multiple user instances connected to those plaquettes and the provisioning of classical resources to support each such instance in a quantum classical architecture, as demanded by the specific job or user… [0102] The algorithm may be compiled (503) through a system programming interface [further comprising a virtual quantum processor,… such that processor hardware is implemented with an agnostic architecture of the information process stack, preferably above the kernel scheduler API as virtualization that occurs in a computing environment using known stacks for processing information that can run on any server environment] (403). The compilation may include: a translation of an algorithm to a set of machine executable instructions, for instance a set of executable gates and readout operations; translation of an algorithm and/or instructions to another algorithm and/or instructions, for instance reducing the number of gate operations required to approximately implement a unitary [further comprising a virtual quantum processor, wherein gate matrices within the main memory are constructed with the classical meta information required for the quantum gate circuit, such that processor hardware is implemented with an agnostic architecture of the information process stack, preferably above the kernel scheduler API] to optimize the algorithms efficiency; providing information about potential plaquettes available to perform the algorithm, for instance their connectivity, and/or available gate-set, and/or benchmarks; and providing information about other compilations, for instance if a requested subroutine has been compiled for use with a previous algorithm. And in[0051] In some instances, programs can be formatted as source code that can be rendered in human-readable form (e.g., as text) and can be compiled, for example, by a compiler running on the servers 108 [such that processor hardware is implemented with an agnostic architecture of the information process stack, preferably above the kernel scheduler API], on the quantum computing systems 103, or elsewhere… )
Additionally Yan teaches in [0043] …FIG. 5C illustrates the OSL-virtualization approach. In FIG. 5C, as in previously discussed FIG. 4, an operating system 404 runs above the hardware 402 of a host computer. The operating system provides an interface for higher-level computational entities, the interface including a system-call interface 428 and exposure to the non-privileged instructions and memory addresses and registers 426 of the hardware layer 402. However, unlike in FIG. 5A, rather than applications running directly above the operating system, OSL virtualization involves an OS-level virtualization layer 560 that provides an operating-system interface 562-564 to each of one or more containers 566-568. The containers, in turn, provide an execution environment for one or more applications, such as application 570 running within the execution environment provided by container 566. The container can be thought of as a partition of the resources generally available to higher-level computational entities through the operating system interface 430 [a virtual quantum processor, wherein as part of a resource hierarchy]. While a traditional virtualization layer can simulate the hardware interface expected by any of many different operating systems. OSL virtualization essentially provides a secure partition of the execution environment provided by a particular operating system. As one example, OSL virtualization provides a file system to each container, but the file system provided to the container is essentially a view of a partition of the general file system provided by the underlying operating system. In essence, OSL virtualization uses operating-system features, such as name space support, to isolate each container from the remaining containers so that the applications executing within the execution environment provided by a container are isolated from applications executing within the execution environments provided by all other containers. As a result, a container can be booted up much faster than a virtual machine, since the container uses operating-system-kernel features that are already available within the host computer. Furthermore, the containers share computational bandwidth, memory, network bandwidth, and other computational resources provided by the operating system. without resource overhead allocated to virtual machines and virtualization layers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Yan and Rig for the same reasons disclosed above in the claim 1 rejection.
Regarding claim 10, the rejection of claim 1 is incorporated and Rig in combination with Yan teaches the system of claim 1, wherein, when running an application, the information process stack is configured to: run parallel versions of the application on both virtual quantum processing units (virtual QPUs) and native quantum processing units (native QPUs), (in [0060] In some implementations, all or part of the computing system 101 operates as a hybrid computing environment. For example, quantum programs can be formatted as hybrid classical/quantum programs that include instructions for execution by one or more quantum computing resources and instructions for execution by one or more classical resources. The servers 108 can allocate quantum and classical computing resources in the hybrid computing environment, and delegate programs to the allocated computing resources for execution. The quantum computing resources in the hybrid environment may include, for example, one or more quantum processing units (QPUs) [wherein, when running an application, the information process stack is configured to: run parallel versions of the application on both … and native quantum processing units (native QPUs)], one or more quantum virtual machines (QVMs) [wherein, when running an application, the information process stack is configured to: run parallel versions of the application on both virtual quantum processing units (virtual QPUs) …], one or quantum simulators, or possibly other types of quantum resources…)
wherein, preferably, when the application is being run via a native QPU, a memory pattern translation unit is configured to read out state vectors; and/or wherein, preferably, when the application is being run via a virtual QPU, the system is configured to utilize advanced quantum inspired computing (AQIC) shortcuts automatically. (in [0122] FIG. 7 is a representation of an example virtualizable hybrid quantum-classical processor unit, and FIG. 8 is a representation of an example of two coherent virtualizable hybrid quantum-classical processor units. The processor units 700, 800 comprise: independent QPU cores 701, 801 where each box in the figure corresponds to a thread of execution for an array of N qubit(s) [wherein, preferably, when the application is being run via a native QPU, a memory pattern translation unit is configured to read out state vectors]… [0155] In FIG. 13, the classical CPUs 1308 can have the same industry-standard architecture as is used in general purpose data centers. This would allow a user's program to run against a quantum virtual machine (QVM) and then immediately target the real QPU, without needing to recompile the software [or wherein, preferably, when the application is being run via a virtual QPU, the system is configured to utilize advanced quantum inspired computing (AQIC) shortcuts automatically]… )
Regarding claim 11 the rejection of claim 1 is incorporated and Rig in combination with Yan teaches the system of claim 1, wherein the information process stack is configured to: store data utilized in different instances of native and virtual processing in shared memory using virtual processor instances (VPIs) comprised of processor kernel extensions. ([0122] FIG. 7 is a representation of an example virtualizable hybrid quantum-classical processor unit, and FIG. 8 is a representation of an example of two coherent virtualizable hybrid quantum-classical processor units. The processor units 700, 800 comprise: independent QPU cores 701, 801 where each box in the figure corresponds to a thread of execution for an array of N qubit(s); independent CPU cores 702, 802 where each box corresponds to a classical thread of execution [wherein the information process stack is configured to: store data utilized in different instances of native and virtual processing in shared memory using virtual processor instances (VPIs) comprised of processor kernel extensions] (which may be processing an instance, doing minimum weight perfect matching, etc.); local Qache buses 703, 803 which are tightly coupled memory shared between all the QPU and CPU cores on their corresponding hybrid processing units (HPUs); processor-to-processor (system) Qache buses 804, 904 which enable coherency of the hybrid shared cache across multiple hybrid processing units [shared memory using virtual processor instances (VPIs)]; local Qache copies 705, 805, 905, which are cache copies local to a given hybrid processing unit that is managed by that hybrid processor's Quantum Memory Management Unit (QMMU) and holds coherent copies of all hybrid classical variables and state readout for the corresponding entire system; hybrid virtualization managers (hypervisors) 706, 806, 906 which load and manage jobs for execution [shared memory using virtual processor instances (VPIs)], and part of managing these jobs includes configuring and maintaining the QMMU; Qache Virtualization Modules 707, 807, 907 where the QMMU maintains cache coherence between the local qache copy and the local qache copies of other hybrid processors on the system qache bus. As such the hybrid processor 708, 808, 908 is a collection of concurrent quantum and classical cores that can share memory and form a standalone-capable unit for hybrid quantum computation…)
Regarding claim 12, the rejection of claim 1 is incorporated and Rig in combination with Yan teaches the system of claim 1, wherein a memory pattern itself within the main memory functions as meta-information for the respective processing units to control their execution of the data processed, such as to realize cache coherency, implement inherent intermediate representations or deliver information about topological dependencies to the control units of the processors, which, preferably, is configured for utilization by software developers to orchestrate different processing units accessing the same main memory most efficiently in parallel. ([0124] The QMMU and the Qache are shown in detail in FIG. 9. The QMMU and Qache operate with the following: Ci Classical Shared Variable 921, which is a classical bitstring for communicating state/sharing data between QPU and CPU cores; Qi Gate Command 922, which are gate commands for triggering specified state manipulation of qubits Qi from i=0 to i=N, where N is the number of qubits allocated to that QPU core; Qi State 923, which is the last measured state of Qi (if gate has been applied, this Qache entry is marked dirty in the hygiene mask., if measured state is still valid, hygiene mask holds clean for this Qache entry); Qi State Hygiene Mask 924 indicates if quantum information exists in the system for Qi or if Qi contains a bit of classical information. A Coherency Agent 925 uses a cache coherence scheme (snooping, directory based, etc.) to maintain Qache coherency across the multiprocessor system [wherein a memory pattern itself within the main memory functions as meta-information for the respective processing units to control their execution of the data processed, such as to realize cache coherency, implement inherent intermediate representations or deliver information about topological dependencies to the control units of the processors, which, preferably, is configured for utilization by software developers to orchestrate different processing units accessing the same main memory most efficiently in parallel.].)
Regarding claim 16, the rejection of claim 1 is incorporated and Rig in combination with Yan teaches the system of claim 1, wherein the virtual processing unit is configured to: be built by the multi-protocol driver in memory, if there is no physical implementation of the VPIs; and/or map physical cache of a physical (quantum) processing unit into the main memory and thereby provide cache coherency throughout the system. (in [0124] The QMMU and the Qache are shown in detail in FIG. 9. The QMMU and Qache operate with the following: Ci Classical Shared Variable 921, which is a classical bitstring for communicating state/sharing data between QPU and CPU cores; Qi Gate Command 922, which are gate commands for triggering specified state manipulation of qubits Qi from i=0 to i=N, where N is the number of qubits allocated to that QPU core; Qi State 923, which is the last measured state of Qi (if gate has been applied, this Qache entry is marked dirty in the hygiene mask., if measured state is still valid, hygiene mask holds clean for this Qache entry); Qi State Hygiene Mask 924 indicates if quantum information exists in the system for Qi or if Qi contains a bit of classical information. A Coherency Agent 925 uses a cache coherence scheme (snooping, directory based, etc.) to maintain Qache coherency [or map physical cache of a physical (quantum) processing unit into the main memory and thereby provide cache coherency throughout the system] across the multiprocessor system. )
Regarding independent claim 19, Rig teaches a method of performing virtualized quantum processing, the method comprising, (in [0049] Each of the example quantum computing systems 103A, 103B operates as a quantum computing resource in the computing system 101 [performing virtualized quantum processing]. The other resources 107 may include additional quantum computing resources (e.g., quantum computing systems, quantum virtual machines (QVMs) or quantum simulators) as well as classical (non-quantum) computing resources such as, for example, digital microprocessors, specialized co-processor units (e.g., graphics processing units (GPUs), cryptographic co-processors, etc.), special purpose logic circuitry (e.g., field programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), etc.), systems-on-chips (SoCs), etc., or combinations of these and other types of computing modules.)
initializing qubits with classical meta information; initializing gate circuits between the qubits with the classical meta information; (in [0065] In some implementations, a quantum computing system can operate using gate-based models for quantum computing. For example, the qubits can be initialized in an initial state [initializing qubits with classical meta information; initializing gate circuits between the qubits with the classical meta information], and a quantum logic circuit comprised of a series of quantum logic gates can be applied to transform the qubits and extract measurements representing the output of the quantum computation. Individual qubits may be controlled by single-qubit quantum logic gates, and pairs of qubits may be controlled by two-qubit quantum logic gates (e.g., entangling gates that are capable of generating entanglement between the pair of qubits). In some implementations, a quantum computing system can operate using adiabatic or annealing models for quantum computing. For instance, the qubits [initializing qubits with classical meta information; initializing gate circuits between the qubits with the classical meta information] can be initialized in an initial state, and the controlling Hamiltonian [with classical meta information] can be transformed adiabatically by adjusting control parameters [initializing qubits with classical meta information; initializing gate circuits between the qubits with the classical meta information] to another state that can be measured to obtain an output of the quantum computation [initializing qubits with classical meta information; initializing gate circuits between the qubits with the classical meta information]… )
processing a given quantum circuit by transforming all the qubits by unitary matrices; (in [0085] Hardware and software systems for virtualized quantum-classical computing are described as follows with reference to the figures. The system capabilities and core concepts that underpin the virtualization of quantum-classical compute systems and their provisioning to multiple simultaneous users are covered starting from the qubit level (for example, the quantum integrated circuit) and including: the dynamical creation and definition of qubit plaquettes with specific performance attributes and characteristics [process a given quantum circuit by transforming all qubits by unitary matrices]; the hosting on a single QPU multiple user instances connected to those plaquettes and the provisioning of classical resources to support each such instance in a quantum classical architecture, as demanded by the specific job or user… [0102] The algorithm may be compiled (503) through a system programming interface (403). The compilation may include: a translation of an algorithm to a set of machine executable instructions, for instance a set of executable gates and readout operations; translation of an algorithm and/or instructions to another algorithm and/or instructions, for instance reducing the number of gate operations required to approximately implement a unitary [process a given quantum circuit by transforming all qubits by unitary matrices] to optimize the algorithms efficiency; providing information about potential plaquettes available to perform the algorithm, for instance their connectivity, and/or available gate-set, and/or benchmarks; and providing information about other compilations, for instance if a requested subroutine has been compiled for use with a previous algorithm.)
measuring the qubits to retrieve classical information; and processing the classical information; (in [0031] In some instances, a method for calculating a price for use of a configuration of qubits and qubit-qubit links on one or more quantum processor units [measuring the qubits to retrieve classical information; and processing the classical information] by a user for running a computer program, may comprise: accessing a first database by a computer processor unit to collect design characteristics of the one or more quantum processor units, including inferred characteristics pertaining to the expressiveness of the one or more quantum processor units, wherein the inferred characteristics include instruction availability; accessing a second database by the computer processor unit to collect [processing the classical information] measurements of physical characteristics of the one or more quantum processor units [measuring the qubits to retrieve classical information; and processing the classical information]; accessing a third database by the computer processor unit to collect characteristics of a specific user's request; and determining the price using data collected from the first, second and third databases. And in [0065] In some implementations, a quantum computing system can operate using gate-based models for quantum computing. For example, the qubits can be initialized in an initial state, and a quantum logic circuit comprised of a series of quantum logic gates can be applied to transform the qubits and extract measurements representing the output of the quantum computation [measuring the qubits to retrieve classical information; and processing the classical information]. Individual qubits may be controlled by single-qubit quantum logic gates, and pairs of qubits may be controlled by two-qubit quantum logic gates (e.g., entangling gates that are capable of generating entanglement between the pair of qubits). In some implementations, a quantum computing system can operate using adiabatic or annealing models for quantum computing. For instance, the qubits can be initialized in an initial state, and the controlling Hamiltonian can be transformed adiabatically by adjusting control parameters to another state that can be measured to obtain an output of the quantum computation [measuring the qubits to retrieve classical information; and processing the classical information]...)
While Rig teaches the information processing stack for processing claimed information in a distributed/cloud computing environment. One of ordinary skill in art would understand that provisioned virtual machine/containers for processing information in a cloud computing environment include claimed elements as noted above.
Additionally Yan expressly teaches that provisioned virtual machine/containers for processing information in a cloud computing environment include claimed elements wherein, preferably, the method is implemented via an information process stack, or computational stack, comprising: a hardware layer, an operating system coupled to the hardware layer, and a container environment coupled to the operating system (in [0038] FIG. 4 illustrates generalized hardware and software components of a general-purpose computer system, such as a general-purpose computer system having an architecture similar to that shown in FIG. 1. The computer system 400 [wherein, preferably, the method is implemented via an information process stack, or computational stack, comprising: a hardware layer,] is often considered to include three fundamental layers: (1) a hardware layer or level 402 […hardware layer …]; (2) an operating-system layer or level 404 [a hardware layer, an operating system coupled to the hardware layer, and a container environment coupled to the operating system]; and (3) an application-program layer or level 406. The hardware layer 402 includes one or more processors 408, system memory 410, various different types of input-output (“I/O”) devices 410 and 412, and mass-storage devices 414…. [0043] ... FIG. 5C illustrates the OSL-virtualization approach. In FIG. 5C, as in previously discussed FIG. 4, an operating system 404 runs above the hardware 402 of a host computer [a hardware layer, an operating system coupled to the hardware layer, and a container environment coupled to the operating system] The operating system provides an interface for higher-level computational entities, the interface including a system-call interface 428 and exposure to the non-privileged instructions and memory addresses and registers 426 of the hardware layer 402. However, unlike in FIG. 5A, rather than applications running directly above the operating system, OSL virtualization involves an OS-level virtualization layer 560 that provides an operating-system interface 562-564 to each of one or more containers 566-568 [a hardware layer, an operating system coupled to the hardware layer, and a container environment coupled to the operating system]. The containers, in turn, provide an execution environment for one or more applications, such as application 570 running within the execution environment provided by container 566. The container can be thought of as a partition of the resources generally available to higher-level computational entities through the operating system interface 430. While a traditional virtualization layer can simulate the hardware interface expected by any of many different operating systems. OSL virtualization essentially provides a secure partition of the execution environment provided by a particular operating system. As one example, OSL virtualization provides a file system to each container, but the file system provided to the container is essentially a view of a partition of the general file system provided by the underlying operating system [a hardware layer, an operating system coupled to the hardware layer, and a container environment coupled to the operating system]. In essence, OSL virtualization uses operating-system features, such as name space support, to isolate each container from the remaining containers so that the applications executing within the execution environment provided by a container are isolated from applications executing within the execution environments provided by all other containers. As a result, a container can be booted up much faster than a virtual machine, since the container uses operating-system-kernel features that are already available within the host computer. Furthermore, the containers share computational bandwidth, memory, network bandwidth, and other computational resources provided by the operating system. without resource overhead allocated to virtual machines and virtualization layers...)
Yan and Rig are analogous art because both involve developing information retrieval and processing techniques using machine learning systems and algorithms.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the prior art of retrieving and processing information in distributed-computer-systems, as disclosed by Yan with the method of developing information retrieval and processing computer system with quantum and classical compute resources provisionable to multiple users in distributed computing environments as disclosed by Rig.
One of ordinary skill in the arts would have been motivated to combine the methods and systems disclosed by Yan and Rig, as noted above.; Doing so allows for implementing systems based on cloud-computing interfaces that enable easy and straightforward configuration of virtual computing facilities, flexibility in the types of applications and operating systems that can be configured, and other functionalities that are useful cloud-computing users, (Yan, 0037).
Regarding claim 20, the rejection of claim 19 is incorporated and Rig in combination with Yan teaches the method of 19, wherein the processing of the classical information is performed by virtual hardware processors that are hardware agnostic, and wherein, preferably, the virtual hardware processors are implemented via a virtual quantum computer system comprising: (in [0085] Hardware and software systems for virtualized quantum-classical [wherein the processing of the classical information is performed by virtual hardware processors that are hardware agnostic, and wherein, preferably, the virtual hardware processors are implemented via a virtual quantum computer system comprising: as virtualization that occurs in a computing environment using known stacks for processing information that can run on any server environment] computing are described as follows with reference to the figures. The system capabilities and core concepts that underpin the virtualization of quantum-classical compute systems and their provisioning to multiple simultaneous users are covered starting from the qubit level (for example, the quantum integrated circuit) and including: the dynamical creation and definition of qubit plaquettes with specific performance attributes and characteristics]; the hosting on a single QPU multiple user instances connected to those plaquettes and the provisioning of classical resources to support each such instance in a quantum classical architecture, as demanded by the specific job or user… [0102] The algorithm may be compiled (503) through a system programming interface [wherein the processing of the classical information is performed by virtual hardware processors that are hardware agnostic, and wherein, preferably, the virtual hardware processors are implemented via a virtual quantum computer system comprising: as virtualization that occurs in a computing environment using known stacks for processing information that can run on any server environment] (403). The compilation may include: a translation of an algorithm to a set of machine executable instructions, for instance a set of executable gates and readout operations; translation of an algorithm and/or instructions to another algorithm and/or instructions, for instance reducing the number of gate operations required to approximately implement a unitary to optimize the algorithms efficiency; providing information about potential plaquettes available to perform the algorithm, for instance their connectivity, and/or available gate-set, and/or benchmarks; and providing information about other compilations, for instance if a requested subroutine has been compiled for use with a previous algorithm. And in[0051] In some instances, programs can be formatted as source code that can be rendered in human-readable form (e.g., as text) and can be compiled, for example, by a compiler running on the servers 108 [wherein the processing of the classical information is performed by virtual hardware processors that are hardware agnostic, and wherein, preferably, the virtual hardware processors are implemented via a virtual quantum computer system comprising:], on the quantum computing systems 103, or elsewhere… )
a main memory; one or more memory bus systems coupled to the main memory; (in [0122] FIG. 7 is a representation of an example virtualizable hybrid quantum-classical processor unit, and FIG. 8 is a representation of an example of two coherent virtualizable hybrid quantum-classical processor units. The processor units 700, 800 comprise: independent QPU cores 701, 801 where each box in the figure corresponds to a thread of execution for an array of N qubit(s); independent CPU cores 702, 802 where each box corresponds to a classical thread of execution (which may be processing an instance, doing minimum weight perfect matching, etc.); local Qache buses 703, 803 which are tightly coupled memory [comprising: a main memory; one or more memory bus systems coupled to the main memory] shared between all the QPU and CPU cores on their corresponding hybrid processing units (HPUs); processor-to-processor (system) Qache buses 804, 904 which enable coherency of the hybrid shared cache across multiple hybrid processing units; local Qache copies 705, 805, 905, which are cache copies local to a given hybrid processing unit that is managed by that hybrid processor's Quantum Memory Management Unit (QMMU) [comprising: a main memory; one or more memory bus systems coupled to the main memory] and holds coherent copies of all hybrid classical variables and state readout for the corresponding entire system; hybrid virtualization managers (hypervisors) 706, 806, 906 which load and manage jobs for execution, and part of managing these jobs includes configuring and maintaining the QMMU.…)
one or more physical processing units that have access to the main memory, preferably via at least one memory bus system; (in [0122] FIG. 7 is a representation of an example virtualizable hybrid quantum-classical processor unit, and FIG. 8 is a representation of an example of two coherent virtualizable hybrid quantum-classical processor units. The processor units 700, 800 comprise: independent QPU cores 701, 801 where each box in the figure corresponds to a thread of execution for an array of N qubit(s); independent CPU cores 702, 802 where each box corresponds to a classical thread of execution (which may be processing an instance, doing minimum weight perfect matching, etc.); local Qache buses [one or more physical processing units that have access to the main memory, preferably via at least one memory bus system] 703, 803 which are tightly coupled memory shared between all the QPU and CPU cores on their corresponding hybrid processing units (HPUs); processor-to-processor (system) Qache buses 804, 904 which enable coherency of the hybrid shared cache across multiple hybrid processing units; … [0123] The neighbor hybrid processor 809 is a second hybrid processor that sits on a cache coherent bus [one or more physical processing units that have access to the main memory, preferably via at least one memory bus system] with another hybrid processor. Examples of arbitrary parceling 810 of hybrid resources, which are arbitrary subsets of the available quantum and classical cores from the hybrid multi-processor that form the work units for execution of customer hybrid computation, are indicated in FIG. 8 for customers 1, 2 and 3 as 811, 812 and 813. All arbitrary subsets maintain tight coupling through the shared memory interface (system Qache bus) [one or more physical processing units that have access to the main memory, preferably via at least one memory bus system]. And in [0113] Commands for the waveform and readout engines (612-617) are provided by the classical compute functionality of the hybrid classical/quantum processor 611 (the “sequencers”). Soft processor(s) may be on the same FPGA as the waveform engine logic and hard processor(s) may be integrated on the same die as the FPGA/ASIC as the waveform engine. Processors are connected to the waveform engine via a high-bandwidth, low-latency (very much less than the coherence time) communications link/bus [one or more physical processing units that have access to the main memory, preferably via at least one memory bus system]…)
a data processing unit coupled to at least one of the one or more physical processing units, the data processing unit serving as a bridge between internal systems of the virtual quantum computer system and external systems; (As depicted in Fig. 1 and in [0040] The example computing system 101 can provide services to the user devices 110, for example, as a cloud-based or remote-accessed computer system, as a distributed computing resource, as a supercomputer or another type of high-performance computing resource, or in another manner. The computing system 101 or the user devices 110 may also have access to one or more other quantum computing systems (e.g., quantum computing resources that are accessible through the wide area network 115 [a data processing unit coupled to at least one of the one or more physical processing units, the data processing unit serving as a bridge between internal systems of the virtual quantum computer system and external systems], the local network 109 or otherwise). )
While Rig teaches the information processing stack for processing claimed information in a distributed/cloud computing environment. One of ordinary skill in art would understand that provisioned virtual machine/containers for processing information in a cloud computing environment include claimed elements as noted above.
Additionally Yan teaches in [0043] …FIG. 5C illustrates the OSL-virtualization approach. In FIG. 5C, as in previously discussed FIG. 4, an operating system 404 runs above the hardware 402 of a host computer [wherein the processing of the classical information is performed by virtual hardware processors that are hardware agnostic, and wherein, preferably, the virtual hardware processors are implemented via a virtual quantum computer system comprising]. The operating system provides an interface for higher-level computational entities, the interface including a system-call interface 428 and exposure to the non-privileged instructions and memory addresses and registers 426 of the hardware layer 402. However, unlike in FIG. 5A, rather than applications running directly above the operating system, OSL virtualization involves an OS-level virtualization layer 560 that provides an operating-system interface 562-564 to each of one or more containers 566-568. The containers, in turn, provide an execution environment for one or more applications, such as application 570 running within the execution environment provided by container 566. ….
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Yan and Rig for the same reasons disclosed above.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Rigetti et al. (US 20220084085, hereinafter ‘Rig’) in view of Yan et al. (US 20250199823, hereinafter ‘Yan’) in further view of Bocharov et al. (US 20210089953, hereinafter ‘Bo’).
Regarding claim 3, the rejection of claim 1 is incorporated and Rig in combination with Yan teaches the system of claim 1, wherein: the one or more cache coherency interconnects (in [0122] FIG. 7 is a representation of an example virtualizable hybrid quantum-classical processor unit, and FIG. 8 is a representation of an example of two coherent virtualizable hybrid quantum-classical processor units. The processor units 700, 800 comprise: independent QPU cores 701, 801 where each box in the figure corresponds to a thread of execution for an array of N qubit(s); independent CPU cores 702, 802 where each box corresponds to a classical thread of execution (which may be processing an instance, doing minimum weight perfect matching, etc.); local Qache buses 703, 803 which are tightly coupled memory shared between all the QPU and CPU cores on their corresponding hybrid processing units (HPUs); processor-to-processor (system) Qache buses 804, 904 which enable coherency of the hybrid shared cache across multiple hybrid processing units [wherein: the one or more cache coherency interconnects];… [0124] The QMMU and the Qache are shown in detail in FIG. 9. The QMMU and Qache operate with the following: Ci Classical Shared Variable 921, which is a classical bitstring for communicating state/sharing data between QPU and CPU cores [the initialization of the qubits with classical meta information includes performing memory pattern translation as shared bitstring memory translations between QPU and CPU cores]; Qi Gate Command 922, which are gate commands for triggering specified state manipulation of qubits Qi from i=0 to i=N, where N is the number of qubits allocated to that QPU core; Qi State 923, which is the last measured state of Qi (if gate has been applied, this Qache entry is marked dirty in the hygiene mask., if measured state is still valid, hygiene mask holds clean for this Qache entry); Qi State Hygiene Mask 924 indicates if quantum information exists in the system for Qi or if Qi contains a bit of classical information. A Coherency Agent 925 uses a cache coherence scheme (snooping, directory based, etc.) to maintain Qache coherency across the multiprocessor system.)
wherein, preferably, the memory pattern translation comprises translation to one or both of Bloch registers and/or neural networks. (in [0119] The second aspect is that the quantum gate instructions need to be available with extremely low latency to all the individual control processors for each qubit. Continuing with the example above, if the users program performs a gate on a qubit, and that gets allocated to q0 for one iteration [wherein, preferably, the memory pattern translation comprises translation to one or both of Bloch registers], but then is reallocated to q10 for another iteration, the control system for q10 needs to have that instruction. This aspect is represented by the Qi unitary command discussed in more detail below. The translation table discussed below is what holds the current mapping of programs to qubit resources [wherein, preferably, the memory pattern translation comprises translation to one or both of Bloch registers]. The programs are written to use “virtual” qubit addresses, which this table then translates to physical qubits. [0120] The description below encompasses a range of system scales, from the case where all qubits could be controlled by a single classical compute chip, so that the low-latency shared memory could be implemented as a multi-port memory register [wherein, preferably, the memory pattern translation comprises translation to one or both of Bloch registers for storing qubit information in memory for information processing], to cases where communication between chips, boards, and chassis are needed. In these later cases, tradeoffs between interconnect density and latency are considered. )
Rig teaches the using of memory to store and processing quantum information using memory registers as claimed Bloch registers. Examiner notes that one of ordinary skill in the art would understand the Bloch sphere is a geometrical representation of the space of pure states of a qubit, thus any memory capable of storing quantum information using registers is within in the scope of claimed Bloch registers, as this is not considered a term of art in computer architecture, see MPEP 2111.
Additionally, Bo expressly teaches wherein, preferably, the memory pattern translation comprises translation to one or both of Bloch registers and/or neural networks. (in [0035] FIG. 3 illustrates a quantum circuit comprising two quantum gates. In FIG. 3, a qubit in a first state |ψ.sub.1, represented by the Bloch sphere 302, is transformed by unitary operation U 304 to a qubit in state |ψ.sub.2, as represented by Bloch sphere 306 [wherein, preferably, the memory pattern translation comprises translation to one or both of Bloch registers], which is, in turn, transformed by unitary operation V 308 to place the qubit in state |ψ.sub.3, as represented by Bloch sphere 310. This quantum circuit can be represented as the gate sequence UV which transforms the qubit as follows:…; And in [0017] …The quantum prediction circuit 104 is a unitary circuit that acts to transform a quantum state of an input qubit string (also referred to as a qubit register [wherein, preferably, the memory pattern translation comprises translation to one or both of Bloch registers] or input vector) that it receives from the state preparation circuit 102. The state preparation circuit 102 prepares this input qubit string by amplitude encoding a subset 114 of a time-sequential sequence 116 of data bits (e.g., represented as “input x” in FIG. 1). The quantum prediction circuit 104 includes a sequence of quantum gates (not shown) that each apply a discrete state transformation to one or more of qubits in the qubit register [wherein, preferably, the memory pattern translation comprises translation to one or both of Bloch registers]… [0029] … FIG. 2B shows an arbitrary qubit state vector |ψcustom-character within the unit sphere shown in FIG. 2A…. The representation of the state of a qubit shown in FIG. 2B is referred to as a Bloch sphere [wherein, preferably, the memory pattern translation comprises translation to one or both of Bloch registers]. )
Bo, Yan and Rig are analogous art because both involve developing information retrieval and processing techniques using machine learning systems and algorithms.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the prior art of retrieving and processing information using systems and methodologies that leverage the advantages of amplitude encoding for modeling qubit states using quantum circuits and unitary operations, as disclosed by Bo with the method of developing information retrieval and processing computer system with quantum and classical compute resources provisionable to multiple users in distributed computing environments as collectively disclosed by Yan and Rig.
One of ordinary skill in the arts would have been motivated to combine the methods and systems disclosed by Bo,Yan and Rig, as noted above.; Doing so allows for implementing systems and methodologies that leverage the advantages of amplitude encoding as represented by Bloch sphere to help process qubit states using quantum circuits and unitary operations based on a variational approach designed for quantum devices with less processing power, (Bo, 0015 & 0033-0035).
Claims 4, 5 and 25 are rejected under 35 U.S.C. 103 Rigetti et al. (US 20220084085, hereinafter ‘Rig’) in view of Yan et al. (US 20250199823, hereinafter ‘Yan’) in further view of Hogaboam et al. (US 20210173660, hereinafter ‘Hoga’).
Regarding claim 4, the rejection of claim 1 is incorporated and Rig in combination with Yan teaches the system of claim 1, wherein optimization parameters in a memory representation of quantum information are provided as meta information from an application layer via a kernel scheduler (API 5D) to an inner core of the operating system to efficiently use overall transactional computation power of the information process stack. (in [0056] In some implementations, all or part of the computing environment operates as a cloud-based quantum computing (QC) environment [wherein optimization parameters in a memory representation of quantum information are provided as meta information from an application layer via a kernel scheduler (API 5D) to an inner core of the operating system to efficiently use overall transactional computation power of the information process stack], and the servers 108 operate as a host system for the cloud-based QC environment. The cloud-based QC environment may include software elements that operate on both the user devices 110 and the computer system 101 and interact with each other over the wide area network 115. For example, the cloud-based QC environment [quantum information are provided as meta information from an application layer via a kernel scheduler (API 5D) to an inner core of the operating system to efficiently use overall transactional computation power of the information process stack] may provide a remote user interface, for example, through a browser or another type of application on the user devices 110. The remote user interface may include, for example, a graphical user interface or another type of user interface that obtains input provided by a user of the cloud-based QC environment. In some cases the remote user interface includes, or has access to, one or more application programming interfaces (APIs) [application layer via a kernel scheduler (API 5D)], command line interfaces, graphical user interfaces, or other elements that expose the services of the computer system 101 to the user devices 110.)
While Rig and Yan teaches the system for information processing using cloud computing environments and virtualization methods, as noted above, one of ordinary skill would understand the use of kernels to executing computing instructions/operations as noted above.
Additionally, Hoga teaches the use of kernels to executing computing instructions/operations, in [0087] Qubit map and route layer 904 maps qubits of the quantum processor to the physical (or virtual) qubits of the quantum processor and operation scheduling layer 905 schedules quantum operations for execution on the qubits [wherein optimization parameters in a memory representation of quantum information are provided as meta information from an application layer via a kernel scheduler (API 5D) to an inner core of the operating system to efficiently use overall transactional computation power of the information process stack]. In one embodiment, the qubit map and route layer 904 is provided with data related to the physical arrangement of qubits in the quantum processor in order to render mapping decisions. In addition, both the qubit map and route layer 904 and operation scheduling layer 905 may construct and/or utilize Directed Acyclic Graph (DAG) 906 specifying data and/or resource dependencies between the quantum gate operations. The operation schedule is specified in a quantum runtime level language 911A, a quantum simulator level language 911B, or one or more other quantum execution language types such as the Intel CC Gen1 LL and the Python PycQED LL…. [0089] In one embodiment, the output from the compilation phase above is the ICQPX intermediate representation and a control flow graph of the classical instruction mix suitable for execution on the underlying virtual machine. Multiple program “kernels” [quantum information are provided as meta information from an application layer via a kernel scheduler (API 5D) to an inner core of the operating system to efficiently use overall transactional computation power of the information process stack] can thus be passed to the virtual machine layer in order to execute the program written in the higher level language.
Hoga, Yan and Rig are analogous art because both involve developing information retrieval and processing techniques using machine learning systems and algorithms.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the prior art of retrieving and processing information in distributed computing environments for quantum computing task, as disclosed by Hoga with the method of developing information retrieval and processing computer system with quantum and classical compute resources provisionable to multiple users in distributed computing environments as collectively disclosed by Yan and Rig.
One of ordinary skill in the arts would have been motivated to combine the methods and systems disclosed by Hoga, Yan and Rig, as noted above.; Doing so allows for new instruction set architectures to be devised for quantum computing, (Hoga, 0100).
Regarding claim 5, the rejection of claim 1 is incorporated and Rig in combination with Yan teaches the system of claim 1, wherein the information process stack is further configured to: transfer, via a kernel scheduler API, the classical meta information required for the quantum gate circuit to a memory pattern translation layer associated with the operating system. ((in [0031] In some instances, a method for calculating a price for use of a configuration of qubits and qubit-qubit links on one or more quantum processor units by a user for running a computer program, may comprise: accessing a first database by a computer processor unit to collect design characteristics of the one or more quantum processor units [the classical meta information required for the quantum gate circuit], including inferred characteristics pertaining to the expressiveness of the one or more quantum processor units, wherein the inferred characteristics include instruction availability; accessing a second database by the computer processor unit to collect [wherein the information process stack is further configured to: transfer, via a kernel scheduler API, the classical meta information required for the quantum gate circuit to a memory pattern translation layer associated with the operating system as processed stored to claimed memory pattern translation layer] measurements of physical characteristics of the one or more quantum processor units accessing a third database by the computer processor unit to collect characteristics of a specific user's request; and determining the price using data collected from the first, second and third databases [wherein the information process stack is further configured to: transfer, via a kernel scheduler API, the classical meta information required for the quantum gate circuit to a memory pattern translation layer associated with the operating system as processed stored to claimed memory pattern translation layer for retrievial]. And in [0065] In some implementations, a quantum computing system can operate using gate-based models for quantum computing. For example, the qubits can be initialized in an initial state, and a quantum logic circuit comprised of a series of quantum logic gates can be applied to transform the qubits and extract measurements representing the output of the quantum computation [the classical meta information required for the quantum gate circuit]. Individual qubits may be controlled by single-qubit quantum logic gates, and pairs of qubits may be controlled by two-qubit quantum logic gates (e.g., entangling gates that are capable of generating entanglement between the pair of qubits). In some implementations, a quantum computing system can operate using adiabatic or annealing models for quantum computing. For instance, the qubits can be initialized in an initial state, and the controlling Hamiltonian can be transformed adiabatically by adjusting control parameters to another state that can be measured to obtain an output of the quantum computation [wherein the information process stack is further configured to: transfer, via a kernel scheduler API, the classical meta information required for the quantum gate circuit to a memory pattern translation layer associated with the operating system as stored quantum storage information for performing the adjustment of control parameters]...)
Additionally, Hoga teaches the use of kernels as executable instructions as noted in the claim three rejection and in [0080] Quantum run-time (QRT) 703 requests thread assignments from the quantum processor driver API 704 for each qubit as well as ring buffer resource locations, memory alignments, data widths, sync barriers, and sets these up for program execution. The QRT 703 loads the natively compiled kernel into all DMA queues and the processor begins executing when the kernel instructions are loaded into the ring buffer queues and the head/tail pointers diverge. Each qubit thread executes a single instruction in parallel through a global clocking and synchronization signal (cycle). Multiple qubit operations (CCNOT, CNOT, etc. . . . ) of qubit threads are co-located on the same QMS (Quantum Multiprocessor Stream) and coordinate multi-qubit operations through synchronization between threads using a local shared memory 650 or across QMSs using the interconnect shared memory space [wherein the information process stack is further configured to: transfer, via a kernel scheduler API, the classical meta information required for the quantum gate circuit to a memory pattern translation layer associated with the operating system as stored information for performing multi-qubit operations in a share memory distributed computing environment]. [0081] Qubit measurements [the classical meta information required for the quantum gate circuit] are issued to each qubit stream as the final instruction in the stream. The measurement arbiter gathers all measurement instructions across the threads and then triggers the measurement process on a measurement cycle [wherein the information process stack is further configured to: transfer, via a kernel scheduler API, the classical meta information required for the quantum gate circuit to a memory pattern translation layer associated with the operating system as stored information for performing qubit operations in a share memory distributed computing environment]… [0087] Qubit map and route layer 904 maps qubits of the quantum processor to the physical (or virtual) qubits of the quantum processor and operation scheduling layer 905 schedules quantum operations for execution on the qubits. In one embodiment, the qubit map and route layer 904 is provided with data related to the physical arrangement of qubits in the quantum processor in order to render mapping decisions [wherein the information process stack is further configured to: transfer, via a kernel scheduler API, the classical meta information required for the quantum gate circuit to a memory pattern translation layer associated with the operating system as stored information for performing qubit pattern operations in a share memory distributed computing environment rendering decisions]…
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Hoga, Yan and Rig for the same reasons disclosed above.
Regarding claim 25, the rejection of claim 19 is incorporated and the limitations are similar with claim 4 and are rejected under the same rationale.
Claims 8 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Rigetti et al. (US 20220084085, hereinafter ‘Rig’) in view of Yan et al. (US 20250199823, hereinafter ‘Yan’) in view of Leipold et al. (US 20190392342, hereinafter ‘Le’).
Regarding claim 8, the rejection of claim 1 is incorporated and Rig in combination with Yan teaches the system of claim 1, further comprising a quantum processing unit (QPU) that is configured to utilize an arithmetic and logic unit (ALU) as a piece of software in processor kernel extensions of a hybrid quantum computing operating system, preferably carried out by physical resources of the hardware layer (780). (in [0058] In an example implementation of a cloud-based QC environment, the servers 108 may operate as a cloud provider that dynamically manages the allocation and provisioning of physical computing resources (e.g., GPUs, CPUs, QPUs, etc.) [further comprising a quantum processing unit (QPU) that is configured to utilize an arithmetic and logic unit (ALU) as a piece of software in processor kernel extensions of a hybrid quantum computing operating system, preferably carried out by physical resources of the hardware layer (780)]. Accordingly, the servers 108 may provide services by defining virtualized resources for each user account. For instance, the virtualized resources may be formatted as virtual machine images, virtual machines, containers, or virtualized resources that can be provisioned for a user account and configured by a user…; Examiner notes the system operations as an software/kernel extension of a hybrid computing system, in [0060] In some implementations, all or part of the computing system 101 operates as a hybrid computing environment. For example, quantum programs can be formatted as hybrid classical/quantum programs that include instructions for execution by one or more quantum computing resources and instructions for execution by one or more classical resources. The servers 108 can allocate quantum and classical computing resources in the hybrid computing environment [computing environment includes the use of arithmetic and logic unit (ALU) as a piece of software in processor kernel extensions of ], and delegate programs to the allocated computing resources for execution. The quantum computing resources in the hybrid environment may include, for example, one or more quantum processing units (QPUs), one or more quantum virtual machines (QVMs), one or more quantum simulators, or possibly other types of quantum resources… [0215] Some of the processes and logic flows described in this specification can be performed by one or more programmable processors executing one or more computer programs to perform actions by operating on input data and generating output. The processes and logic flows can also be performed by, and apparatus can also be implemented as, special purpose logic circuitry, e.g., an FPGA (field programmable gate array) or an ASIC (application specific integrated circuit).)
Rig teaches the provisioning virtualized resources to instantiate operations of claimed quantum processing unit, as noted above. One of ordinary skill in the art would understanding the provisioning resources in a server/cloud computing environment includes the use of arithmetic and logic unit (ALU) as a piece of software in processor kernel extensions of
Le expressly teaches the provisioning resources in a server/cloud computing environment includes the use of arithmetic and logic unit (ALU) as a piece of software in processor kernel extensions of , in [0140] A high level block diagram illustrating an example quantum processing unit [further comprising a quantum processing unit (QPU) that is configured to utilize an arithmetic and logic unit (ALU) as a piece of software in processor kernel extensions of a hybrid quantum computing operating system, preferably carried out by physical resources of the hardware layer] in more detail is shown in FIG. 14. The quantum processing unit, generally referenced 280, comprises an irreversible classic computing core 286, clock and timing circuit 308, command pulse generator 294, quantum command pointer 284, data input unit 306, quantum computing core 296, quantum memory refresh unit 310, classic arithmetic logic unit (ALU) [provisioning resources in a server/cloud computing environment includes the use of arithmetic and logic unit (ALU) as a piece of software in processor kernel extensions of ] 290, partial measurement unit 292, and operation completion detection unit 288. Quantum computing core 296 comprises quantum entanglement circuit 302, quantum error correction circuit 304, proximity state readout circuit 300, and quantum memory unit/ancillary state storage/quantum memory stabilization circuit 298.
Le, Yan and Rig are analogous art because both involve developing information retrieval and processing techniques using machine learning systems and algorithms.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the prior art of retrieving and processing information using quantum computing machine architecture that includes a classic computing core as well as a quantum computing core, as disclosed by Le with the method of developing information retrieval and processing computer system with quantum and classical compute resources provisionable to multiple users in distributed computing environments as collectively disclosed by Yan and Rig.
One of ordinary skill in the arts would have been motivated to combine the methods and systems disclosed by Le, Yan and Rig, as noted above.; Doing so allows the development and implementation of a hybrid quantum computing machine for measuring one or more qubits that yield classical electronic signals that are input to a classic ALU for performing computations with detected outputs. (Le, 0145).
Regarding claim 14, the rejection of claim 1 is incorporated and Rig in combination with Yan teaches the system of claim 1, wherein the information process stack is configured to: store data in shared memory and process the data using virtual processor instances (VPIs), wherein the VPIs are processor kernel extensions comprising: a plurality of subcomponents including a multi-protocol driver (MPD), a meta protocol controller (MPC), (in [0085] Hardware and software systems for virtualized quantum-classical computing are described as follows with reference to the figures [wherein the information process stack is configured to: store data in shared memory and process the data using virtual processor instances (VPIs)]. The system capabilities and core concepts that underpin the virtualization of quantum-classical compute systems and their provisioning to multiple simultaneous users are covered starting from the qubit level (for example, the quantum integrated circuit) and including: the dynamical creation and definition of qubit plaquettes with specific performance attributes and characteristics; the hosting on a single QPU multiple user instances connected to those plaquettes and the provisioning of classical resources to support each such instance in a quantum classical architecture, as demanded by the specific job or user. And in [0122] FIG. 7 is a representation of an example virtualizable hybrid quantum-classical processor unit, and FIG. 8 is a representation of an example of two coherent virtualizable hybrid quantum-classical processor units. The processor units 700, 800 comprise: independent QPU cores 701, 801 where each box in the figure corresponds to a thread of execution for an array of N qubit(s); independent CPU cores 702, 802 where each box corresponds to a classical thread of execution (which may be processing an instance, doing minimum weight perfect matching, etc.); local Qache buses 703, 803 which are tightly coupled memory shared [and a bus system configured to provide the subcomponents access to shared memory in the main memory] between all the QPU and CPU cores on their corresponding hybrid processing units (HPUs); processor-to-processor (system) Qache buses 804, 904 which enable coherency of the hybrid shared cache across multiple hybrid processing units; local Qache copies 705, 805, 905, which are cache copies local to a given hybrid processing unit that is managed by that hybrid processor's Quantum Memory Management Unit (QMMU) and holds coherent copies of all hybrid classical variables and state readout for the corresponding entire system; hybrid virtualization managers (hypervisors) [wherein the VPIs are processor kernel extensions comprising: a plurality of subcomponents including a multi-protocol driver (MPD)] 706, 806, 906 which load and manage jobs for execution, and part of managing these jobs includes configuring and maintaining the QMMU; Qache Virtualization Modules 707, 807, 907 where the QMMU maintains cache coherence between the local qache copy and the local qache copies of other hybrid processors on the system qache bus…; And in [0028] In some aspects of what is described here, monolithic quantum-classical hybrid computing resources may be dynamically partitioned and virtualized into multiple different and independently-saleable (as a resource to a user) parcels. These parcels may comprise configurations of qubits and qubit-qubit links on one or more quantum processor units for use by users for running computer programs. This virtualization may extend from the qubit level up through the control system, and including auxiliary classical infra/compute resources for demanding hybrid workloads and jobs [a plurality of subcomponents including a multi-protocol driver (MPD), a meta protocol controller (MPC)]. An order matching system can match a demand queue to a set of available dynamically provisioned quantum-classical resources, as part of a front-end system for a user to reserve, provision, and purchase credits for, or time on, hybrid quantum-classical resources of a certain desired performance level, and for systems for monitoring and metering the use of these resources to provide an account bill or usage statement. Furthermore, in some instances, each qubit control signal may be independently controlled by a thread of computation [a plurality of subcomponents including a multi-protocol driver (MPD), a meta protocol controller (MPC)], implemented by a CPU scheduling operations on the spooler. These threads are synchronized, either with explicit signals, or through deterministic timing. This makes it very natural to allocate a collection of control threads (i.e. those associated with a specific subset of qubits) to each user to natively support multi-tenancy of the hybrid quantum-classical computing resources.)
While Rig teaches the information processing stack for processing claimed information in a distributed/cloud computing environment. One of ordinary skill in art would understand that provisioned virtual machine/containers for processing information in a cloud computing environment include claimed elements as noted above.
Additionally Yan expressly teaches that provisioned virtual machine/containers for processing information in a cloud computing environment include claimed elements, in [0038] FIG. 4 illustrates generalized hardware and software components of a general-purpose computer system, such as a general-purpose computer system having an architecture similar to that shown in FIG. 1. The computer system 400 is often considered to include three fundamental layers: (1) a hardware layer or level 402; (2) an operating-system layer or level 404; and (3) an application-program layer or level 406. The hardware layer 402 includes one or more processors 408, system memory 410, various different types of input-output (“I/O”) devices 410 and 412, and mass-storage devices 414… The operating system includes many internal components and modules, including a scheduler 442, memory management 444, a file system 446, device drivers 448 [wherein the VPIs are processor kernel extensions comprising: a plurality of subcomponents including a multi-protocol driver (MPD), a meta protocol controller (MPC)], and many other components and modules… [0040] For all of these reasons, a higher level of abstraction, referred to as the “virtual machine,” [wherein the information process stack is configured to: store data in shared memory and process the data using virtual processor instances (VPIs), wherein the VPIs are processor kernel extensions comprising] has been developed and evolved to further abstract computer hardware in order to address many difficulties and challenges associated with traditional computing systems, including the compatibility issues discussed above. FIGS. 5A-D illustrate several types of virtual machine and virtual-machine execution environments. FIGS. 5A-B use the same illustration conventions as used in FIG. 4. FIG. 5A shows a first type of virtualization. The computer system 500 in FIG. 5A includes the same hardware layer 502 as the hardware layer 402 shown in FIG. 4. However, rather than providing an operating system layer directly above the hardware layer, as in FIG. 4, the virtualized computing environment illustrated in FIG. 5A features a virtualization layer 504 that interfaces through a virtualization-layer/hardware-layer interface 506, equivalent to interface 416 in FIG. 4, to the hardware. The virtualization layer provides a hardware-like interface 508 to a number of virtual machines, such as virtual machine 510, executing above the virtualization layer in a virtual-machine layer 512. Each virtual machine includes one or more application programs or other higher-level computational entities packaged together with an operating system, referred to as a “guest operating system,” such as application 514 and guest operating system 516 packaged together within virtual machine 510 [wherein the information process stack is configured to: store data in shared memory and process the data using virtual processor instances (VPIs), wherein the VPIs are processor kernel extensions comprising]. Each virtual machine is thus equivalent to the operating-system layer 404 and application-program layer 406 in the general-purpose computer system shown in FIG. 4. Each guest operating system within a virtual machine interfaces to the virtualization-layer interface 508 rather than to the actual hardware interface 506. The virtualization layer partitions hardware resources into abstract virtual-hardware layers to which each guest operating system within a virtual machine interfaces. The guest operating systems within the virtual machines, in general, are unaware of the virtualization layer and operate as if they were directly accessing a true hardware interface. The virtualization layer ensures that each of the virtual machines currently executing within the virtual environment receive a fair allocation of underlying hardware resources and that all virtual machines receive sufficient resources to progress in execution. The virtualization-layer interface 508 may differ for different guest operating systems…)
Le expressly teaches that provisioned virtual machine/containers for processing information in a cloud computing environment include claimed elements, in [0018] Direct memory access (DMA) [… a bus system configured to provide the subcomponents access to shared memory in the main memory and to handle direct memory access (DMA) exchanges involving the subcomponents.] engine 112 accesses memory, such as system memory, independent of another processor such as a processor core of an external central processing unit (CPU), an external digital signal processor (DSP), or compute resources 130. The external CPU, any external DSP, and the compute resources 130 are able to process other tasks while the DMA engine 112 performs memory access operations. The DMA engine 112 includes circuitry and sequential elements that support one or more channels for transmitting memory access operations and receiving memory access responses. Besides system memory, the DMA engine 112 is also capable of transferring data with another device such as another processing unit, a hub, a peripheral device, and so forth… [0020] The apparatus 100 uses the circuitry of compute resources 130 of partition 110 to process tasks such as highly data parallel applications. The compute resources 130 includes the multiple compute units 140A-140C, each with multiple lanes 142. Each lane is also referred to as a SIMD unit or a SIMD lane. In some embodiments, the lanes 142 operate in lockstep. In various embodiments, the data flow within each of the lanes 142 is pipelined. Pipeline registers are used for storing intermediate results and circuitry for arithmetic logic units (ALUs) perform integer arithmetic […and an arithmetic and logic unit (ALU); …], floating-point arithmetic, Boolean logic operations, branch condition comparisons and so forth. These components are not shown for ease of illustration. Each of the computation units within a given row across the lanes 142 is the same computation unit… [0036] In some embodiments, the translated commands are sent to the kernel mode driver 230 via the input/output (I/O) driver 220. In one embodiment, an I/O control system call interface is used. Although a single driver, the input/output (I/O) driver 220, is shown, multiple drivers exist in a stack of drivers [wherein the VPIs are processor kernel extensions comprising: a plurality of subcomponents including a multi-protocol driver (MPD)] between the application 210 and a piece of hardware for processing a request targeted at the piece of hardware. In other embodiments, the translated commands are directly sent to the kernel mode driver 230. In various embodiments, the kernel mode driver 230 redirects I/O requests to the driver managing the target device object, such as file system driver 235 for a memory… [0038] The circuitry of the memory controller 242 in the hardware layer accesses the command group stored in the ring buffer 240. The command processor 244 uses interfaces to the memory controller 242 [… a meta protocol controller (MPC)] for accessing the commands stored on the ring buffer 240. The command processor 244 schedules the retrieved commands based on a task type of the commands…
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Le, Yan and Rig for the same reasons disclosed above
Regarding claim 15, the rejection of claim 14 is incorporated and Le further teaches the system of claim 14, wherein the multi-protocol driver (MPD) is configured to: function as a driver interface to the operating system; handle communication between subcomponents of virtual processor instances (VPIs), including a multi-protocol driver (MPD), a meta protocol controller (MPC) (in [0036] In some embodiments, the translated commands are sent to the kernel mode driver 230 via the input/output (I/O) driver 220. In one embodiment, an I/O control system call interface is used. Although a single driver, the input/output (I/O) driver 220, is shown, multiple drivers exist in a stack of drivers [wherein the multi-protocol driver (MPD) is configured to: function as a driver interface to the operating system; handle communication between subcomponents of virtual processor instances (VPIs), including a multi-protocol driver (MPD)] between the application 210 and a piece of hardware for processing a request targeted at the piece of hardware. In other embodiments, the translated commands are directly sent to the kernel mode driver 230. In various embodiments, the kernel mode driver 230 redirects I/O requests to the driver managing the target device object, such as file system driver 235 for a memory… [0038] The circuitry of the memory controller 242 in the hardware layer accesses the command group stored in the ring buffer 240. The command processor 244 uses interfaces to the memory controller 242 [… a meta protocol controller (MPC)] for accessing the commands stored on the ring buffer 240. The command processor 244 schedules the retrieved commands based on a task type of the commands…
Examiner notes that Rig in combination with Yan teaches the virtual processor instances and virtualized instances of a Quantum processor as noted in claim 1 rejection and above.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Le, Yan and Rig for the same reasons disclosed above
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Rigetti et al. (US 20220084085, hereinafter ‘Rig’) in view of Yan et al. (US 20250199823, hereinafter ‘Yan’) in further view of Wang et al (US 20190349305, hereinafter ‘Wang’)
Regarding claim 9, the rejection of claim 1 is incorporated and Rig in combination with Yan teaches the system of claim 1, wherein the container environment includes a kernel scheduler API having MPI overlay functionality that provides known methods of thread parallelization to a programmer, such that the programmer can distribute applications and/or tasks within one application over arbitrary numbers of different processors and compute nodes that run a same version of the operating system. ([0150] When deploying an application on the HPU based services, the following decisions need to be made, either automatically by the compiler or other application, or by the user explicitly. First, should the application be constrained to a dedicated set of resources (to the exclusion of other users or applications) or can it target virtualized hardware, and then be mapped to physical hardware dynamically by the hypervisor? Second, various metrics need to be specified: how many QPUs to use (perhaps to parallelize the algorithm) [wherein the container environment includes a kernel scheduler API having]…)
While Rig teaches the use of parallel algorithms, there is no expressly teach that the disclosed parallelization/parallel algorithm as a message passing interface (MPI) parallelization algorithm.
Wang teaches parallelization/parallel algorithm as a message passing interface (MPI) parallelization algorithm, in [0031] Parallel applications are software programs written using parallel frameworks and running in a single-machine multi-thread [wherein the container environment includes a kernel scheduler API having MPI overlay functionality that provides known methods of thread parallelization to a programmer, such that the programmer can distribute applications …] and/or multi-machine multi-process way. Preferably, a parallel framework may be a parallel framework such as multiple threads, shared memory or message transmission. And in [0073] According to a preferred mode, Step S1 may comprise at least one of the following sub-steps: for every container in which high-performance parallel applications (hereinafter referred to as HPPAs) are run, the applications being run in the Linux kernel loaded with the PCI expansion card 10B, wherein each of the high-performance parallel applications is preferably written based on the MPI (Message Passing Interface) [wherein the container environment includes a kernel scheduler API having MPI overlay functionality that provides known methods of thread parallelization to a programmer, such that the programmer can distribute applications]; … And in [0032] A container, similar to a virtual machine, is a software sandbox, and also a security mechanism. It provides a program that is running with an isolated environment and strictly controls access of a program in the container to resources. Linux Namespaces mechanism provides a solid basis for container-based virtualization. Container may use this capability to isolate resources so that processes in different containers belong to different Namespaces, and are transparent to and independent of each other. Containers are light-weight virtualization technology at the operating-system level, and its underlying technologies [… tasks within one application over arbitrary numbers of different processors and compute nodes that run a same version of the operating system], Linux Namespace and Linux Control Group (Cgroup) are both entirely kernel properties, free from costs for any intermediate layer…Preferably, in the present invention, the first container and/or the second container is, for example, a software sandbox having an isolated environment and being created in a host machine using operating-system-based virtualization technology [… tasks within one application over arbitrary numbers of different processors and compute nodes that run a same version of the operating system].
Wang, Yan and Rig are analogous art because both involve developing information retrieval and processing techniques in distributed computing environments.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the prior art of implementing container communication method for parallel-applications and a system, as disclosed by Wang with the method of developing information retrieval and processing computer system with quantum and classical compute resources provisionable to multiple users in distributed computing environments as collectively disclosed by Yan and Rig.
One of ordinary skill in the arts would have been motivated to combine the methods and systems disclosed by Wang, Yan and Rig, as noted above.; Doing so allows for improving the processing capability and resource utilization of servers when running multiple virtual machines using the same physical machine, (Wang, 0002).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Rigetti et al. (US 20220084085, hereinafter ‘Rig’) in view of Yan et al. (US 20250199823, hereinafter ‘Yan’) in further of Katabarwa (US 20200334107, hereinafter ‘Kata’).
Regarding claim 13, the rejection of claim 1 is incorporated and Rig in combination with Yan teaches the system of claim 1, wherein (in [0064] Each of the example quantum computing systems 103A, 103B shown in FIG. 1 can perform quantum computational tasks by executing quantum machine instructions (e.g., a binary program compiled for the quantum computing system). In some implementations, a quantum computing system can perform quantum computation by storing and manipulating information within quantum states of a composite quantum system [wherein]. For example, qubits (i.e., quantum bits) can be stored in and represented by an effective two-level sub-manifold of a quantum coherent physical system [wherein]... In some implementations, the quantum states of the qubits are read out by measuring the transmitted or reflected signal from auxiliary quantum devices that are coupled to individual qubits. [0065] In some implementations, a quantum computing system can operate using gate-based models for quantum computing. For example, the qubits can be initialized in an initial state, and a quantum logic circuit comprised of a series of quantum logic gates can be applied to transform the qubits and extract measurements representing the output of the quantum computation. Individual qubits may be controlled by single-qubit quantum logic gates, and pairs of qubits may be controlled by two-qubit quantum logic gates (e.g., entangling gates that are capable of generating entanglement between the pair of qubits). In some implementations, a quantum computing system can operate using adiabatic or annealing models for quantum computing. For instance, the qubits can be initialized in an initial state, and the controlling Hamiltonian [wherein] can be transformed adiabatically by adjusting control parameters to another state that can be measured to obtain an output of the quantum computation. )
While Rig teaches the use of qubit quantum gates to measure patterns in state vector of a qubit and measuring state changes along with the classical information as noted above, one of ordinary skill in the art would understand that classical information includes modeling quantum states that include modeling/measuring qubit quantum-gate operations and a Bloch sphere is a geometrical representation of the space of pure states of a qubit.
Rig does not expressly teach the use of a Bloch sphere.
Kata expressly teaches the use of a Bloch sphere, in (in [0086] Certain implementations of quantum computers, referred as gate model quantum computers, comprise quantum gates. In contrast to classical gates, there is an infinite number of possible single-qubit quantum gates that change the state vector of a qubit. Changing the state of a qubit state vector typically is referred to as a single-qubit rotation, and may also be referred to herein as a state change or a single-qubit quantum-gate operation. A rotation, state change, or single-qubit quantum-gate operation may be represented mathematically by a unitary 2×2 matrix with complex elements. A rotation corresponds to a rotation of a qubit state within its Hilbert space [a Bloch sphere is built into an intermediate representation of a memory pattern within the main memory in such a way that associated same state vectors lΨ> are fully represented within the memory pattern alongside or along with the classical information |0> and |1>], which may be conceptualized as a rotation of the Bloch sphere [wherein a Bloch sphere is built into an intermediate representation of a memory pattern within the main memory in such a way that associated same state vectors lΨ> are fully represented within the memory pattern alongside or along with the classical information |0> and |1>]. (As is well-known to those having ordinary skill in the art, the Bloch sphere is a geometrical representation of the space of pure states of a qubit.) Multi-qubit gates alter the quantum state of a set of qubits [a Bloch sphere is built into an intermediate representation of a memory pattern within the main memory in such a way that associated same state vectors lΨ> are fully represented within the memory pattern alongside]. For example, two-qubit gates rotate the state of two qubits as a rotation in the four-dimensional Hilbert space of the two qubits. (As is well-known to those having ordinary skill in the art, a Hilbert space is an abstract vector space possessing the structure of an inner product that allows length and angle to be measured. Furthermore, Hilbert spaces are complete: there are enough limits in the space to allow the techniques of calculus to be used.) And in [0090] Some embodiments described herein generate, measure, or utilize quantum states that approximate a target quantum state [a Bloch sphere is built into an intermediate representation of a memory pattern within the main memory in such a way that associated same state vectors lΨ> are fully represented within the memory pattern alongside] (e.g., a ground state of a Hamiltonian). As will be appreciated by those trained in the art, there are many ways to quantify how well a first quantum state “approximates” a second quantum state. In the following description, any concept or definition of approximation known in the art may be used without departing from the scope hereof. For example, when the first and second quantum states are represented as first and second vectors [associated same state vectors lΨ> are fully represented within the memory pattern alongside or along with the classical information |0> and |1>], respectively, the first quantum state approximates the second quantum state when an inner product between the first and second vectors (called the “fidelity” between the two quantum states) is greater than a predefined amount (typically labeled ϵ) [associated same state vectors lΨ> are fully represented within the memory pattern alongside or along with the classical information |0> and |1>]. In this example, the fidelity quantifies how “close” or “similar” the first and second quantum states are to each other. The fidelity represents a probability that a measurement of the first quantum state will give the same result as if the measurement were performed on the second quantum state…
Examiner notes that the qbits are model as classical information states approximated quantum elements, for example, as depicted in Fig. 7
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And in [0083] Each qubit has an infinite number of different potential quantum-mechanical states. When the state of a qubit is physically measured, the measurement produces one of two different basis states resolved from the state of the qubit. Thus, a single qubit can represent a one, a zero, or any quantum superposition of those two qubit states [along with the classical information |0> and |1>]; a pair of qubits can be in any quantum superposition of 4 orthogonal basis states; and three qubits can be in any superposition of 8 orthogonal basis states. The function that defines the quantum-mechanical states of a qubit is known as its wavefunction. The wavefunction also specifies the probability distribution of outcomes for a given measurement…)
Kata, Yan and Rig are analogous art because both involve developing information retrieval and processing techniques in distributed computing environments.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the prior art of implementing a virtual quantum machine that models a quantum computer device, as disclosed by Kata with the method of developing information retrieval and processing computer system with quantum and classical compute resources provisionable to multiple users in distributed computing environments as collectively disclosed by Yan and Rig.
One of ordinary skill in the arts would have been motivated to combine the methods and systems disclosed by Kata, Yan and Rig, as noted above.; Doing so allows for developing and implementing a virtual quantum machine that models the quantum computer device in order to conduct benchmarking of quantum error correction tools, (Kata, Abstract).
Claims 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Rigetti et al. (US 20220084085, hereinafter ‘Rig’) in view of Yan et al. (US 20250199823, hereinafter ‘Yan’) in further view of Leipold et al. (US 20190392342, hereinafter ‘Le’ and Giurgica-Tiron et al. (US 20220164691, hereinafter ‘Tudor’).
Regarding claim 17, the rejection of claim 15 is incorporated and Rig in combination with Yan teaches the system of claim 15, wherein the meta protocol controller (880) is configured to: handle the meta information exchanged over the multi-protocol driver (MPD) and hold an Intermediate Representation (IR) for the information processing structures, such as quantum circuits. (in [0085] Hardware and software systems for virtualized quantum-classical computing are described as follows with reference to the figures [hold an Intermediate Representation (IR) for the information processing structures, such as quantum circuits)]. The system capabilities and core concepts that underpin the virtualization of quantum-classical compute systems and their provisioning to multiple simultaneous users are covered starting from the qubit level (for example, the quantum integrated circuit) [hold an Intermediate Representation (IR) for the information processing structures, such as quantum circuits] and including: the dynamical creation and definition of qubit plaquettes with specific performance attributes and characteristics; the hosting on a single QPU multiple user instances connected to those plaquettes and the provisioning of classical resources to support each such instance in a quantum classical architecture, as demanded by the specific job or user. And in [0122] FIG. 7 is a representation of an example virtualizable hybrid quantum-classical processor unit, and FIG. 8 is a representation of an example of two coherent virtualizable hybrid quantum-classical processor units. The processor units 700, 800 comprise: independent QPU cores 701, 801 where each box in the figure corresponds to a thread of execution for an array of N qubit(s); independent CPU cores 702, 802 where each box corresponds to a classical thread of execution (which may be processing an instance, doing minimum weight perfect matching, etc.); local Qache buses 703, 803 which are tightly coupled memory shared [wherein the meta protocol controller (880) is configured to: handle the meta information exchanged over the multi-protocol driver (MPD)] between all the QPU and CPU cores on their corresponding hybrid processing units (HPUs); processor-to-processor (system) Qache buses 804, 904 which enable coherency of the hybrid shared cache across multiple hybrid processing units; local Qache copies 705, 805, 905, which are cache copies local to a given hybrid processing unit that is managed by that hybrid processor's Quantum Memory Management Unit (QMMU) and holds coherent copies of all hybrid classical variables and state readout for the corresponding entire system; hybrid virtualization managers (hypervisors) [wherein the meta protocol controller (880) is configured to: handle the meta information exchanged over the multi-protocol driver (MPD)] 706, 806, 906 which load and manage jobs for execution, and part of managing these jobs includes configuring and maintaining the QMMU; Qache Virtualization Modules 707, 807, 907 where the QMMU maintains cache coherence between the local qache copy and the local qache copies of other hybrid processors on the system qache bus…; And in [0028] In some aspects of what is described here, monolithic quantum-classical hybrid computing resources may be dynamically partitioned and virtualized into multiple different and independently-saleable (as a resource to a user) parcels. These parcels may comprise configurations of qubits and qubit-qubit links on one or more quantum processor units for use by users for running computer programs. This virtualization may extend from the qubit level up through the control system, and including auxiliary classical infra/compute resources for demanding hybrid workloads and jobs. An order matching system can match a demand queue to a set of available dynamically provisioned quantum-classical resources, as part of a front-end system for a user to reserve, provision, and purchase credits for, or time on, hybrid quantum-classical resources of a certain desired performance level, and for systems for monitoring and metering the use of these resources to provide an account bill or usage statement. Furthermore, in some instances, each qubit control signal may be independently controlled by a thread of computation [wherein the meta protocol controller (880) is configured to: handle the meta information exchanged over the multi-protocol driver (MPD)], implemented by a CPU scheduling operations on the spooler. These threads are synchronized, either with explicit signals, or through deterministic timing. This makes it very natural to allocate a collection of control threads (i.e. those associated with a specific subset of qubits) to each user to natively support multi-tenancy of the hybrid quantum-classical computing resources.)
While Rig teaches the information processing stack for processing claimed information in a distributed/cloud computing environment. One of ordinary skill in art would understand that provisioned virtual machine/containers for processing information in a cloud computing environment include claimed elements as noted above.
Additionally Yan expressly teaches that provisioned virtual machine/containers for processing information in a cloud computing environment include claimed elements, in [0038] FIG. 4 illustrates generalized hardware and software components of a general-purpose computer system, such as a general-purpose computer system having an architecture similar to that shown in FIG. 1. The computer system 400 is often considered to include three fundamental layers: (1) a hardware layer or level 402; (2) an operating-system layer or level 404; and (3) an application-program layer or level 406. The hardware layer 402 includes one or more processors 408, system memory 410, various different types of input-output (“I/O”) devices 410 and 412, and mass-storage devices 414… The operating system includes many internal components and modules, including a scheduler 442, memory management 444, a file system 446, device drivers 448 [wherein the meta protocol controller (880) is configured to: handle the meta information exchanged over the multi-protocol driver (MPD)], and many other components and modules…
Le expressly teaches that provisioned virtual machine/containers for processing information in a cloud computing environment include claimed elements, in [0036] In some embodiments, the translated commands are sent to the kernel mode driver 230 via the input/output (I/O) driver 220. In one embodiment, an I/O control system call interface is used. Although a single driver, the input/output (I/O) driver 220, is shown, multiple drivers exist in a stack of drivers [wherein the meta protocol controller (880) is configured to: handle the meta information exchanged over the multi-protocol driver (MPD)] between the application 210 and a piece of hardware for processing a request targeted at the piece of hardware. In other embodiments, the translated commands are directly sent to the kernel mode driver 230. In various embodiments, the kernel mode driver 230 redirects I/O requests to the driver managing the target device object, such as file system driver 235 for a memory… [0038] The circuitry of the memory controller 242 in the hardware layer accesses the command group stored in the ring buffer 240. The command processor 244 uses interfaces to the memory controller 242 for accessing the commands stored on the ring buffer 240 [wherein the meta protocol controller (880) is configured to: handle the meta information exchanged over the multi-protocol driver (MPD)]. The command processor 244 schedules the retrieved commands based on a task type of the commands…
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Le, Yan and Rig for the same reasons disclosed above.
Additionally, Tudor teaches claimed hold an Intermediate Representation (IR) for the information processing structures, such as quantum circuits, in [0238] FIG. 14D is a flow chart that illustrates an example execution of a quantum routine on the computing system 1400. The classical computing system 1410 generates 1460 a quantum program to be executed or processed by the quantum computing system 1420. The quantum program may include instructions or subroutines to be performed by the quantum computing system 1420. In an example, the quantum program is a quantum circuit [hold an Intermediate Representation (IR) for the information processing structures, such as quantum circuits]. This program can be represented mathematically in a quantum programming language or intermediate representation such as QASM or Quil [hold an Intermediate Representation (IR) for the information processing structures, such as quantum circuits].
Tudor, Le, Yan and Rig are analogous art because both involve developing information retrieval and processing techniques using machine learning systems and algorithms.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of the prior art of retrieving and processing information using quantum Amplitude estimation algorithms, as disclosed by Le with the method of developing information retrieval and processing computer system with quantum and classical compute resources provisionable to multiple users in distributed computing environments as collectively disclosed by Le, Yan and Rig.
One of ordinary skill in the arts would have been motivated to combine the methods and systems disclosed by Tudor, Le, Yan and Rig, as noted above.; Doing so enable noisy intermediate scale quantum (NISQ) devices to perform amplitude estimation faster than amplitude estimation algorithms performed using a classical (non-quantum) computer, (Tudor, 0003).
Regarding claim 18, the rejection of claim 15 is incorporated and Rig in combination with Yan teaches the system of claim 15, wherein, when the system utilizes a gate-based quantum processor, (in[0102] The algorithm may be compiled (503) through a system programming interface (403). The compilation may include: a translation of an algorithm to a set of machine executable instructions, for instance a set of executable gates and readout operations; translation of an algorithm and/or instructions to another algorithm and/or instructions, for instance reducing the number of gate operations required to approximately implement a(( to optimize the algorithms efficiency [wherein, when the system utilizes a gate-based quantum processor, ]; providing information about potential plaquettes available to perform the algorithm, …. )
Additionally, Le teaches in [0140] A high level block diagram illustrating an example quantum processing unit in more detail is shown in FIG. 14. The quantum processing unit, generally referenced 280, comprises an irreversible classic computing core 286, clock and timing circuit 308, command pulse generator 294, quantum command pointer 284, data input unit 306, quantum computing core 296, quantum memory refresh unit 310, classic arithmetic logic unit (ALU) 290, [the arithmetic and logic unit (ALU) ] partial measurement unit 292, and operation completion detection unit 288. Quantum computing core 296 comprises quantum entanglement circuit 302, quantum error correction circuit 304, proximity state readout circuit 300, and quantum memory unit/ancillary state storage/quantum memory stabilization circuit 298.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the present application to combine the teachings of Le, Yan and Rig for the same reasons disclosed above.
Tudor teaches in [0033] Amplitude estimation also has applications which are not reducible to approximate counting, for example, where the goal is to estimate custom-character0|U|0custom-character for a general unitary operator U [when the system utilizes a gate-based quantum processor, ]. Some examples of this kind include applications of amplitude estimation to quantum linear algebra and machine learning [when the system utilizes a gate-based quantum processor, ]. For example, quantum procedures for estimating the inner product custom-characterx|ycustom-character between vectors x, y∈custom-character.sup.n may be useful for quantum classification and clustering algorithms. Amplitude estimation may be used to achieve quantum speedup for this inner product estimation. For example, amplitude estimation may use O(1/ϵ) samples as opposed to the O(1/ϵ.sup.2) samples, which is the number of samples used classically for estimating the inner product to error ϵ. Amplitude estimation variants may also be beneficial for reducing the condition number dependence K in the linear system solvers from O(κ.sup.2) to O(κ). This reduces the running time and also the depth of the linear system solver quantum circuit by a factor of κ, which in many cases is more than a 100×.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Low et al. (US 20210295194): teaches in [0034] Simulating quantum systems is one of the most promising applications of quantum computers. Generally speaking, the system is described by a Hamiltonian H, which is a Hermitian matrix. The goal then is to synthesize a quantum circuit that approximates the real time-evolution operator e.sup.−iHt, which is unitary, for some time t to some target error ϵ. To date, a number of very general quantum algorithms for this problem have risen to prominence, such as Lie-Trotter-Suzuki product formulas [1], sparse Hamiltonian simulation [2], linear-combination of unitaries [3], qubitization [4], and quantum signal processing [5]. The algorithm of choice largely depends on the structure of H… [0035] The block-encoding framework is a useful abstraction for designing quantum algorithms for linear algebra. Broadly speaking, the goal is to synthesize a unitary quantum circuit custom-character[H/α] that, in a matrix representation, encodes the Hamiltonian in the top-left block with some normalizing constant α≥∥H∥ like…
Georg Gesek (NPL: A Uniform Quantum Computing Model based on Virtual Quantum Processors): teaches that a virtual quantum processing unit (vQPU) is implemented as software code within a large main memory of a Turing machine/server bases computing enviornment and if the quantum processor is to be virtual, the gate matrices are constructed with classical information, state data, to be stored in a classical computing memory element.
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/OLUWATOSIN ALABI/Primary Examiner, Art Unit 2129
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