DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 65, 75, and 76 are rejected under 35 U.S.C. 102a1 as being anticipated by JP11163402A (hereafter JP’402, 11/28/23 IDS).
Regarding claim 1, JP’402 discloses a semiconductor device (FIG. 3), comprising:
a base substrate (1, FIG. 3, [0027]) comprising a main substrate;
a first light reflector (B1, FIG. 3, [0030]) located above the base substrate;
a first mask (M, FIG. 3, [0029]) located above the first light reflector;
a base semiconductor part (S1, FIG. 3, [0030]) located above the first mask;
a compound semiconductor part (S2-S4, FIG. 3, [0030]) located above the base semiconductor part; and
a second light reflector (B2, FIG. 3, [0054]) located above the compound semiconductor part and the first light reflector.
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Regarding claim 2, JP’402 discloses the first mask comprises a mask portion and an opening portion (FIG. 3).
Regarding claim 65, JP’402 discloses a first electrode (X, FIG. 3, [0027]) located above the compound semiconductor part; and a second electrode (Y, FIG. 3, [0027]) located above the first mask or below the main substrate, wherein in plan view, an area located between the first electrode and the second electrode does not overlap the opening portion (an area immediately adjacent to a left side of Y between the electrodes X/Y does not overlap with an opening between adjacent mask layers, FIG. 3).
Regarding claim 75, JP’402 discloses the first mask comprises the mask portion and the opening portion (FIG. 3), and the first light reflector comprises a plurality of pairs, each pair comprising a first refractive portion and a second refractive portion having a light refractive index larger than that of the first refractive portion ([0054]).
Regarding claim 76, JP’402 discloses the base semiconductor part is in contact with the upper surface of the first light reflector in the opening portion (S1 is in contact with an upper surface of B1 in the opening between adjacent mask layers, FIG. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 66-72, 74, 79, and 80 are rejected under 35 U.S.C. 103 as being unpatentable over JP’402 in view of Yamaguchi et al. (US PG Pub 2001/0032975 A1).
Regarding claim 66, JP’402 has disclosed the semiconductor device outlined in the rejection to claim 2 above and further discloses the base semiconductor part comprises a first portion (a portion of S1 between the adjacent mask layer M where dislocation line L lies, FIG .3) and a second portion (another portion of S1 above the mask layer M, FIG. 3) located on the mask portion and having a threading dislocation density except the second portion having a threading dislocation density of one fifth or less of that of the first portion. Yamaguchi discloses the base semiconductor part (106, FIG. 2, [0094]) comprises a first portion (116, FIG. 2, [0094]) and a second portion (104, FIG. 2, [0094]) located on the mask portion (103, FIG. 2, [0093]) and having a threading dislocation density of one fifth or less of that of the first portion (“the dislocation density of the high dislocation density region 116 is about 5.times.10.sup.12 m.sup.-2, and the dislocation density of the low dislocation density region 104 is about 2.times.10.sup.10 m.sup.-2,” [0098]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the first and second portions of JP’402 with the second portion having a threading dislocation density less than one fifth of that of the first portion as taught by Yamaguchi in order to prolong the life-time of the semiconductor device ([0006] and [0008] of Yamaguchi).
Regarding claim 67, JP’402 discloses a first electrode located above the compound semiconductor part and overlapping the second light reflector in plan view (FIG. 3).
Regarding claim 68, JP’402 discloses a second electrode located above the first mask or below the main substrate (FIG. 3).
Regarding claim 69, JP’402 discloses an insulating film (M2, FIG. 3, [0052]) located on the compound semiconductor part, wherein the insulating film comprises an aperture portion (an opening of M2, FIG. 3) overlapping the first electrode, the first light reflector, the second portion, and the second light reflector in plan view.
Regarding claim 70, JP’402 discloses the compound semiconductor part comprises a first type semiconductor layer (S2, FIG. 3, [0030]), an active layer (S3, FIG. 3, [0030]), and a second type semiconductor layer (S4, FIG. 3, [0030]) in this order.
Regarding claim 71, JP’402 discloses the second type semiconductor layer comprises an aperture portion (an opening of M2, FIG. 3) that overlaps the first light reflector, the second portion, and the second light reflector in plan view, and a high-resistance portion (M2, FIG. 3, [0052]) surrounding the aperture portion and having a current resistance higher than that of the aperture portion.
Regarding claim 72, JP’402 discloses the aperture portion overlaps none of the center of the mask portion in plan view (FIG. 3a).
Regarding claim 74, JP’402 discloses the second portion overlaps the first light reflector and the second light reflector in plan view (FIG. 3).
Regarding claim 79, JP’402 has disclosed the semiconductor device outlined in the rejection to claim 1 above except a base portion located between the main substrate and the first light reflector, and the base portion comprises a nitride semiconductor. Yamaguchi discloses a base portion (102, FIG. 2, [0093]) located between the main substrate (101, FIG. 2, [0094]) and the first light reflector (when modified the base portion will be inserted between 1 and B1 of JP’402), and the base portion comprises a nitride semiconductor ([0093]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor device of JP’402 with the base portion located between the main substrate and the first light reflector as taught by Yamaguchi in order to prolong the life-time of the semiconductor device ([0006] and [0008] of Yamaguchi).
Regarding claim 80, JP’402 discloses the second electrode is in contact with the upper surface of the first light reflector (Y is in electrical contact with the upper surface of B1, FIG. 3).
Claim 77 is rejected under 35 U.S.C. 103 as being unpatentable over JP’402 in view of Kidoguchi et al. (US PG Pub 2003/0143771 A1, 11/28/23 IDS).
Regarding claim 77, JP’402 has disclosed the semiconductor device outlined in the rejection to claim 75 above and further discloses the first light reflector is located on the base substrate (FIG. 3) except the base substrate comprises a recessed portion with its upper surface open. Kidoguchi discloses the base substrate (11/12, FIG. 1, [0126]) comprises a recessed portion (12c, FIG. 1, [0128]) with its upper surface open. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the base substrate of JP’402 with the recessed portion with its upper surface open as taught by Kidoguchi in order to reduce damage of the laminated body of the semiconductor device ([0156] of Kidoguchi).
Claims 81-82 are rejected under 35 U.S.C. 103 as being unpatentable over JP’402 in view of FUTAGAWA et al. (US PG Pub 2017/0201073 A1, 11/28/23 IDS).
Regarding claim 81, JP’402 has disclosed the semiconductor device outlined in the rejection to claim 69 above except the first electrode is a transparent electrode located between the compound semiconductor part and the second light reflector, the first electrode is in contact with the upper surface of the insulating film, and the first electrode is in contact with the compound semiconductor part in the aperture portion. FUTAGAWA discloses the first electrode is a transparent electrode (32, FIG. 1A, [0088]) located between the compound semiconductor part (20, FIG. 1A, [0087]) and the second light reflector (42, FIG. 1A, [0088]), the first electrode is in contact with the upper surface of the insulating film (34, FIG. 1A, where 32 is in contact with the upper surface of 34, FIG. 1A, [0100]), and the first electrode is in contact with the compound semiconductor part in the aperture portion (32 is in contact with 20 in 24A, FIG. 1A, [0100]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor device of JP’402 with inserting the transparent electrode between the compound semiconductor part and the second light reflector as taught by FUTAGAWA in order to reduce series resistance for the semiconductor device.
Regarding claim 82, JP’402 has disclosed the semiconductor device outlined in the rejection to claim 69 above except the second light reflector is provided in an island shape on the first electrode. FUTAGAWA discloses the second light reflector is provided in an island shape on the first electrode (42 is provided on 32 or 34 having an island shape, FIG. 1A, [0088]). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to have modified the semiconductor device of JP’402 with second light reflector being provided in an island shape on the first electrode as taught by FUTAGAWA in order to reduce series resistance for the semiconductor device.
Allowable Subject Matter
Claims 73 and 78 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
JP’200624713A (10/16/24 IDS) discloses a semiconductor device comprising a mask positioned above a substrate and various high and low threading dislocation density regions similar to the claimed invention (see FIG. 3).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YUANDA ZHANG whose telephone number is (571)270-1439. The examiner can normally be reached M-F 10:30 AM - 6:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MINSUN HARVEY can be reached at (571)272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/YUANDA ZHANG/Primary Examiner, Art Unit 2828
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