DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim(s) 1 – 8 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e. an abstract idea) without significantly more.
In step 1, of the 101 – analysis set forth in the MPEP 2106, the examiner has determined that the following limitations recite a process that, under the broadest reasonable interpretation, falls within one or more statutory categories (processes).
In step 2A prong 1, of the 101 – analysis set forth in MPEP 2106, the examiner has determined that the following limitations recite a process that, under broadest reasonable interpretation, recites abstract idea but for the recitation of generic computer components:
Regarding claim 1,
calculate a maximum execution time of the prediction model based on the first and second execution times
(i.e.: the broadest reasonable interpretation, the claim recites abstract idea: mathematical concept: It involves performing mathematical calculation using execution time values to derive a maximum execution time. See (MPEP 2106.04)).
evaluate the prediction model based on the maximum execution time
(i.e.: the broadest reasonable interpretation, the claim recites abstract idea: mental process: It involves assessing whether the prediction model satisfies a criterion based on the calculated maximum execution time. See (MPEP 2106.04)).
If the claim limitations, under their broadest reasonable interpretation, covers performance of the limitations as a mental process, but for the recitation of generic computer components, then it falls within the mental process. Accordingly, the claim recites an abstract idea.
Step 2A Prong 2 of the 101-analysis, set forth in MPEP 2106, the examiner has determined that
the following additional elements do not integrate this judicial exception into a practical application:
A prediction system comprising a CPU (Central Processing Unit) and a memory storing a program the CPU being configured to: execute a control operation for controlling a control target, generate a prediction model based on a tree learning algorithm,
(i.e.: deemed insufficient to transform the judicial exception to a patentable invention because the claim recites limitation which does not amount to more than a recitation of the words "apply it" (or an equivalent), such as mere instructions to implement an abstract idea on a computer. See MPEP 2106.05(f)).
acquire a predicted value by inputting, to the prediction model, a process value including one or more state values among state values that can be referenced by the CPU,
(i.e.: deemed insufficient to transform the judicial exception to a patentable invention because the claim recites limitation directed to mere data gathering as deemed insufficient to transform the judicial exception because claimed elements are considered insignificant extra-solution activity, See MPEP (2106.05(g))).
acquire each of first and second execution times that are times taken for outputting the predicted value in response to input of first and second data to the prediction model,
(i.e.: deemed insufficient to transform the judicial exception to a patentable invention because the claim recites limitation directed to mere data gathering as deemed insufficient to transform the judicial exception because claimed elements are considered insignificant extra-solution activity, See MPEP (2106.05(g))).
In Step 2B of the 101-analysis set forth in the 2019 PEG, the examiner has determined that the
claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception:
Regarding limitation (I), recite mere application of the abstract idea or mere instructions to implement an abstract idea on a computer are deemed insufficient to transform the judicial exception to a patentable invention because the limitations generally apply the use of a generic computer and/or process with the judicial exception, see MPEP 2106.05(f).
Regarding limitation (II and III), additional elements considered extra/post solution activity, as analyzed above, are activity that are well-understood routine and conventional, specifically: the courts have recognized the computer functions as well‐understood, routine, and conventional functions.
Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TL| Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network). See MPEP 2106.05(d)(II).
As analyzed above, the additional elements, analyzed above, do not integrate the noted judicial exception into a practical application because they do not impose any meaningful limits on practicing the abstract idea. Therefore, the claim is directed to an abstract idea.
Regarding claim 2, dependent upon claim 1, and fail to resolve the deficiencies identified above by integrating the judicial exception into a practical application, or introducing significantly more than the judicial exception. The claim recites:
wherein the CPU …
Deemed insufficient to transform the judicial exception to a patentable invention because the limitation is directed to mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea and are considered to adding the words “apply it” (or an equivalent) with the judicial exception, See MPEP 2106.05(f).
Limitations directed to using the computer as a tool for implementing an abstract idea cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B.
… is configure to calculate a unit execution time for a unit processing count based on a difference between the first and second execution times and a difference between a processing count for the first execution time and a processing count for the second execution time,
(i.e.: the broadest reasonable interpretation, the claim recites abstract idea: mathematical concept: It involves performing arithmetic operations on numeric values, including determining differences between execution times and processing counts and deriving a ratio based unit value. See (MPEP 2106.04)).
calculate the maximum execution time based on a maximum processing count and the unit execution time.
(i.e.: the broadest reasonable interpretation, the claim recites abstract idea: mathematical concept: It involves calculating a projected execution time value using relationships between maximum processing counts and unit execution time. See (MPEP 2106.04)).
Regarding claim 3, dependent upon claim 2, and fail to resolve the deficiencies identified above by integrating the judicial exception into a practical application, or introducing significantly more than the judicial exception. The claim recites:
wherein: the prediction model executes a plurality of prediction processes on input data, and
The recitation in the additional limitation simply links the judicial exception to a field of use and/or technology environment, see MPEP 2106.05(h).
Limitations directed to field of use cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B.
the CPU …
Deemed insufficient to transform the judicial exception to a patentable invention because the limitation is directed to mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea and are considered to adding the words “apply it” (or an equivalent) with the judicial exception, See MPEP 2106.05(f).
Limitations directed to using the computer as a tool for implementing an abstract idea cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B.
… is configured to calculate the processing counts for the first and second execution times based on a sum of respective processing counts of the plurality of prediction processes, and calculate the maximum processing count based on a sum of respective maximum processing counts of the plurality of prediction processes
(i.e.: the broadest reasonable interpretation, the claim recites abstract idea: mathematical concept: It involves aggregating and summing numerical processing count values associated with multiple prediction processes to derive total and maximum counts. See (MPEP 2106.04)).
Regarding claim 4, dependent upon claim 1, and fail to resolve the deficiencies identified above by integrating the judicial exception into a practical application, or introducing significantly more than the judicial exception. The claim recites:
wherein the tree learning algorithm comprises a decision tree learning algorithm generated using a random forest.
The recitation in the additional limitation simply links the judicial exception to a field of use and/or technology environment, see MPEP 2106.05(h).
Limitations directed to field of use cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B.
Regarding claim 5, dependent upon claim 1, and fail to resolve the deficiencies identified above by integrating the judicial exception into a practical application, or introducing significantly more than the judicial exception. The claim recites:
wherein the CPU …
Deemed insufficient to transform the judicial exception to a patentable invention because the limitation is directed to mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea and are considered to adding the words “apply it” (or an equivalent) with the judicial exception, See MPEP 2106.05(f).
Limitations directed to using the computer as a tool for implementing an abstract idea cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B.
… is configured to evaluate the prediction model based on a comparison between a predetermined control task period and the maximum execution time.
(i.e.: the broadest reasonable interpretation, the claim recites abstract idea: mental process: It involves comparing two values (a predetermined control task period and the maximum execution time) and making a determination whether a condition is satisfied by the prediction model. See (MPEP 2106.04)).
Regarding claim 6, dependent upon claim 1, and fail to resolve the deficiencies identified above by integrating the judicial exception into a practical application, or introducing significantly more than the judicial exception. The claim recites:
wherein the CPU …
Deemed insufficient to transform the judicial exception to a patentable invention because the limitation is directed to mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea and are considered to adding the words “apply it” (or an equivalent) with the judicial exception, See MPEP 2106.05(f).
Limitations directed to using the computer as a tool for implementing an abstract idea cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B.
… is configured to adjust a parameter of the prediction model,
(i.e.: the broadest reasonable interpretation, the claim recites abstract idea: mental process: It involves deciding how to modify a parameter based on evaluation result. See (MPEP 2106.04)).
wherein the CPU is configured to generate a plurality of the prediction models in accordance with the adjusted parameter, and each of the plurality of prediction models, and output an evaluation result of the evaluation of the plurality of prediction models.
The recitation in the additional limitation simply links the judicial exception to a field of use and/or technology environment, see MPEP 2106.05(h).
Limitations directed to field of use cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B.
Regarding claim 7,
The rest of the limitations recite similar subject matter as claim 1, so are rejected under the same rationale.
An information processing device connected to a control device, the control device including a first Central Processing Unit (CPU) and a first memory storing a first program, the first CPU configured to execute a control operation for controlling a control target
Deemed insufficient to transform the judicial exception to a patentable invention because the limitation is directed to mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea and are considered to adding the words “apply it” (or an equivalent) with the judicial exception, See MPEP 2106.05(f).
Limitations directed to using the computer as a tool for implementing an abstract idea cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B.
acquire a predicted value by inputting, to a prediction model, a process value including one or a plurality of state values among state values that can be referenced
The recitation in the additional limitation directed to mere data gathering as deemed insufficient to transform the judicial exception because claimed elements are considered insignificant extra-solution activity and well-understood routine and conventional (2106.05(d)).
Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TL| Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network). See MPEP 2106.05(d)(II).
The additional limitations as analyze failed to integrate a judicial exception into a practical application at Step 2A and provide an inventive concept in Step 2B, per the analysis above.
the information processing device including a second CPU and a second memory storing a second program, the second CPU configured to
Deemed insufficient to transform the judicial exception to a patentable invention because the limitation is directed to mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea and are considered to adding the words “apply it” (or an equivalent) with the judicial exception, See MPEP 2106.05(f).
Limitations directed to using the computer as a tool for implementing an abstract idea cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B.
Claim 8, recites similar subject matter as claim 7, so is rejected under the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 7 and 8 rejected under 35 U.S.C. 103 as being unpatentable over Chen et al., "Execution time prediction for energy-efficient hardware accelerators" in view of Remis et al., Pub. No.: US20190325292A1 and Sharma et al., Pub. No.: US20130268469A1.
Regarding claim 1, Chen teaches: A prediction system comprising a CPU (Central Processing Unit) and a memory storing a program, the CPU being configured to:
(Chen, page: 458, “2.1 System Setup The system we consider in this paper consists of processor cores, caches, main memory, and hardware accelerators [A prediction system comprising a CPU (Central Processing Unit) and a memory storing a program, the CPU]. The cores and accelerators are loosely coupled. The accelerators access memory through DMA instead of going through the processor’s cache.”)
execute a control operation for controlling a control target,
(Chen, page: 458, “In this paper, we present a predictive approach to control the DVFS levels of hardware accelerators at fine granularity [execute a control operation for controlling a control target], exploiting input-dependent variations.”)
calculate a maximum execution time of the prediction model based on the first and second execution times and evaluate the prediction model based on the maximum execution time.
(Chen, page: 459, “Table-based: Some hardware accelerators, including the Multi-Format Codec (MFC) in Samsung Exynos Series SoCs, use a lookup table to determine the DVFS level [20]. The table is addressed by a coarse-grained parameter, such as the resolution of a video. Before decoding a video, the driver will look into the table and set a DVFS level for the entire video sequence. People have also studied using the type of frames as inputs to the table [21]. However, these approaches do not take into account fine-grained job-to-job execution time variations. Essentially, these approaches set DVFS levels to the worst case for that coarse-grained parameter used to index the table [calculate a maximum execution time of the prediction model based on the first and second execution times] (i.e.: determining DVFS settings according to worst-case (maximum execution time) for jobs associated with a coarse-grained parameter). As can be seen in Figure 2, though all jobs have the same coarse-grained parameter (resolution in this case), most jobs have much shorter execution time than the worst-case [evaluate the prediction model based on the maximum execution time] (i.e.: evaluating whether the predication or control approach appropriately balances timing and energy efficiency). Thus the coarse-grained approach misses opportunities for energy reduction.”)
Chen does not teach:
generate a prediction model
acquire a predicted value by inputting, to the prediction model, a process value including one or more state values among state values that can be referenced by the CPU,
acquire each of first and second execution times that are times taken for outputting the predicted value in response to input of first and second data to the prediction model,
… based on a tree learning algorithm,
Remis teaches:
generate a prediction model
(Remis, “[0029] In general, implementing a ML/AI system involves two phases, a learning/training phase and an inference phase. In the learning/training phase, a training algorithm or procedure is used to train a model [generate a prediction model] to operate in accordance with patterns and/or associations based on, for example, training data.”)
acquire a predicted value by inputting, to the prediction model,
(Remis, “[0100] … For example, the model trainer 212 determines, analyzes or compares (e.g., via a comparator) the first execution time and the second execution time to determine the query engine that resulted in the fastest execution time. In this manner, the model trainer 212 establishes a ground truth (e.g., the binary output (y) noted above) for comparing to the predicted result of the LSTM model [acquire a predicted value by inputting, to the prediction model,]. The model trainer 212 annotates the past query with the result of the query engine executed the past query in the fastest amount of time (block 620).”)
a process value including one or more state values among state values that can be referenced by the CPU,
(Remis, “[0054] The context determiner 218 retrieves, receives, obtains, determines and/or otherwise contains context information (Ct) (e.g. parameters) associated with a current state of the query selection system 100 and/or the hybrid database 102 [a process value including one or more state values among state values that can be referenced by the CPU]. In turn, the context determiner 218 communicates the context information to the model classifier 210 and the model classifier 210 receives the context information (Ct) as an input value. Some examples of the context information (Ct) include, but are not limited to, engine load, graph analytics, system load, cache, and/or any other parameter(s) that can impact performance of a query…”)
acquire each of first and second execution times that are times taken for outputting the predicted value in response to input of first and second data to the prediction model,
(Remis, “[0100] After the past query is executed on the graph database 104 and the relational database 106, the model trainer 212 compares (e.g., via a comparator) the first execution time and the second execution time (block 616) and determines the query engine that resulted in the fastest execution time (block 618). For example, the model trainer 212 determines, analyzes or compares (e.g., via a comparator) the first execution time and the second execution time to determine the query engine that resulted in the fastest execution time [acquire each of first and second execution times that are times taken for outputting the predicted value in response to input of first and second data to the prediction model]. In this manner, the model trainer 212 establishes a ground truth (e.g., the binary output (y) noted above) for comparing to the predicted result of the LSTM model. The model trainer 212 annotates the past query with the result of the query engine executed the past query in the fastest amount of time (block 620).”)
Remis and Chen are related to the same field of endeavor (i.e.: machine learning methods). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teaching of Remis with teachings of Chen to compare different processing or execution options, determine which one performs fastest and use these results to train a model that improves further prediction and performance optimalization (Remis, ¶[0098] – [0101]).
Chen in view of Remis do not teach:
… based on a tree learning algorithm,
Sharma teaches:
based on a tree learning algorithm,
(Sharma, “[0025] The model iteration sub-module 203 can use a decision tree-based predictive learning technique [based on a tree learning algorithm,] and the input variables to build a prediction model...”)
Sharma, Chen and Remis are related to the same field of endeavor (i.e.: machine learning methods). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teaching of Sharma with teachings of Chen and Remis to add tree based prediction and variable ranking capability to identify key input variables affecting execution-time prediction and performance. (Sharma, Abstract).
Regarding claim 4, Chen in view of Remis and Sharma teach the method of claim 1.
Sharma further teaches: The prediction system according to claim 1, wherein the tree learning algorithm comprises a decision tree learning algorithm generated using a random forest.
(Sharma, “[0033] At block 303, processing logic creates a decision tree-based prediction model using the input variables. Examples of a prediction model can include, and are not limited to, a yield prediction model, a preventative maintenance prediction model, a metrology prediction model, a defect prediction model, etc. Processing logic can build a prediction model using decision trees. In one embodiment, processing logic uses a Rules Ensemble algorithm and decision trees to create the prediction model. In another embodiment, processing logic uses a Random Forest algorithm [wherein the tree learning algorithm comprises a decision tree learning algorithm generated using a random forest] and decision trees to create the prediction model.”)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the present application to combine the teachings of Sharma with teachings of Chen and Remis for the same reasons disclosed for claim 1.
Regarding claim 7, Chen teaches: An information processing device connected to a control device, the control device including a first Central Processing Unit (CPU) and a first memory storing a first program,
(Chen, page: 458, “2.1 System Setup The system we consider in this paper consists of processor cores, caches, main memory, and hardware accelerators [An information processing device connected to a control device, the control device including a first Central Processing Unit (CPU) and a first memory storing a first program]. The cores and accelerators are loosely coupled. The accelerators access memory through DMA instead of going through the processor’s cache.”)
the first CPU configured to execute a control operation for controlling a control target, and
(Chen, page: 458, “In this paper, we present a predictive approach to control the DVFS levels of hardware accelerators at fine granularity [execute a control operation for controlling a control target], exploiting input-dependent variations.”)
Chen does not teach:
acquire a predicted value by inputting, to a prediction model, a process value including one or a plurality of state values among state values that can be referenced,
the information processing device including a second CPU and a second memory storing a second program, the second CPU configured to
generate the prediction model based on a tree learning algorithm,
Remis teaches:
acquire a predicted value by inputting, to a prediction model,
(Remis, “[0100] … For example, the model trainer 212 determines, analyzes or compares (e.g., via a comparator) the first execution time and the second execution time to determine the query engine that resulted in the fastest execution time. In this manner, the model trainer 212 establishes a ground truth (e.g., the binary output (y) noted above) for comparing to the predicted result of the LSTM model [acquire a predicted value by inputting, to a prediction model,]. The model trainer 212 annotates the past query with the result of the query engine executed the past query in the fastest amount of time (block 620).”)
a process value including one or a plurality of state values among state values that can be referenced,
(Remis, “[0054] The context determiner 218 retrieves, receives, obtains, determines and/or otherwise contains context information (Ct) (e.g. parameters) associated with a current state of the query selection system 100 and/or the hybrid database 102 [a process value including one or a plurality of state values among state values that can be referenced]. In turn, the context determiner 218 communicates the context information to the model classifier 210 and the model classifier 210 receives the context information (Ct) as an input value. Some examples of the context information (Ct) include, but are not limited to, engine load, graph analytics, system load, cache, and/or any other parameter(s) that can impact performance of a query…”)
the information processing device including a second CPU and
(Remis, “[0078] … the example object and property analyzer 304, the example table populator 306 and/or, more generally, the example query selection system 100 of FIGS. 1-3 could be implemented by one or more analog or digital circuit(s), logic circuits, programmable processor(s) [the information processing device including a second CPU], programmable controller(s), graphics processing unit(s) (GPU(s)), digital signal processor(s) (DSP(s)), application specific integrated circuit(s) (ASIC(s)), programmable logic device(s) (PLD(s)) and/or field programmable logic device(s) (FPLD(s))…”)
a second memory storing a second program, the second CPU configured to
(Remis, “[0111] The processor 1012 of the illustrated example includes a local memory 1013 (e.g., a cache). The processor 1012 of the illustrated example is in communication with a main memory including a volatile memory 1014 and a non-volatile memory 1016 via a bus 1018 [a second memory storing a second program, the second CPU configured to].”)
Remis and Chen are related to the same field of endeavor (i.e.: machine learning methods). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teaching of Remis with teachings of Chen to compare different processing or execution options, determine which one performs fastest and use these results to train a model that improves further prediction and performance optimalization (Remis, ¶[0098] – [0101]).
Chen in view of Remis do not teach:
generate the prediction model based on a tree learning algorithm,
Sharma teaches:
generate the prediction model based on a tree learning algorithm,
(Sharma, “[0025] The model iteration sub-module 203 can use a decision tree-based predictive learning technique [generate the prediction model based on a tree learning algorithm,] and the input variables to build a prediction model...”)
Sharma, Chen and Remis are related to the same field of endeavor (i.e.: machine learning methods). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teaching of Sharma with teachings of Chen and Remis to add tree based prediction and variable ranking capability to identify key input variables affecting execution-time prediction and performance. (Sharma, Abstract).
Claim 8, recites limitations analogous to claim 7, so is rejected under the same rationale.
Claim(s) 2 – 3 rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Remis, Sharma and in further view of Floyd et al., Pub. No.: US20220100572A1.
14. Regarding claim 2, Chen in view of Remis and Sharma teach the method of claim 1.
Chen in view of Remis and Sharma do not teach:
wherein the CPU is configured to calculate a unit execution time for a unit processing count based on a difference between the first and second execution times and a difference between a processing count for the first execution time and a processing count for the second execution time, and calculate the maximum execution time based on a maximum processing count and the unit execution time.
Floyd teaches:
wherein the CPU is configured to calculate a unit execution time for a unit processing count based on a difference between the first and second execution times and a difference between a processing count for the first execution time and a processing count for the second execution time
(Floyd, “[0021] … The processor device next determines a maximum execution time interval for the second process based on the maximum cycle time interval and the fixed execution time interval [calculate a unit execution time for a unit processing count based on a difference between the first and second execution times]. For instance, the maximum execution time interval may be calculated as a difference between the maximum cycle time interval and the amount of time taken to execute the first process, a difference between the maximum cycle time interval and a moving average of first process execution times, a difference between the maximum cycle time interval and a configured execution time of the first process, or a difference between the maximum cycle time interval [a difference between a processing count for the first execution time and a processing count for the second execution time] and a predicted execution time of the first process generated by an ML model, as non-limiting examples.”)
calculate the maximum execution time based on a maximum processing count and the unit execution time.
(Floyd, “[0027] … According to some examples, the maximum execution time interval 28 may be calculated as a difference between the maximum cycle time interval 22 and a configured execution time 34 of the first process [calculate the maximum execution time based on a maximum processing count and the unit execution time], or as a difference between the maximum cycle time interval 22 and a predicted execution time 36 of the first process generated by an ML model 38.”)
Floyd, Chen, Remis and Sharma are related to the same field of endeavor (i.e.: machine learning methods). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teaching of Floyd with teachings of Chen, Remis and Sharma to manage multiple processes with different delay sensitivities by dynamically adjusting execution time based on timing constraints to improve real time performance and resource efficiency. (Floyd, Abstract).
Regarding claim 3, Chen in view of Remis, Sharma and Floyd teach the method of claim 2.
Chen further teaches: wherein: the prediction model executes a plurality of prediction processes on input data, and
(Chen, page: 462, “3.4 Prediction Model After obtaining the features and execution time for each job, we develop a model that takes feature values and maps them to execution time. The model is then trained using the feature values and execution time data from training runs [wherein: the prediction model executes a plurality of prediction processes on input data].”)
Floyd further teaches: the CPU is configured to calculate the processing counts for the first and second execution times based on a sum of respective processing counts of the plurality of prediction processes, and
(Floyd, “[0025] … Each iteration of the processing workload 16 is associated with a maximum cycle time interval 22 during which the iteration is executed, and which may vary between iterations of the processing workload 16. Additionally, the first process 18 is associated with a fixed execution time interval 24, while the second process 20 is associated with an adjustable execution time interval 26 [the CPU is configured to calculate the processing counts for the first and second execution times]. Because both the first process 18 and the second process 20 are executed within each iteration of the processing workload 16, the sum of the fixed execution time interval 24 and the adjustable execution time interval 26 must be less than or equal to the maximum cycle time interval 22 [based on a sum of respective processing counts of the plurality of prediction processes,]…”)
calculate the maximum processing count based on a sum of respective maximum processing counts of the plurality of prediction processes.
(Floyd, “[0031] It is to be understood that, while the processing workload 16 of FIG. 1 is shown as comprising a single fixed-execution-time process 18 and a single adjustable-execution-time process 20, the operations described above with respect to FIG. 1 are equally applicable to embodiments in which a processing workload includes multiple fixed-execution-time processes and/or multiple adjustable-execution-time processes. In such embodiments, the maximum cycle time interval would be determined as a sum of the fixed execution time interval(s) for the multiple fixed-execution-time process(es) [calculate the maximum processing count based on a sum of respective maximum processing counts of the plurality of prediction processes] and the adjustable execution time interval(s) for the multiple adjustable-execution-time process(es)…”)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the present application to combine the teachings of Floyd with teachings of Chen, Remis and Sharma for the same reasons disclosed for claim 1.
Claim 5 rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Remis, Sharma and in further view of STATTELMANN et al., Pub. No.: US20150286203A1.
14. Regarding claim 5, Chen in view of Remis and Sharma teach the method of claim 1.
Chen in view of Remis and Sharma do not teach:
wherein the CPU is configured to evaluate the prediction model based on a comparison between a predetermined control task period and the maximum execution time.
STATTELMANN teaches:
wherein the CPU is configured to evaluate the prediction model based on a comparison between a predetermined control task period and the maximum execution time.
(STATTELMANN, “[0020] An exemplary system for an optimized operation of real time control applications or systems in and industrial automation is disclosed [between a predetermined control task period], comprising: at least one data processing unit; at least one database for storing at least execution time information; and at least one interface for the input of data, wherein the at least one processing unit is configured with program code to include: … … wherein the training applications are decomposed into smaller code pieces which are searched for recurring code sequences; and a comparison unit that compares model predictions and measurements [wherein the CPU is configured to evaluate the prediction model based on a comparison], wherein depending on a comparison result the refinement unit is configured to further refine the initial timing data structure, and wherein comparison and refinement are performed on a cyclic basis as long as a desired accuracy is achieved and a final CPU timing model or data structure is determined and created, and an analyzing unit that decomposes the structure of a control application into code sequences for which the created timing data structure provides an execution time estimate, determines an estimate for at least one of the best-case execution time and the worst-case execution time of the control application [and the maximum execution time], and reports at least one of the best-case execution time and the worst-case execution time.”)
STATTELMANN, Chen, Remis and Sharma are related to the same field of endeavor (i.e.: machine learning methods). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teaching of STATTELMANN with teachings of Chen, Remis and Sharma to estimate best and worst case execution time and improve prediction accuracy for real time tasks and timing aware performance management. (STATTELMANN, Abstract).
Claim 6 rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Remis, Sharma and in further view of Lim et al., Pub. No.: US20210174229A1.
14. Regarding claim 6, Chen in view of Remis and Sharma teach the method of claim 1.
Chen in view of Remis and Sharma do not teach:
wherein the CPU is configured to adjust a parameter of the prediction model, wherein the CPU is configured to generate a plurality of the prediction models in accordance with the adjusted parameter, and each of the plurality of prediction models, and output an evaluation result of the evaluation of the plurality of prediction models
Lim teaches:
wherein the CPU is configured to adjust a parameter of the prediction model, wherein the CPU is configured to generate a plurality of the prediction models in accordance with the adjusted parameter, and each of the plurality of prediction models, and output an evaluation result of the evaluation of the plurality of prediction models.
(Lim, “[0057] The learner 320 may generate and adjust the parameter group of the prediction model 33 by analyzing the ensemble learning data 32. The parameter group may be a set of all parameters included in the artificial neural network structure or the neural network of the prediction model 33. The learner 320 may generate the ensemble result by analyzing the ensemble learning data 32 [wherein the CPU is configured to generate a plurality of the prediction models in accordance with the adjusted parameter]. The learner 320 may adjust the parameter group of the prediction model 33 [wherein the CPU is configured to adjust a parameter of the prediction model] such that the generated ensemble result has the expected comparison result (or such that the generated ensemble result is within a reference error from the comparison result). The comparison result may be an actual measurement value of the prediction time, and may be preset for the ensemble prediction device 300 [and each of the plurality of prediction models, and output an evaluation result of the evaluation of the plurality of prediction models]. The adjusted parameter group may be reflected to the prediction model 33 to be managed by the ensemble prediction device 300.”)
Lim, Chen, Remis and Sharma are related to the same field of endeavor (i.e.: machine learning methods). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teaching of Lim with teachings of Chen, Remis and Sharma to combine multiple prediction results, evaluate prediction errors and dynamically adjust model parameters and weights to improve execution time prediction accuracy. (Lim, Abstract).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kobayashi et al., Pub. No.: US20170061329A1.
Kobayashi teaches a machine learning management device calculates, based on execution results of the plurality of machine learning algorithms, increase rates of prediction performances of a plurality of models generated by the plurality of machine learning algorithms.
Lo et al., Pub. No.: US10949260B2.
Lo teaches a device using prediction-guided resource allocation technologies for software applications, comprising generating a plurality of program features that impact execution time of a plurality of program tasks; predicting execution time of the plurality of program tasks on one or more computing cores using the plurality of program features.
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/M.T.M./Examiner, Art Unit 2148
/MICHELLE T BECHTOLD/Supervisory Patent Examiner, Art Unit 2148
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