Prosecution Insights
Last updated: April 19, 2026
Application No. 18/565,050

NODE MATCHING METHOD AND APPARATUS, DEVICE, AND MEDIUM

Non-Final OA §103
Filed
Nov 28, 2023
Examiner
POPE, KHARYE
Art Unit
2693
Tech Center
2600 — Communications
Assignee
Suzhou MetaBrain Intelligent Technology Co., Ltd.
OA Round
1 (Non-Final)
64%
Grant Probability
Moderate
1-2
OA Rounds
3y 3m
To Grant
87%
With Interview

Examiner Intelligence

Grants 64% of resolved cases
64%
Career Allow Rate
341 granted / 529 resolved
+2.5% vs TC avg
Strong +22% interview lift
Without
With
+22.1%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
32 currently pending
Career history
561
Total Applications
across all art units

Statute-Specific Performance

§101
3.4%
-36.6% vs TC avg
§103
63.5%
+23.5% vs TC avg
§102
17.7%
-22.3% vs TC avg
§112
10.0%
-30.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 529 resolved cases

Office Action

§103
DETAILED ACTION Response to Amendment This is in response to Applicants Preliminary Amendment filed 11/28/2023 which has been entered. Claims 13 and 14 have been amended. Claims 11 and 12 have been cancelled. No Claims 15-22 have been added. Claims 1-10 and 13-22 are still pending in this application, with Claims 1, 13 and 14 being independent. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 3-7, 13-18 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over WU (CN 109510786 A) in view of ZHOU et al (CN 1592445 A). As per Claim 1, Wu teaches a node matching method, applied to a target node in a multi-stage switching network, the target node comprising a plurality of allowed input ports and a plurality of allowed output ports, the node matching method comprising: acquiring real-time state parameters of the plurality of allowed input ports and the plurality of allowed output ports of the target node; wherein the real-time state parameters comprise: state information indicating whether each of the allowed input ports and each of the allowed output ports are idle (Figures 1-3; Paragraphs [0023] – [0068] and [0107]). (Note: Wu describes routing control for a three-stage Clos network [being applied to a target node in a multistage switching network] Step S101 obtains the input ports. S102 and S103 determines whether the output port of the input port and ascertains whether the output port is idle [i.e. available]. Wu described the use of lookup tables to record input ports and output ports which record current port state [i.e. active or idle] and based on current state make a determination as to port availability) (Note: In paragraph [0068], Wu indicates the routing method may be implemented in a switching device and that device may include a memory, a processor, instructions stored on the memory and a program executed by a processor to perform the routing method. In paragraph [0107], Wu describes a software product as among other things software stored in a computer readable medium) Wu does not teach a dynamic priority serial number of each allowed input port among all the allowed input ports, and a dynamic priority serial number of each allowed output port among all the allowed output ports. However, Zhou teaches a dynamic priority serial number of each allowed input port among all the allowed input ports, and a dynamic priority serial number of each allowed output port among all the allowed output ports (Figure 3). (Note: In describing an optimal addressing selection method illustrated in Figure 3; Zhou describes searching all interfaces [i.e. input/output ports to identifying a device [i.e. node] and all of the interfaces of set A. Zhou then describes removing all virtual and non-available interfaces [i.e. ports] from the original set A to obtain a revised set which will be referred to as A prime [i.e. A’] which consists of all available input and output ports. Zhou indicates that the priority associated with the respective ports is determined to select optimal port pairings [input/output ports matching]) The combination of Wu and Zhou teaches determining serial numbers of all the allowed input ports in an idle state and serial numbers of all the allowed output ports in an idle state according to the real-time state parameters and a preset calculation rule; matching the allowed input ports with the allowed output ports, which have corresponding serial numbers, to obtain a matching relationship; and performing data transmission according to the matching relationship. (Note: A serial number is merely an identifier. The use of lookup tables to record input ports and output ports inherent teach the use of an identifier to identify the respective port. The concept of prioritized ports is described by Zhou as described above. The matching of input ports to output ports is taught as described above; and the transmission of data is taught as described in the Abstract of Wu utilizing the identified optimized input/output pair) It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Wu with the method taught by Zhou to provide multiple, equal-cost paths between input and output ports which prevent network bottlenecks, thereby ensuring that a failure of a single switch or link does not significantly degrade performance. As per Claim 3, the combination of Wu and Zhou teaches wherein after matching the allowed input ports with the allowed output ports, which have corresponding serial numbers, to obtain matching relationships, the method further comprises: performing locked grant on the allowed input ports and the allowed output ports corresponding to the matching relationship. (Note: The purpose of performing locked grant is to ensure that matching relationships are not disconnected until that data which is intended to be transmitted is complete. It is found to be obvious to maintain this relationship as it would be disadvantageous to suspend the relationship between ports during the transmission of data) It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Wu with the method taught by Zhou to provide multiple, equal-cost paths between input and output ports which prevent network bottlenecks, thereby ensuring that a failure of a single switch or link does not significantly degrade performance. As per Claim 4, the combination of Wu and Zhou teaches wherein the method further comprises: updating the real-time state parameters according to the matching relationship. (Note: As communications are dynamic it is impractical to establish a relationship and assume it will be optimal in every situation) It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Wu with the method taught by Zhou to provide multiple, equal-cost paths between input and output ports which prevent network bottlenecks, thereby ensuring that a failure of a single switch or link does not significantly degrade performance. As per Claim 5, the combination of Wu and Zhou teaches wherein the multi-stage switching network is a three-stage switching network, and the target node is an input node (Wu: Paragraph [0104]). (Note: Figure 4 of Wu is an illustration of a Clos network [i.e. three-stage switching network]) It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Wu with the method taught by Zhou to provide multiple, equal-cost paths between input and output ports which prevent network bottlenecks, thereby ensuring that a failure of a single switch or link does not significantly degrade performance. As per Claim 6, the combination of Wu and Zhou teaches wherein the dynamic priority serial number of each allowed input port is the priority of the allowed input port among all the allowed input ports, and is globally visible; and the dynamic priority serial number of each allowed output port is the priority of the allowed output port among all the allowed output ports, and is globally visible as described in Claim 1. (Note: The term globally visible is mentioned in the specification but no additional detail is provided beyond it being mentioned. The fact that the identifier is not hidden by the fact it is included in the lookup tables described above is found to read on the claimed language) It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Wu with the method taught by Zhou to provide multiple, equal-cost paths between input and output ports which prevent network bottlenecks, thereby ensuring that a failure of a single switch or link does not significantly degrade performance. As per Claim 7, the combination of Wu and Zhou teaches a node matching apparatus as described in Claim 1. It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method and apparatus taught by Wu with the method and apparatus taught by Zhou to provide multiple, equal-cost paths between input and output ports which prevent network bottlenecks, thereby ensuring that a failure of a single switch or link does not significantly degrade performance. As per Claims 13 and 14, the combination of Wu and Zhou teaches a computer device; and non-transitory computer-readable storage medium executed by a processor as described in Claim 1. It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method, apparatus and non-transitory computer-readable storage medium taught by Wu with the method and apparatus taught by Zhou to provide multiple, equal-cost paths between input and output ports which prevent network bottlenecks, thereby ensuring that a failure of a single switch or link does not significantly degrade performance. As per Claim 15, the combination of Wu and Zhou teaches wherein the state information of each port comprises an idle state or a busy state as described in Claim 1. It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Wu with the method taught by Zhou to provide multiple, equal-cost paths between input and output ports which prevent network bottlenecks, thereby ensuring that a failure of a single switch or link does not significantly degrade performance. As per Claim 16, the combination of Wu and Zhou teaches wherein the dynamic priority serial number of each port refers to the priority of the port among all ports at the same side. (Note: In Claim 1 the Wu describes the establishment of a lookup table containing input ports and output ports. On one side of the table are input ports and the other side of the table are the output ports [i.e. set A]. This table is processed to remove all unavailable ports to produce a revised lookup table [i.e. set A’]. Modifying the revised lookup table to incorporate the optimized prioritization described by Zhou is found to read on the claimed language) It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Wu with the method taught by Zhou to provide multiple, equal-cost paths between input and output ports which prevent network bottlenecks, thereby ensuring that a failure of a single switch or link does not significantly degrade performance. As per Claim 17, the combination of Wu and Zhou teaches configuring and adjusting the priority of each port on the target node according to actual requirements as described in Claim 1. It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Wu with the method taught by Zhou to provide multiple, equal-cost paths between input and output ports which prevent network bottlenecks, thereby ensuring that a failure of a single switch or link does not significantly degrade performance. As per Claim 18 the combination of Wu and Zhou teaches ranking all idle ports according to the dynamic priority serial numbers (Note: the optimization by priority described by Zhou is found to read on the recitation) It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Wu with the method taught by Zhou to provide multiple, equal-cost paths between input and output ports which prevent network bottlenecks, thereby ensuring that a failure of a single switch or link does not significantly degrade performance. As per Claim 22, the combination of Wu and Zhou teaches wherein once the matching relationships are determined, the matching relationships is not disconnected until whole frame data is sent completely as described above. It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the method taught by Wu with the method taught by Zhou to provide multiple, equal-cost paths between input and output ports which prevent network bottlenecks, thereby ensuring that a failure of a single switch or link does not significantly degrade performance. Claims 8, 10 and 19-21 are rejected due to their dependency on a rejected base Claim. Claim(s) 9 is rejected under 35 U.S.C. 103 as being unpatentable over WU (CN 109510786 A) in view of ZHOU et al (CN 1592445 A) as applied to Claim 7 above, and further in view of Sindhu et al (2010/0061241 A1). As per Claim 9, the combination of Wu and Zhou teaches the node matching apparatus according to Claim 7; but does not teach an output buffer module connected to the transmission module. However, Sindhu teaches an output buffer module connected to the transmission module (Figure 15; Page 13, Paragraphs [0125] – [0130]). It would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the apparatus taught by Wu and Zhou with the apparatus taught by Sindhu to leverage output buffers as a form of temporary storage during bursts of network traffic which prevents packet loss and thereby combating signal degradation while ensuring smooth transmission and reducing the need for packet retransmission. Allowable Subject Matter Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zievers (2012/0284379 A1), Musacchino et al (2008/0212472 A1), Aybay (8,724,628 B1), Aybay (8,724,479 B1), LEA (2013/0083793 A1). Each of these describes systems and methods of routing communication in packet switched systems. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHARYE POPE whose telephone number is (571)270-5587. The examiner can normally be reached Monday - Friday 8AM - 4PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ahmad Matar can be reached at 571-272-7488. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. KHARYE POPE Primary Examiner Art Unit 2693 /KHARYE POPE/Primary Examiner, Art Unit 2693
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Prosecution Timeline

Nov 28, 2023
Application Filed
Feb 02, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
64%
Grant Probability
87%
With Interview (+22.1%)
3y 3m
Median Time to Grant
Low
PTA Risk
Based on 529 resolved cases by this examiner. Grant probability derived from career allow rate.

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