Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Notice for all Patent Application as subject to AIA
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
Claims 1-15 are presented for examination.
Claim Rejections - 35 USC § 102(a)(1)/102(a)(2)
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6 and 12-14 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by QI et al (U.S. Patent Application Publication No. 2022/0342065 A1).
QI’s patent application meets all the limitations for claims 1-6 and 12-14 recited in the claimed invention.
As to claim 1, QI et al disclose a computing apparatus configured to perform a convolution operation, wherein the computing apparatus comprises a master processing circuit and a plurality of slave processing circuits (figures 1-2, pars. 0010 & 0025), wherein the master processing circuit is configured to: broadcast at least one feature map block of an input feature map to a plurality of scheduled slave processing circuits during the convolution operation (figurers 1-2, pars. 0013-0016 & 0019-0020, providing feature map as an input for convolution process), wherein the feature map block is obtained by dividing the input feature map into blocks according to a lowest storage dimension (figures 1-2, pars. 0021-0025 & 0055-0058 & 0068-0074, dividing input data according input dimension); and each scheduled slave processing circuit is configured to: perform the convolution operation on the feature map block and a corresponding weight block, wherein the weight block is obtained by dividing a weight into blocks according to an output channel dimension; and return an operation result to the master processing circuit (figure 1, pars. 0075-0083, performing the convolution process according input dimension and outputting process result).
As to claims 2-4, QI et al disclose that the master processing circuit is further configured to: divide the input feature map into blocks according to the lowest storage dimension during the convolution operation; and align the feature map block to a first alignment requirement in the lowest storage dimension when broadcasting the feature map block, wherein the first alignment requirement is determined according to a processing capacity of the slave processing circuit (figures 1-2, pars. 0013-0022 & 0072-0083, providing feature map as an input for convolution process and performing the convolution process according input dimension), wherein the first alignment requirement is equal to a maximum data processing capacity of an operation circuit in the slave processing circuit at one time, and a size of each aligned feature map block in the lowest storage dimension is equal to the maximum data processing capacity at one time (figures 1 & 5, pars. 0054-0056, figures 3-4, pars. 0084-0085, distributing input data based on the data size and data processing capacity).
As to claim 5, QI et al disclose that the master processing circuit is further configured to: divide the weight into blocks according to the output channel dimension, so that the scheduled slave processing circuits load corresponding weight blocks, wherein the weight block is divided into a plurality of weight lines according to the lowest storage dimension, and the weight lines are aligned to a first alignment requirement in the lowest storage dimension, wherein the first alignment requirement is determined according to a processing capacity of the slave processing circuit (figures 1-2, pars. 0021-0025 & 0054-0058 & 0068-0074, figures 3-4, pars. 0084-008, dividing input data according input dimension and distributing input data based on the data size and data processing capacity).
As to claim 6, QI et al disclose that the master processing circuit is further configured to: group a plurality of weight blocks continuously divided in the output channel dimension in sequence according to rounds of operations, wherein a count of weight blocks in each weight block group corresponds to a total operation capacity of scheduled slave processing circuits in a corresponding round of operation (see abstract, figure 1, pars. 0021-0025 & 0055-0058, page 6 column 1 lines 24-49, dividing input data according input dimension); segment the weight blocks in each weight block group in sequence according to the scheduled slave processing circuits in the corresponding round of operation, wherein each weight block segment corresponds to one scheduled slave processing circuit; and store each weight block segment in a storage area allocated for a corresponding slave processing circuit respectively (figures 1 & 5, pars. 0054-0056, figures 3-4, pars. 0084-0085, distributing input data based on the data size and data processing capacity).
As to claim 12, QI et al disclose that the master processing circuit is further configured to: concatenate operation results returned from the plurality of scheduled slave processing circuits in the multiple rounds of operations according to dividing and multiplexing methods to obtain a final result (figure 1 & 5, pars. 0019-0024 & 0080-0085).
As to claims 13-14, they are also rejected for the same reasons set forth to rejecting claim 1 above, since claims 13-14 do not teach or define any new limitations than above rejected claim 1.
Claim Objections
Claims 7-11 are objected to as being dependent upon a rejected base claim 1, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The examiner has found that the prior art of record does not disclose or teach or suggest or render obvious each slave processing circuit further comprises a first buffer circuit, a second buffer circuit, and a plurality of operation circuits defined in the claim 7 comprising: the first buffer circuit is configured to cache one or a plurality of weight lines divided according to the lowest storage dimension in at least one weight block corresponding to the slave processing circuit, the weight line is distributed to a corresponding operation circuit during the operation; and the second buffer circuit is configured to cache the feature map block broadcast by the master processing circuit, the feature map block is broadcast to all operation circuits in the slave processing circuit during the operation, each operation circuit is configured to perform an element-wise multiply-accumulate operation on the weight line distributed from the first buffer circuit and the feature map block broadcast from the second buffer circuit.
Additional References
The examiner as of general interest cites the following references.
Chen et al, U.S. Patent No. 12,423,560 B2.
Hoang et al, U.S. Patent No. 11,568,228 B2.
Content Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Bharat Barot whose telephone number is (571)272-3979. The examiner can normally be reached on 7:00AM-3:30PM.
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/BHARAT BAROT/Primary Examiner, Art Unit 2453August 17, 2026
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