Prosecution Insights
Last updated: August 17, 2026
Application No. 18/565,996

APPARATUS, METHOD, DEVICE AND MEDIUM FOR ACCELERATING COMPUTATION OF PROCESS ENGINE

Non-Final OA §101§102
Filed
Nov 30, 2023
Priority
Nov 25, 2021 — nonprovisional of PCTCN2021133099
Examiner
CHANNAVAJJALA, SRIRAMA T
Art Unit
Tech Center
Assignee
Intel Corporation
OA Round
1 (Non-Final)
74%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 74% — above average
74%
Career Allowance Rate
525 granted / 706 resolved
+14.4% vs TC avg
Strong +33% interview lift
Without
With
+32.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 3m
Avg Prosecution
24 currently pending
Career history
726
Total Applications
across all art units

Statute-Specific Performance

§101
21.3%
-18.7% vs TC avg
§103
44.9%
+4.9% vs TC avg
§102
16.5%
-23.5% vs TC avg
§112
12.6%
-27.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 706 resolved cases

Office Action

§101 §102
CTNF 18/565,996 CTNF 74683 Notice of Pre-AIA or AIA Status The present application 89/565,996 , filed on 11/30/2023 ( or after March 16, 2013), is being examined under the first inventor to file provisions of the AIA ( First Inventor to File) . 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. This application is a 371 of PCT/CN2021/133099 11/25/2021 DETAILED ACTION Claims 1-13,15,17-21,23 are pending, canceled claim 14,16,22,24-25 in this application. Examiner acknowledges applicant’s preliminary amendment filed on 11/30/2023 Drawings The Drawings filed on 11/30/2023 are acceptable for examination purpose. Information Disclosure Statement The information disclosure statement (IDS) submitted on 3/4/2025, 11/30/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner Claim Rejections - 35 USC § 101 07-04-01 AIA 07-04 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. Claims 1-13,15,17-21,23 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The judicial exception is not integrated into a practical application . Claim 1-20 is/are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The judicial exception is not integrated into a practical application. The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. The eligibility analysis in support of these findings is provided below, in accordance with the 2019 Revised Patent Subject Matter Eligibility Guidance , Federal Register (84 FR 50) on January 7, 2019 hereinafter 2019 PEG Step 1. In accordance with Step 1 of the eligibility inquiry (as explained in MPEP 2106), it is noted that the method of claim 1,9,15, directed to one of the eligible categories of subject matter and therefore satisfy Step 1. Step 2A. In accordance with Step 2A prong one of the 2019 PEG, the limitations reciting the abstract idea are highlighted, and the limitations directed to additional elements are highlighted, as set forth in exemplary claim 1 Claim 1,9,17 “interface circuitry to receive weight data and activation data, the weight data and the activation data stored in a batch-height-width-channel (NHWC) memory layout; instructions: and processor circuitry to execute the instructions to: determine a process capacity of a process engine; determine an input channel size; in response to the input channel size not being an integer multiple of the process capacity, pad a number of zeroes after a last element of weight data belonging to a filter and a last element of corresponding activation data respectively, wherein the number equals to an absolute difference between the process capacity of process engine and a remainder of a product of the input channel size and a kernel width and a kernel height of the filter divided by the process capacity of process engine, slice all weight data elements belonging to the filter and zeroes padded after the last element of the weight data into weight data slices in a scale of the process capacity, and corresponding activation data elements and zeroes padded after the last element of the corresponding activation data into corresponding activation data slices in the scale of the process capacity, and feed the process engine with each weight data slice and a corresponding activation data slice sequentially”, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. For example “input channel size, pad a number of zeroes, weight data, number equals to an absolute difference, kernel width, kernel height, slice all weight data, process capacity, feed the process engine, activation data slice…..”, appears mere data structure manipulation in the context of this claim encompasses the user thinking mere data gathering of the process capacity. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas set forth in the 2019 PEG . Accordingly, the claim recites an abstract idea. With respect to Step 2A prong two of the 2019 PEG, the judicial exception is not integrated into a practical application. The additional elements are directed to method steps, however, these elements fail to integrate the abstract idea into a practical application because they fail to provide an improvement to the functioning of a computer or to any other technology or technical field, fail to apply the exception with a particular machine, fail to apply the judicial exception to effect a particular memory data structure of channel size, kernel width, kernel height, filter divided by the process capacity, to effect a transformation of a particular article to a different state or thing, and fail to apply/use the abstract idea in a meaningful way beyond generally linking the use of the judicial exception to a particular technological environment. Furthermore, although these elements have been fully considered, they are directed to the use of generic computing elements (fig 7, para 76-84,89-90, of the instant specification make it clear that the disclosed functionality is implemented on well-known computing systems and general purpose computing devices) to perform the abstract idea, which is not sufficient to amount to a practical application (as noted in the 2019 PEG ) and is amount to simply saying "apply it" using a general purpose computer, which merely serves to tie the abstract idea to a particular technological environment computer based operating environment) by using the computer as a tool to perform the abstract idea. Since the analysis of Step 2A prong one and prong two results in the conclusion that the claims are directed to an abstract idea, additional analysis under Step 2B of the eligibility inquiry must be conducted in order to determine whether any claim element or combination of elements amount to significantly more than the judicial exception. Step 2B . The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. The additional method limitations are directed to a generic computer, at a very high level of generality and without imposing meaningful limitations on the scope of the claim. In addition fig 7, para 76-84,89-90 of the instant specification describe generic off-the-shelf computer-based elements for implementing the claimed invention which does not amount to significantly more than the abstract idea and is not enough to transform an abstract idea into eligible subject matter. Such generic, high-level, and nominal involvement of a computer or computer-based elements for carrying out the invention merely serves to tie the abstract idea to a particular technological environment, which is not enough to render the claims patent- eligible, as noted at pg. 74624 of Federal Register/Vol. 79, No. 241, citing Alice, which in turn cites Mayo. Further, See, e.g., Alice Corp. Pty. Ltd. v. CLS Bank Int'l, 134 S. Ct. 2347, 2359-60, 110 USPQ2d 1976, 1984 (2014). See also OIP Techs. v. Amazon.com, 788 F.3d 1359, 1364, 115 USPQ2d 1090, 1093-94 (Fed. Cir. 2015) ("Just as Diehr could not save the claims in Alice, which were directed to 'implement[ing] the abstract idea of intermediated settlement on a generic computer', it cannot save O/P's claims directed to implementing the abstract idea of price optimization on a generic computer.") (citations omitted). See also, Affinity Labs of Texas LLC v. DirecTV LLC, 838 F.3d 1253, 1257-1258 (Fed. Cir. 2016) (mere recitation of a GUI does not make a claim patent-eligible); Intellectual Ventures I LLC v. Capital One Bank, 792 F.3d 1363, 1370 (Fed. Cir. 2015) ("the interactive interface limitation is a generic computer element".) he additional elements are broadly applied to the abstract idea at a high level of generality ("similar to how the recitation of the computer in the claims in Alice amounted to mere instructions to apply the abstract idea of intermediated settlement on a generic computer,") as explained in MPEP § 2106.05(f)) and they operate in a well-understood, routine, and conventional manner. MPEP § 2106.05 (d)(II) sets forth the following: The courts have recognized the following computer functions as well-understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g. at a high level of generality) as insignificant extra-solution activity. Receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec...; TLI Communications LLC v. AV Auto. LLC...; OIP Techs., Inc., v. Amazon.com, Inc... ; buySAFE, Inc. v. Google, Inc...; Performing repetitive calculations, Flook ... ; Bancorp Services v. Sun Life...; Electronic recordkeeping, Alice Corp...; Ultramercial... ; Storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc...; Electronically scanning or extracting data from a physical document, Content Extraction and Transmission, LLC v. Wells Fargo Bank...; and A web browser's back and forward button functionality, Internet Patent Corp. v. Active Network, Inc. Courts have held computer-implemented processes not to be significantly more than an abstract idea (and thus ineligible) where the claim as a whole amounts to nothing more than generic computer functions merely used to implement an abstract idea, such as an idea that could be done by a human analog (i.e., by hand or by merely thinking). claim 2,10,18, further elaborates “wherein a weight data slice comprises weight data elements from one or more data groups belonging to the filter, and each data group comprises weight data elements of the input channel size”, which have been determined to be extra-solution activity that does not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(b)(I). Even in combination, the additional details recited in these claims do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. Claim 3,11,19, further elaborates “wherein the processor circuitry is to perform the padding slicing, and feeding operations on weight data belonging to a next filter and corresponding activation data”, which have been determined to be extra-solution activity that does not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(b)(I). Even in combination, the additional details recited in these claims do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. Claim 4,12,20, further elaborates “wherein the process engine is neural network acceleration hardware, the neural network acceleration hardware to calculate an inner product or convolution of data elements in the scale of the process capacity”, which have been determined to be extra-solution activity that does not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(b)(I). Even in combination, the additional details recited in these claims do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. Claim 5,13,21, further elaborates “wherein the process capacity of the process engine is 16, the input channel size is 8, and both the kernel width and the kernel height of the filter are 3, and the processor circuitry is to :pad 8 zeroes after a last element of weight data belonging to the filter and a last element of corresponding activation data respectively; slice all 72 weight data elements belonging to the filter and 8 zeroes padded after the last element of the weight data into 5 weight data slices and corresponding 72 activation data elements and 8 zeroes padded after the last element of the corresponding activation data into corresponding 5 activation data slices, each of the 5 weight data slices and the corresponding 5 activation data slices comprising 16 data elements; and feed the process engine with each of the 5 weight data slices and a corresponding activation data slice sequentially in 5 computation cycles”, which have been determined to be extra-solution activity that does not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(b)(I). Even in combination, the additional details recited in these claims do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. Claim 6, further elaborates “wherein a memory utilization ratio is 90%”, which have been determined to be extra-solution activity that does not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(b)(I). Even in combination, the additional details recited in these claims do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. Claim 7,15,23, further elaborates “wherein the process capacity of the process engine is 16, the input channel size is 24, and both the kernel width and the kernel height of the filter are 3, and the processor circuitry is to: pad 8 zeroes after a last element of weight data belonging to the filter and a last element of corresponding activation data respectively; slice all 216 weight data elements belonging to the filter and 8 zeroes padded after the last element of the weight data into 14 weight data slices and corresponding 216 activation data elements and 8 zeroes padded after the last element of the corresponding activation data into corresponding 14 activation data slices, each of the 14 weight data slices and the corresponding 14 activation data slices comprising 16 data elements; and feed the process engine with each of the 14 weight data slices and a corresponding activation data slice sequentially in 14 computation cycles”, which have been determined to be extra-solution activity that does not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(b)(I). Even in combination, the additional details recited in these claims do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. claim 8, further elaborates “wherein a memory utilization ratio is 96.42%”, which have been determined to be extra-solution activity that does not impose any meaningful limits on practicing the abstract idea. See MPEP 2106.05(b)(I). Even in combination, the additional details recited in these claims do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. The examiner suggests that the applicant review the specification of the instant application to find further teachings that if recited in said claims, may provide significantly more to the judicial exception. Such elements / limitations that can be considered as significantly more recite an improvement to another technology or technical field, an improvement to the functioning of a computer itself, or meaningful limitations beyond generally linking the use of an abstract idea to a particular technological environment. Claim 14 (canceled) Claim 16 (canceled) Claim 22 (canceled) Claim 24-25 (canceled) Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15-aia AIA Claim(s) 1-13,15,17-21,23 is/are rejected under i s/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Ross et al., (hereafter Ross), US Pub. No. 2020/0159814 published May, 2020 . As to Claim 1,9,17, .Ross teachs a system which including an apparatus, comprising (Ross: fig 23) “interface circuitry (0264 – hardware engine comprise dedicated circuitry or logic) to receive weight data and activation data, the weight data (Ross: 0240 – Ross teaches weight data stored in a particular multiplier) and the activation data stored ( Ross: 0155)in a batch-height-width-channel (NHWC) memory layout; instructions(Ross: fig 1, 0052-0053, ,fig 11, 0079, 0155-0158, 0198 – Ross teaches memory layout data structure with respect to current tile, row or column, width/height and depth of a matrix of the input tensor element 102 used in selecting the data values stored. Ross teaches values in all positions are generated as control pattern square matrix having width, height of the kernel as detailed in 0158, it is noted that data storage in multi-dimensional array identifying height and width information stored in the channels and PNG media_image1.png 260 233 media_image1.png Greyscale PNG media_image2.png 179 235 media_image2.png Greyscale “processor circuitry to execute the instructions to: (Ross: fig 23, 0256-0257 – Ross teaches computer system defining instructions element 2324) “determine a process capacity of a process engine” (Ross: fig 1, 0052-0053); “determine an input channel size” (Ross: fig 1, 0059 – Ross teaches multiple tiles defining each channel size); PNG media_image3.png 169 142 media_image3.png Greyscale “in response to the input channel size not being an integer multiple of the process capacity” (Ross: fig 2, 0053, 0058-0060 – Ross teaches multiple channel size(s) divides the matrix of each input channel for example as shown in fig 1 where each input channel determines the size, values with respect to column-major order, diagonal-major order of respective layer), “pad a number of zeroes after a last element of weight data belonging to a filter and a last element of corresponding activation data respectively, (Ross: 0054,0057-0058,0067, 0098, fig 4, 0104-0106 – Ross teaches pad the input tensor ith respect to size and generating the respective value reaches every input value in the input tensor reaches including two dimensional matrix of the input tensor, input with padding, it should be noted that padding values may be zero or null or some other values because input tensor has largest index value); PNG media_image4.png 129 269 media_image4.png Greyscale wherein the number equals to an absolute difference between the process capacity of process engine and a remainder of a product of the input channel size and a kernel width and a kernel height of the filter divided by the process capacity of process engine (Ross: ,fig 4, 0105-106, fig 5C-6, 0116-0118 – Ross teaches multiple input channels are convolved with the kernel and generate an output features, and the input stream generator pads each input channel with respect to the channel size and kernel width) PNG media_image5.png 248 185 media_image5.png Greyscale PNG media_image6.png 96 170 media_image6.png Greyscale “slice all weight data elements belonging to the filter and zeroes padded after the last element of the weight data into weight data slices in a scale of the process capacity, and corresponding activation data elements and zeroes padded after the last element of the corresponding activation data into corresponding activation data slices in the scale of the process capacity” (Ross: fig 5-6, fig 9, 0054,0059,0085,0088-0089,0116 – Ross teaches slice of respective weights associated with the two dimensional kernels of different sizes and convolution operation is performed on each of channel with sub-filter or filter kennel, applying different kernel weights to different parts of inputs, further position of the input values, padding of the width of the matrix determines the size of the kernel as detailed in 0088-0089) “feed the process engine with each weight data slice and a corresponding activation data slice sequentially” (Ross: fig 13A-B, 0176-0177,0183-0184 – Ross teaches pattern processing generating engine generates position of the row, column and the respective identified tile size of each dimension in the input tensor, and the weight data indicates the tile size) PNG media_image7.png 344 224 media_image7.png Greyscale PNG media_image8.png 331 230 media_image8.png Greyscale As to claim 2,10,18, Ross disclosed “wherein a weight data slice comprises weight data elements from one or more data groups belonging to the filter, and each data group comprises weight data elements of the input channel size” (Ross: fig 13A-13B, 0178-0179,0183-0184). As to Claim 3,11,19, Ross disclosed “wherein the processor circuitry is to perform the padding slicing, and feeding operations on weight data belonging to a next filter and corresponding activation data” (Ross: fig 4-5, 0104-0108). PNG media_image9.png 307 224 media_image9.png Greyscale As to Claim 4,12,20, Ross disclosed “wherein the process engine is neural network acceleration hardware, the neural network acceleration hardware to calculate an inner product or convolution of data elements in the scale of the process capacity” (Ross: 0003,0053-0054, fig 1). As to Claim 5,13,21, Ross disclosed “wherein the process capacity of the process engine is 16, the input channel size is 8, and both the kernel width and the kernel height of the filter are 3, and the processor circuitry is to (Ross: Abstract, fig 1) :”pad 8 zeroes after a last element of weight data belonging to the filter and a last element of corresponding activation data respectively” (Ross: fig 4,0105-017); “slice all 72 weight data elements belonging to the filter and 8 zeroes padded after the last element of the weight data into 5 weight data slices and corresponding 72 activation data elements and 8 zeroes padded after the last element of the corresponding activation data into corresponding 5 activation data slices, each of the 5 weight data slices and the corresponding 5 activation data slices comprising 16 data elements” (Ross: fig 13A-13B, 0176-0180); and “feed the process engine with each of the 5 weight data slices and a corresponding activation data slice sequentially in 5 computation cycles” (Ross: 0198-0200). As to Claim 6, Ross wherein a memory utilization ratio is 90% (Ross: 0165,0200-0201). As to Claim 7,15,23, Ross disclosed “wherein the process capacity of the process engine is 16, the input channel size is 24, and both the kernel width and the kernel height of the filter are 3, and the processor circuitry is to” (Ross: Abstract, fig 1, fig 4): pad 8 zeroes after a last element of weight data belonging to the filter and a last element of corresponding activation data respectively” (Ross: fig 4,5A, 0105-0110); “slice all 216 weight data elements belonging to the filter and 8 zeroes padded after the last element of the weight data into 14 weight data slices and corresponding 216 activation data elements and 8 zeroes padded after the last element of the corresponding activation data into corresponding 14 activation data slices, each of the 14 weight data slices and the corresponding 14 activation data slices comprising 16 data elements” Ross: fig 13A-13B, 0152-0159,0176-0180; and feed the process engine with each of the 14 weight data slices and a corresponding activation data slice sequentially in 14 computation cycles” (Ross: 0198-0203). As to claim 8, Ross disclosed “wherein a memory utilization ratio is 96.42%” (Ross: 0165,0186-0187,0200-0201. Claim 14 (canceled) Claim 16 (canceled) Claim 22 (canceled) Claim 24-25 (canceled) Conclusion The prior art made of record a. US Pub. No. 2020/0159814 Examiner's Note: Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. SEE MPEP 2141.02 [R-5] VI. PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS: A prior art reference must be considered in its entirety, i.e., as a whole, including portions that would lead away from the claimed invention. W.L. Gore & Associates, Inc. v. Garlock, Inc., 721 F.2d 1540, 220 USPQ 303 (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984) In re Fulton, 391 F.3d 1195, 1201,73 USPQ2d 1141, 1146 (Fed. Cir. 2004). >See also MPEP §2123. In the case of amending the Claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. The prior art made of record, listed on form PTO-892, and not relied upon, if any, is considered pertinent to applicant's disclosure Authorization for Internet Communications The examiner encourages Applicant to submit an authorization to communicate with the examiner via the Internet by making the following statement (from MPEP 502.03): “Recognizing that Internet communications are not secure, I hereby authorize the USPTO to communicate with the undersigned and practitioners in accordance with 37 CFR 1.33 and 37 CFR 1.34 concerning any subject matter of this application by video conferencing, instant messaging, or electronic mail. I understand that a copy of these communications will be made of record in the application file.” Please note that the above statement can only be submitted via Central Fax (not Examiner's Fax), Regular postal mail, or EFS Web using PTO/SB/439 . Any inquiry concerning this communication or earlier communications from the examiner should be directed to Srirama Channavajjala whose telephone number is 571-272-4108. The examiner can normally be reached on Monday-Friday from 8:00 AM to 5:30 PM Eastern Time. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Gorney, Boris, can be reached on (571) 270- 5626. The fax phone numbers for the organization where the application or proceeding is assigned is 571-273-8300 Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free) /Srirama Channavajjala/Primary Examiner, Art Unit 2154 Application/Control Number: 18/565,996 Page 2 Art Unit: 2154 Application/Control Number: 18/565,996 Page 3 Art Unit: 2154 Application/Control Number: 18/565,996 Page 4 Art Unit: 2154 Application/Control Number: 18/565,996 Page 5 Art Unit: 2154 Application/Control Number: 18/565,996 Page 6 Art Unit: 2154 Application/Control Number: 18/565,996 Page 7 Art Unit: 2154 Application/Control Number: 18/565,996 Page 8 Art Unit: 2154 Application/Control Number: 18/565,996 Page 9 Art Unit: 2154 Application/Control Number: 18/565,996 Page 11 Art Unit: 2154 Application/Control Number: 18/565,996 Page 12 Art Unit: 2154 Application/Control Number: 18/565,996 Page 13 Art Unit: 2154 Application/Control Number: 18/565,996 Page 14 Art Unit: 2154 Application/Control Number: 18/565,996 Page 15 Art Unit: 2154 Application/Control Number: 18/565,996 Page 16 Art Unit: 2154
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Prosecution Timeline

Nov 30, 2023
Application Filed
May 26, 2026
Non-Final Rejection mailed — §101, §102 (current)

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