DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-13 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Gu (CN 107919090 A) in view of He (CN 114497151 A).
As to claim 1, Gu teaches
a display panel comprising a display area (see at least fig. 2a and [0049] “the display panel provided in this embodiment includes: a first display area A1, a second display area A2”), the display panel comprising:
first thin film transistors located in the display area (see at least fig. 2b: pixels 106 and [0051] “Both the pixel circuit and the driving circuit include thin-film transistors”); and
fan-out traces located in the display area (see at least figs. 3, 6-8 and [0049] “the second display area includes a driving signal line 102 extending along a first direction and a data signal line 101 extending along a second direction, wherein the driving signal line 102 is correspondingly connected to the driving circuit 1021, and the data signal line 101 is electrically connected to the driving chip 107 through a fan-out segment 1011; the fan-out segment 1011 and the driving circuit 1021 overlap at least partially in a direction perpendicular to the display panel.”; [0066] “the fan-out section and the driving circuit can be stacked in the thickness direction of the display panel”);
wherein each first thin film transistor comprises a first gate (see at least [0051] “The gate 202 of the thin-film transistor is disposed in the first metal layer”);
each fan-out trace comprises a first fan-out sub-section located on one side of the first gate away from the substrate (see at least [0051] “one electrode of the capacitor may be located on the first metal layer, …The gate 202 of the thin-film transistor is disposed in the first metal layer”; [0052] “The fan-out section 1011 is arranged in the same layer as the first electrode 205.”),
an orthographic projection of the first fan-out sub-section on the substrate and an orthographic projection of the first gate on the substrate have a first overlapping portion (see at least [0049] “the fan-out segment 1011 and the driving circuit 1021 overlap at least partially in a direction perpendicular to the display panel.”; [0051]: gate 202 is part of the driving circuit);
the thin film transistor layer further comprises a first conductor layer located between the first gate and the first fan-out sub-section (see at least [0051]: gate 202 is in the driving circuit; [0052]: fan-out is disposed in the same layer as first electrode 205; [0058] “a third metal layer is disposed between the first electrode 205 and the driving circuit.” – note the third metal layer lies between the gate and the fan-out layer and is the first conductor layer),
each first thin film transistor further comprises a first shielding portion located in the first conductor layer (see at least [0058] “a signal shielding layer is also included between the fan-out section and the drive circuit. .. The signal shielding layer is disposed on the third metal layer to shield the signal interference between the fan-out section and the driving circuit” – note since the third metal layer lies between gate and fan-out, and shielding layer is disposed on that metal layer, this corresponds to the claimed shielding portion located in the conductor layer. The shielding layer corresponds to the TFT regions beneath it because it is arranged between fan-out and driving circuit regions),
an orthographic projection of the first shielding portion on the substrate at least partially overlaps the first overlapping portion (see at least [0049] fan-out overlaps driving circuit in perpendicular direction; [0058] shielding layer is “between the fan-out section and the drive circuit” – note the shielding layer overlaps the same overlapping region in projection).
Gu does not directly teach wherein a spacing between one side of the first shielding portion close to the first gate and one side of the first gate close to the first shielding portion is greater than a spacing between one side of the first shielding portion close to the first fan-out sub-section and one side of the first fan-out sub-section close to the first shielding portion.
He teaches a display panel comprising:
a substrate (see at least [0043] “the array substrate 4 also includes a substrate 8”);
a thin film transistor layer located on one side of the substrate (see at least [0043] “a buffer layer 9 and a thin-film transistor layer 10 sequentially disposed on the substrate 8”);
an orthographic projection of the first fan-out sub-section on the substrate and an orthographic projection of the first gate on the substrate have a first overlapping portion (see at least [0046] “the overlapping arrangement described in this application refers to the overlapping projections of two traces arranged on different layers (different layers) in a direction perpendicular to the array substrate 4.” – note because the gate 202 is part of the driving circuit (see [0051] of Gu), the perpendicular overlap inherently includes overlap between the fan-out segment and gate region in projection);
wherein a spacing between one side of the first shielding portion close to the first gate and one side of the first gate close to the first shielding portion is greater than a spacing between one side of the first shielding portion close to the first fan-out sub-section and one side of the first fan-out sub-section close to the first shielding portion (see at least [0004] “the fanout traces are distributed within the pixels of the display area”; [0038] “the fan-out traces in the display area form parasitic capacitances with the gate (Q point) of the driving TFT (Thin Film Transistor), which affects the stability of the driving TFT”; [0065] “reduce the parasitic capacitance between the fan-out trace 5 and the gate (e.g., the first gate 28 and the second gate 30) of the driving thin film transistor 23”; [0067] “the shielding layer 42 is electrically connected to the power supply voltage signal line 19” – note Gu teaches capacitance depends on distance ([0057]-[0058]), it would have been obvious to adjust relative lateral spacing so that shielding is positioned closer to fan-out and further from gate, thereby reducing parasitic coupling into gate to improve TFT stability).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention that the effectiveness of the shielding layer depends on the relative spacing between the shield, the fan-out trace, and the gate. Since parasitic capacitance increases as the distance between conductors decreases, it would have been an obvious design choice to position the shielding portion closer to the fan-out trace and farther from the gate. Doing so would cause the shield to preferentially couple with the fan-out trace and reduce capacitive coupling to the gate, thereby improving TFT stability, as taught by He ([0038], [0065]). Adjusting the lateral spacing between conductive elements to control parasitic capacitance is a routine optimization based on well-known electrical principles. This modification would not alter the basic structure or operation of Gu’s display panel, but would merely optimize the relative positioning of existing conductive layers to reduce interference. Accordingly, it would have been obvious to modify Gu in view of He to arrive at the claimed spacing relationship as a predictable structural refinement directed to reducing parasitic capacitance and stabilizing the driving TFT.
As to claim 16, Gu teaches
a display panel comprising a display panel (see at least fig. 2a and [0049] “the display panel provided in this embodiment includes: a first display area A1, a second display area A2”), the display panel comprising:
first thin film transistors located in the display area (see at least fig. 2b: pixels 106 and [0051] “Both the pixel circuit and the driving circuit include thin-film transistors”); and
fan-out traces located in the display area (see at least figs. 3, 6-8 and [0049] “the second display area includes a driving signal line 102 extending along a first direction and a data signal line 101 extending along a second direction, wherein the driving signal line 102 is correspondingly connected to the driving circuit 1021, and the data signal line 101 is electrically connected to the driving chip 107 through a fan-out segment 1011; the fan-out segment 1011 and the driving circuit 1021 overlap at least partially in a direction perpendicular to the display panel.”; [0066] “the fan-out section and the driving circuit can be stacked in the thickness direction of the display panel”);
wherein each first thin film transistor comprises a first gate (see at least [0051] “The gate 202 of the thin-film transistor is disposed in the first metal layer”);
each first thin film transistor further comprises a first shielding portion located in the first conductor layer (see at least [0058] “a signal shielding layer is also included between the fan-out section and the drive circuit. .. The signal shielding layer is disposed on the third metal layer to shield the signal interference between the fan-out section and the driving circuit” – note since the third metal layer lies between gate and fan-out, and shielding layer is disposed on that metal layer, this corresponds to the claimed shielding portion located in the conductor layer. The shielding layer corresponds to the TFT regions beneath it because it is arranged between fan-out and driving circuit regions),
an orthographic projection of the first shielding portion on the substrate at least partially overlaps the first overlapping portion (see at least [0049] fan-out overlaps driving circuit in perpendicular direction; [0058] shielding layer is “between the fan-out section and the drive circuit” – note the shielding layer overlaps the same overlapping region in projection).
Gu does not directly teach wherein a spacing between one side of the first shielding portion close to the first gate and one side of the first gate close to the first shielding portion is greater than a spacing between one side of the first shielding portion close to the first fan-out sub-section and one side of the first fan-out sub-section close to the first shielding portion.
He teaches a display panel comprising:
a substrate (see at least [0043] “the array substrate 4 also includes a substrate 8”);
a thin film transistor layer located on one side of the substrate (see at least [0043] “a buffer layer 9 and a thin-film transistor layer 10 sequentially disposed on the substrate 8”);
an orthographic projection of the first fan-out sub-section on the substrate and an orthographic projection of the first gate on the substrate have a first overlapping portion (see at least [0046] “the overlapping arrangement described in this application refers to the overlapping projections of two traces arranged on different layers (different layers) in a direction perpendicular to the array substrate 4.” – note because the gate 202 is part of the driving circuit (see [0051] of Gu), the perpendicular overlap inherently includes overlap between the fan-out segment and gate region in projection); and
wherein a spacing between one side of the first shielding portion close to the first gate and one side of the first gate close to the first shielding portion is greater than a spacing between one side of the first shielding portion close to the first fan-out sub-section and one side of the first fan-out sub-section close to the first shielding portion. (see at least [0004] “the fanout traces are distributed within the pixels of the display area”; [0038] “the fan-out traces in the display area form parasitic capacitances with the gate (Q point) of the driving TFT (Thin Film Transistor), which affects the stability of the driving TFT”; [0065] “reduce the parasitic capacitance between the fan-out trace 5 and the gate (e.g., the first gate 28 and the second gate 30) of the driving thin film transistor 23”; [0067] “the shielding layer 42 is electrically connected to the power supply voltage signal line 19” – note Gu teaches capacitance depends on distance ([0057]-[0058]), it would have been obvious to adjust relative lateral spacing so that shielding is positioned closer to fan-out and further from gate, thereby reducing parasitic coupling into gate to improve TFT stability).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention that the effectiveness of the shielding layer depends on the relative spacing between the shield, the fan-out trace, and the gate. Since parasitic capacitance increases as the distance between conductors decreases, it would have been an obvious design choice to position the shielding portion closer to the fan-out trace and farther from the gate. Doing so would cause the shield to preferentially couple with the fan-out trace and reduce capacitive coupling to the gate, thereby improving TFT stability, as taught by He ([0038], [0065]). Adjusting the lateral spacing between conductive elements to control parasitic capacitance is a routine optimization based on well-known electrical principles. This modification would not alter the basic structure or operation of Gu’s display panel, but would merely optimize the relative positioning of existing conductive layers to reduce interference. Accordingly, it would have been obvious to modify Gu in view of He to arrive at the claimed spacing relationship as a predictable structural refinement directed to reducing parasitic capacitance and stabilizing the driving TFT.
As to claim 2, the combination of Gu and He teach the display panel according to claim 1 (see above rejection), wherein the first overlapping portion is located in the orthographic projection of the first shielding portion on the substrate (see Gu at least [0049] “the fan-out segment 1011 and the driving circuit 1021 overlap at least partially in a direction perpendicular to the display panel.”; [0058] “The signal shielding layer is disposed on the third metal layer to shield the signal interference between the fan-out section and the driving circuit” – note since the shielding layer is positioned between the fan-out and the driving circuit and arranged to shield the interference in the overlapping region, its projection necessarily covers the overlapping region).
As to claim 3, the combination of Gu and He teach the display panel according to claim 2 (see above rejection), wherein the first shielding portion is electrically connected to a constant voltage signal port of the display panel (see Gu at least [0059] “a fixed potential signal can be connected to the signal shielding layer. .. the signal shielding layer 209 can also be connected to the first power signal”; and He at least [0067] “the shielding layer 42 is electrically connected to the power supply voltage signal line 19”).
As to claim 4, the combination of Gu and He teach the display panel according to claim 1 (see above rejection), wherein a ratio of the spacing between the side of the first shielding portion close to the first gate and the side of the first gate close to the first shielding portion and the spacing between the side of the first shielding portion close to the first fan-out sub-section and the side of the first fan-out sub-section close to the first shielding portion is greater than 1; and the ratio of the spacing between the side of the first shielding portion close to the first gate and the side of the first gate close to the first shielding portion and the spacing between the side of the first shielding portion close to the first fan-out sub-section and the side of the first fan-out sub-section close to the first shielding portion is less than or equal to 5.5 (see Gu at least [0057] “the magnitude of the coupling capacitance depends on the distance between the electrodes.”; and He at least [0038], [0065] “embodiments of this application can reduce the parasitic capacitance between the fan-out trace 5 and the gate (e.g., the first gate 28 and the second gate 30) of the driving thin film transistor 23 in the sub-pixel area 22,)”). Selection of a ratio greater than 1 and less than/equal to 5.5 constitutes routine layout optimization within known TFT lithographic constraints. No unexpected result is alleged.
As to claim 5, the combination of Gu and He teach the display panel according to claim 4 (see above rejection), wherein the spacing between the side of the first shielding portion close to the first gate and the side of the first gate close to the first shielding portion is greater than or equal to 300 nm, and the spacing between the side of the first shielding portion close to the first gate and the side of the first gate close to the first shielding portion is less than or equal to 1100 nm; and the spacing between the side of the first shielding portion close to the first fan-out sub-section and the side of the first fan-out sub-section close to the first shielding portion is greater than or equal to 200 nm, and the spacing between the side of the first shielding portion close to the first fan-out sub-section and the side of the first fan-out sub-section close to the first shielding portion is less than or equal to 800 nm (see Gu at least [0057] “the magnitude of the coupling capacitance depends on the distance between the electrodes.”; and He at least [0038], [0065] “embodiments of this application can reduce the parasitic capacitance between the fan-out trace 5 and the gate (e.g., the first gate 28 and the second gate 30) of the driving thin film transistor 23 in the sub-pixel area 22,)”). Selection of specific nanometer ranges, constitutes routine layout optimization within known TFT lithographic constraints. No unexpected result is alleged. Numeric optimization within typical sub-micron TFT process ranges is a matter of routine engineering design.
As to claim 6, the combination of Gu and He teach the display panel according to claim 1 (see above rejection), further comprising a plurality of data lines located in the display area, the data lines being connected to the first fan-out sub-sections; each fan-out trace further comprises a second fan-out sub-section, the first fan-out sub-section extends in a first direction, the second fan-out sub-section extends in a second direction, each data line extends in the second direction, and the first direction intersects the second direction; and the second fan-out sub-section is located on one side of the first fan-out sub-section away from the substrate (see He at least figs. 1, 2; [0044] “each fan-out routing line 5 includes a first routing section 15… extending along the second direction, and a second routing section 16… extending along the first direction.”; [0049] “multiple data lines 18”).
As to claim 7, the combination of Gu and He teach the display panel according to claim 6 (see above rejection), wherein the data lines and the first fan-out sub-sections are disposed in a same layer (see He at least [0047] “the second wiring section 16 and the first wiring section 15 can be set on the same layer or on different layers”; [0060] “multiple fan-out routing lines 5 are located on the first flat layer 33.”; [0073] “the data line 18 is disposed on the same layer as the second sub-power supply voltage signal line 47.” – note setting data lines and fan-out in the same layer is a conventional routing choice depending on process constraints).
As to claim 8, the combination of Gu and He teach the display panel according to claim 6 (see above rejection), wherein the plurality of data lines are connected with the fan-out traces on a one-to-one basis (see He at least [0049] “multiple fan-out traces 5 are electrically connected to the multiple data lines 18 in a one-to-one correspondence.”).
As to claim 9, the combination of Gu and He teach the display panel according to claim 1 (see above rejection), wherein each first thin film transistor further comprises a first active layer and a first source-drain layer, the first active layer is located on the side of the first gate close to the substrate, the first fan-out sub-section and the first source-drain layer are disposed in a same layer; the thin film transistor layer further comprises a first insulating layer and a second insulating layer, the first insulating layer is disposed between the first gate and the first conductor layer, and the second insulating layer is disposed between the first conductor layer and the first fan-out sub-section; and a thickness of the first insulating layer is greater than a thickness of the second insulating layer (see Gu at least [0051] “The gate 202… disposed in the first metal layer”; [0055] “a planarization layer is provided between the first electrode 205 and the driving circuit”; [0057] “an insulating layer is provided between the third metal layer and the driving circuit”; [0055]-[0057]: varying insulating thickness to control capacitance).
As to claim 10, the combination of Gu and He teach the display panel according to claim 9 (see above rejection), wherein the thin film transistor layer further comprises second thin film transistors located in the display area, the second thin film transistors being electrically connected to the first thin film transistors; and each second thin film transistor comprises a second active layer, a second gate, a third gate, and a second source-drain layer, wherein the second active layer is located on one side of the first active layer away from the substrate, the second gate and the first shielding portion are disposed in a same layer, the second source-drain layer and the first source-drain layer are disposed in a same layer, and the third gate is located on one side of the second active layer close to the substrate (see He at least [0057] “the driving thin film transistor 23 includes… first gate 28… second gate 30…” – note placement of gates and shielding in the same layer is an obvious layout choice).
As to claim 11, the combination of Gu and He teach the display panel according to claim 10 (see above rejection), wherein the first insulating layer comprises a first insulating sub-layer, a second insulating sub-layer, and a third insulating sub-layer, the first insulating sub-layer being located between the first gate and the third gate, the second insulating sub-layer being located between the third gate and the second active layer, and the third insulating sub-layer being located between the second active layer and the first conductor layer (see He at least [0057]: insulating layers 27, 29, 31 – note layer subdivision into sub-layers is conventional TFT stack architecture).
As to claim 12, the combination of Gu and He teach the display panel according to claim 9 (see above rejection), further comprising a light-emitting device layer on one side of the first source-drain layer away from the substrate, the light-emitting device layer comprising a light-emitting device comprising an anode; and the display panel further comprises a second conductor layer located between the first source-drain layer and the light-emitting device layer, the second conductor layer comprising a transition portion, the anode being connected to the transition portion, the first source-drain layer comprising a first source and a first drain, and the transition portion being connected to the first source or the first drain (see He at least [0061] “organic light-emitting layer 6… includes an anode layer 35”; [0062] “the anode layer 35 is electrically connected to the drain 26 … second source/drain electrode block 41”).
As to claim 13, the combination of Gu and He teach the display panel according to claim 12 (see above rejection), wherein the second fan-out sub-sections of the fan-out traces are located in the second conductor layer (see He at least [0047] “the second wiring section 16 and the first wiring section 15 can be set on the same layer or on different layers” – note placing fan-out sections in a particular conductor layer is a routine routing decision).
As to claim 17, the combination of Gu and He teach the display device according to claim 16 (see above rejection), wherein the first overlapping portion is located in the orthographic projection of the first shielding portion on the substrate (see Gu at least [0049] “the fan-out segment 1011 and the driving circuit 1021 overlap at least partially in a direction perpendicular to the display panel.”; [0058] “The signal shielding layer is disposed on the third metal layer to shield the signal interference between the fan-out section and the driving circuit” – note since the shielding layer is positioned between the fan-out and the driving circuit and arranged to shield the interference in the overlapping region, its projection necessarily covers the overlapping region).
As to claim 18, the combination of Gu and He teach the display device according to claim 17 (see above rejection), wherein the first shielding portion is electrically connected to a constant voltage signal port of the display panel (see Gu at least [0059] “a fixed potential signal can be connected to the signal shielding layer. .. the signal shielding layer 209 can also be connected to the first power signal”; and He at least [0067] “the shielding layer 42 is electrically connected to the power supply voltage signal line 19”).
As to claim 19, the combination of Gu and He teach the display device according to claim 16 (see above rejection), wherein a ratio of the spacing between the side of the first shielding portion close to the first gate and the side of the first gate close to the first shielding portion and the spacing between the side of the first shielding portion close to the first fan-out sub-section and the side of the first fan-out sub-section close to the first shielding portion is greater than 1; and the ratio of the spacing between the side of the first shielding portion close to the first gate and the side of the first gate close to the first shielding portion and the spacing between the side of the first shielding portion close to the first fan-out sub-section and the side of the first fan-out sub-section close to the first shielding portion is less than or equal to 5.5 (see Gu at least [0057] “the magnitude of the coupling capacitance depends on the distance between the electrodes.”; and He at least [0038], [0065] “embodiments of this application can reduce the parasitic capacitance between the fan-out trace 5 and the gate (e.g., the first gate 28 and the second gate 30) of the driving thin film transistor 23 in the sub-pixel area 22,)”). Selection of a ratio greater than 1 and less than/equal to 5.5 constitutes routine layout optimization within known TFT lithographic constraints. No unexpected result is alleged.
As to claim 20, the combination of Gu and He teach the display device according to claim 19 (see above rejection), wherein the spacing between the side of the first shielding portion close to the first gate and the side of the first gate close to the first shielding portion is greater than or equal to 300 nm, and the spacing between the side of the first shielding portion close to the first gate and the side of the first gate close to the first shielding portion is less than or equal to 1100 nm; and the spacing between the side of the first shielding portion close to the first fan-out sub-section and the side of the first fan-out sub-section close to the first shielding portion is greater than or equal to 200 nm, and the spacing between the side of the first shielding portion close to the first fan-out sub-section and the side of the first fan-out sub-section close to the first shielding portion is less than or equal to 800 nm (see Gu at least [0057] “the magnitude of the coupling capacitance depends on the distance between the electrodes.”; and He at least [0038], [0065] “embodiments of this application can reduce the parasitic capacitance between the fan-out trace 5 and the gate (e.g., the first gate 28 and the second gate 30) of the driving thin film transistor 23 in the sub-pixel area 22,)”). Selection of specific nanometer ranges, constitutes routine layout optimization within known TFT lithographic constraints. No unexpected result is alleged. Numeric optimization within typical sub-micron TFT process ranges is a matter of routine engineering design.
Allowable Subject Matter
Claims 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: None of the prior art of record teach:
“A display panel comprising a display area, the display panel comprising: a substrate; a thin film transistor layer located on one side of the substrate and comprising first thin film transistors located in the display area and fan-out traces located in the display area; wherein each first thin film transistor comprises a first gate; each fan-out trace comprises a first fan-out sub-section located on one side of the first gate away from the substrate, an orthographic projection of the first fan-out sub-section on the substrate and an orthographic projection of the first gate on the substrate have a first overlapping portion; the thin film transistor layer further comprises a first conductor layer located between the first gate and the first fan-out sub-section, each first thin film transistor further comprises a first shielding portion located in the first conductor layer, an orthographic projection of the first shielding portion on the substrate at least partially overlaps the first overlapping portion; and wherein a spacing between one side of the first shielding portion close to the first gate and one side of the first gate close to the first shielding portion is greater than a spacing between one side of the first shielding portion close to the first fan-out sub-section and one side of the first fan-out sub-section close to the first shielding portion,
wherein the thin film transistor layer comprises a first-type thin film transistor, a second-type thin film transistor, a third-type thin film transistor, a fourth-type thin film transistor, a fifth-type thin film transistor, a sixth-type thin film transistor, a seventh-type thin film transistor, and an eighth-type thin film transistor located in the display area; a source and a drain of the first-type thin film transistor are electrically connected between a second node and a third node, and a gate of the first-type thin film transistor is electrically connected to a first node; one of a source and a drain of the second-type thin film transistor is electrically connected to the second node, the other of the source and the drain of the second-type thin film transistor receives a data signal, and a gate of the second-type thin film transistor receives a first scan signal; a source and a drain of the third-type thin film transistor are electrically connected between the first node and the third node, and a gate of the third-type thin film transistor receives a second scan signal; one of a source and a drain of the fourth-type thin film transistor is electrically connected to the first node, the other of the source and the drain of the fourth-type thin film transistor receives a first reset signal, and a gate of the fourth-type thin film transistor receives a third scan signal; a source and a drain of the fifth-type thin film transistor are electrically connected between a first power supply terminal and the second node, and a gate of the fifth-type thin film transistor receives a light-emitting control signal; a source and a drain of the sixth-type thin film transistor are electrically connected between the third node and a light-emitting device, and a gate of the sixth-type thin film transistor receives the light-emitting control signal; one of a source and a drain of the seventh-type thin film transistor is electrically connected to the light-emitting device, the other of the source and the drain of the seventh-type thin film transistor receives a second reset signal, and a gate of the seventh-type thin film transistor receives a fourth scan signal; one of a source and a drain of the eighth-type thin film transistor is electrically connected to the second node, the other of the source and the drain of the eighth-type thin film transistor receives a third reset signal, and a gate of the eighth-type thin film transistor receives a fifth scan signal; and wherein at least one of the seventh-type thin film transistor or the eighth-type thin film transistor is selected from the first thin film transistors and at least one of the third-type thin film transistor or the fourth-type of thin film transistor is selected from the second thin film transistors.”
Conclusion
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/JENNIFER L ZUBAJLO/Examiner, Art Unit 2627 2/20/2026