DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
1. Applicant’s arguments, filed on 07/07/2026 with respect to the amendments of claims 1 and 8 have been fully considered.
In view of these arguments, Examiner partially agrees with applicant’s argument that both Hosoda and Matsubara do not disclose the upstream switch, the load, and the downstream switch are disposed on a same single current path such that all current supplied to the load flows serially through the upstream switch, the load, and the downstream switch.
Applicant further argued that Hosoda Masubara failed to disclose a processing unit configured to execute processing, wherein the processing unit gives an instruction to switch ON or OFF a first switch that is either one of the upstream switch and the downstream switch, the processing unit determines whether or not current is flowing through the first switch while an instruction to switch OFF the first switch has been given, and in a case of determining that current is flowing through the first switch, the processing unit gives an instruction to switch OFF a second switch that is another one of the upstream switch and the downstream switch.
Examiner respectfully disagrees with the argument.
Hosoda does teach the processing unit (4, 8) gives an instruction to switch ON or OFF a first switch (such as a first switch 11b) that is either one of the upstream switch (13a) and the downstream switch (13b) (see step 22), the processing unit (4, 8) determines whether or not current is flowing through the first switch 11b while an instruction to switch OFF the first switch has been given (the current continues to flow due to a short circuit failure while an instruction to switch off, see par. 0042), and in a case of determining that current is flowing through the first switch (11b), the processing unit gives an instruction to switch OFF a second switch (11a) that is another one of the upstream switch and the downstream switch (see par. 0050, and step 26).
Matsubara discloses the processing unit (10, 20, 30) gives an instruction to switch ON or OFF a first switch (such as an upper arm switch 110 is instructed to be in OFF mode, see par. 0044, 0048) that either one of the upstream switch (110) an the downstream switch (120), the processing unit (10, 20, 30) determines whether or not current is flowing through the first switch (the upper arm switch 110) while an instruction to switch OFF the first switch has been given (the current continues to flow through the upper arm switch 110 due to a short circuit failure while an instruction to switch off, see par. 0037, 0067), and in a case of determining that current is flowing through the first switch ( the short circuit failure of the upper arm switch 110), the processing unit(10, 20, 30) gives an instruction to switch OFF a second switch (the lower arm switch 120 turned off by the instructed signal E when the short circuit failure occurs in the upper arm switch 110 ) that is another one of the upstream switch and the downstream switch (see par. 0063, 0065, 0067).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1, 3, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Hosoda et al (USPN 2010/0036555) in view of Bader (USPN 2021/0344337).
Regarding claim 1, Hosoda discloses a power supply control device (a power control device shown in figure 1) that controls a supply of power to a load (a load 1u), comprising:
an upstream switch (an upper arm switch 13a of U phase) configured to be arranged upstream of the load in a current path of a flow of current through the load;
a downstream switch (a lower arm switch 13b of U phase) configured to be arranged downstream of the load in the current path; and
a processing unit (a control unit 8, and a ECU 4) configured to execute processing (such as execute processing shown in figure 8, par. 0047),
the processing unit (4, 8) gives an instruction to switch ON or OFF a first switch (such as a first switch 11b) that is either one of the upstream switch (13a) and the downstream switch (13b) (see step 22), the processing unit (4, 8) determines whether or not current is flowing through the first switch 11b while an instruction to switch OFF the first switch has been given (the current continues to flow due to a short circuit failure while an instruction to switch off, see par. 0042), and
in a case of determining that current is flowing through the first switch (11b), the processing unit gives an instruction to switch OFF a second switch (11a) that is another one of the upstream switch and the downstream switch (see par. 0050, and step 26), and
Hosoda further discloses the upstream switch (13a) and the downstream switch (13b) are serially connected, but does not explicitly disclose the upstream switch, the load, and the downstream switch as claimed.
Bader discloses a short circuit protection device (see figure 3) comprises an upstream switch (Q2), a load (a load Z), and a downstream switch (Q1) are disposed on a same single current path (a path 12-11) such that all current supplied to the load (the load Z) flows serially through the upstream switch (Q2), the load (z) and the downstream switch (Q1).
It have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified the upstream switch and the downstream switch of Hosoda to incorporate an upstream switch and a downstream switch as disclosed by Bader in order to improve a voltage handling, and optimize current distribution, therefore, increasing reliability of operation of the circuit.
Regarding claim 3, wherein the processing unit (the control unit 8) gives an instruction to switch ON or OFF the upstream switch (such as the switch 13a is turned off, see step 21), the processing unit determines whether or not current is flowing through the upstream switch while an instruction to switch OFF the upstream switch has been given (due to the short circuit failure of the switch 13a, the current continues to flow, see par. 0042), and in a case of determining that current is flowing through the upstream switch, the processing unit gives an instruction to switch OFF the downstream switch (the switch 13b, see step 31 in figure 8).
Regarding claim 8, Hosoda discloses a power supply control method (see figures 1, 8) of controlling a supply of power to a load (such as a load 1U), the power supply control method causing a computer to execute the steps of:
giving an instruction to switch ON or OFF a first switch (such as a first switch 11b is turned OFF, step 21 in figure 8) that is either one of an upstream switch (an upper arm switch 13a) arranged upstream of the load (1U) in a current path of a flow of current through the load and a downstream switch (a lower arm switch 13b) arranged downstream of the load in the current path;
determining whether or not current is flowing through the first switch 11b while an instruction to switch OFF the first switch has been given (the current continues to flow due to a short circuit failure while an instruction to switch off, see par. 0042), and
giving an instruction to switch OFF a second switch (11a) that is another one of the upstream switch (13a) and the downstream switch (13b) in a case where a determination was made that current is flowing through the first switch (the current continues to flow due to a short circuit failure of the first switch 11b while an instruction to switch off, a second switch 11a turned off, see par. 0042, 0050, and step 26 of figure 8).
Hosoda does not explicitly disclose the upstream switch, the load, and the downstream switch as claimed.
Bader discloses a short circuit protection device (see figure 3) comprises an upstream switch (Q2), a load (a load Z), and a downstream switch (Q1) are disposed on a same single current path (a path 12-11) such that all current supplied to the load (the load Z) flows serially through the upstream switch (Q2), the load (z) and the downstream switch (Q1).
It have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified the upstream switch and the downstream switch of Hosoda to incorporate an upstream switch and a downstream switch as disclosed by Bader in order to improve a voltage handling, and optimize current distribution, therefore, increasing reliability of operation of the circuit.
3. Claims 1, 3, 4 are rejected under 35 U.S.C. 103 as being unpatentable over
Masubara et al (USPN 2022/0268854) in view of Bader (USPN 2021/0344337).
Regarding claim 1, Masubara discloses a power supply control device (a power control device 100 shown in figure 1) that controls a supply of power to a load (a load z), comprising:
an upstream switch (an upper arm switch 110) configured to be arranged upstream of the load in a current path of a flow of current through the load;
a downstream switch (a lower arm switch 120) configured to be arranged downstream of the load in the current path; and
a processing unit (a control device includes 10, 20, 30) configured to execute processing (such as controlling the switches 110, 120),
wherein the processing unit (10, 20, 30) gives an instruction to switch ON or OFF a first switch (such as an upper arm switch 110 is instructed to be in OFF mode, see par. 0044, 0048) that either one of the upstream switch (110) an the downstream switch (120), the processing unit (10, 20, 30) determines whether or not current is flowing through the first switch (the upper arm switch 110) while an instruction to switch OFF the first switch has been given (the current continues to flow through the upper arm switch 110 due to a short circuit failure while an instruction to switch off, see par. 0037, 0067), and
in a case of determining that current is flowing through the first switch ( the short circuit failure of the upper arm switch 110), the processing unit(10, 20, 30) gives an instruction to switch OFF a second switch (the lower arm switch 120 turned off by the instructed signal E when the short circuit failure occurs in the upper arm switch 110 ) that is another one of the upstream switch and the downstream switch (see par. 0063, 0065, 0067).
Matsubara does not explicitly disclose the upstream switch, the load, and the downstream switch as claimed.
Bader discloses a short circuit protection device (see figure 3) comprises an upstream switch (Q2), a load (a load Z), and a downstream switch (Q1) are disposed on a same single current path (a path 12-11) such that all current supplied to the load (the load Z) flows serially through the upstream switch (Q2), the load (z) and the downstream switch (Q1).
It have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified the upstream switch and the downstream switch of Matsubara to incorporate an upstream switch and a downstream switch as disclosed by Bader in order to improve a voltage handling, and optimize current distribution, therefore, increasing reliability of operation of the circuit.
Regarding claim 3, Masubara wherein the processing unit (the control device 10, 20, 30) gives an instruction to switch ON or OFF the upstream switch (see par. 0060), the processing unit determines whether or not current is flowing
through the upstream switch (110) while an instruction to switch OFF the upstream switch has been given (erroneous turning on occurs in the upper arm switch 110 which causes the short circuit failure of the upper switch 110, and results the current continues to flow, see par. 0037, 0067), and in a case of determining that current is flowing through the upstream switch (the current flows through the upper switch 110 is determined by a current sensor 40 during the short circuit failure of the upper switch 110), the processing unit (10, 20, 30) gives an instruction to switch OFF the downstream switch (the lower switch 120, see par. 0065, 0067).
Regarding claim 4, Masubara discloses wherein the processing unit (10, 20, 30) acquires a voltage value of a downstream end of the upstream switch while the instruction to switch OFF the upstream switch has been given (a voltage detector 31), and in a case where the acquired voltage value is greater than or equal to a voltage threshold value (a second threshold V0), the processing unit determines that current is flowing through the upstream switch (see par. 0071).
4. Claims 2, 9 are rejected under 35 U.S.C. 103 as being unpatentable over Hosoda et al (USPN 2010/0036555) in view of Bader (USPN 2021/0344337), and further in view of Inada et al (USPN 2024/0204710).
Regarding claim 2, Hosoda discloses wherein the current path is a path of current output from a contactor (5), the processing unit (a control unit 4, 8) receives a supply of power from a connection node (3a) between the contactor and the upstream switch (13a), and the processing unit executes transmission processing for transmitting data to an external device (an external device 4).
Hosoda does not explicitly disclose a fuse as claimed.
Inada discloses a short circuit failure protection for a power device (see figure 3) comprises a current path (from an upper arm to a lower arm) is a path of current output from a fuse (a fuse 60).
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to have modified the contactor switch of Hosoda to incorporate a fuse as disclosed by Kawano in order to provide an overcurrent protection so that protecting circuits from damage due to excessive current flow.
Regarding claim 9, Hosoda discloses wherein the processing unit (the control unit 8) gives an instruction to switch ON or OFF the upstream switch (a switch 11a of the upper arm switch 13a is turned on), the processing unit (8) determines whether or not current is flowing through the upstream switch (13a) while an instruction to switch OFF the upstream switch has been (when a short circuit occurs at the upper switch 13a, see step 21 of figure 8) and in a case of determining that current is flowing through the upstream switch, the processing unit gives an instruction to switch OFF the downstream switch (in a case a short circuit failure of the upper arm switch 13a, a current continues to flows and determined by the control unit 8 and a downstream switch 13b is cut off, see steps 29-31 of figure 8) (see par. 0057).
Allowable Subject Matter
5. Claims 5-7, 10-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
6. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
7. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANNY NGUYEN whose telephone number is (571)272-2054. The examiner can normally be reached M-F 8:00AM-4:30PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at 571-271-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANNY NGUYEN/Primary Examiner, Art Unit 2838
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