DETAILED CORRESPONDENCE
Summary
This Office Action based on the Amendment & Response filed with the Office on 9 March 2026, with respect to the Request for Continued Examination, filed on 16 March 2026, regarding the Xu, et al. application.
Claims 1-20 are currently pending, and claims 1-14 and 20 have been fully considered. Claims 15-19 are withdrawn from consideration.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9 March 2026, has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, and 12-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by a US Patent Application Publication to President and Fellows of Harvard College (US 2017/0069858 A1; hereinafter, “Harvard”).
Regarding claim 1, Harvard discloses a method of fabricating a three-dimensional (3D) FET sensor array (“The scaffolds in this and the following examples were prepared by planar lithography with nanowire transistors serving as sensor elements and metal interconnects sandwiched between biocompatible polymeric scaffold networks.”, [0140]; “… forming 3D NWFETs matrices (nanoelectric scaffolds) by self- or manual organization and hybridization with synthetic biomaterials …”, [0142]), comprising:
fabricating a two-dimensional (2D) precursor field-effect transistor (FET) sensor array having a plurality of nanoscale or microscale FETs using microfabrication techniques (“The present example, in contrast, demonstrates an integrated system from the discrete building blocks of electronic and biological systems, e.g., semiconductor nanowires, molecular precursors of polymers and single cells. These biomimetic and bottom-up steps are used: A) patterning, metallization and epoxy passivation to form single NWFETs …”, [0142]; shown as (2D) NWFETs in FIG.3, steps A-B]),
each of the nanoscale or microscale FETs having a kink at which a FET channel is located (“Kinked 80 nm diameter silicon nanowires, which were used for the reticular NWFET scaffolds, were synthesized with a n+(arm)-n(device)-n+(arm) dopant profile ... Kinks were introduced by evacuation of the reactor (~3x10-3 torr) for 15 s, and the silicon-phosphorus feed-in ratios were 200:1 and 10,000:1 for the n+- and n-type segments, respectively. The n+-type arms were grown for 12-15 min, and the n-type active device channel segment was grown for 30 s immediately following the evacuation step used to introduce a kink”; thus the FET channel was grown and located right after a kink was introduced in the fabrication process, [0183]); and
causing the 2D nanoscale or microscale precursor FET sensor array to buckle or fold into a third dimension “… (B) forming 3D NWFETs matrices (nanoelectric scaffolds) by self- or manual organization and hybridization with synthetic biomaterials, and C) incorporation of cells and growth of synthetic tissue via biological processes.”, [0142]; “The 3D mesh nanoES were prepared by manual folding and rolling of free-standing device arrays”, [0147]).
Regarding claim 5, Harvard discloses the method of claim 1 wherein fabricating the 2D FET structure includes patterning and doping a semiconductor material on a first substrate to define a source, drain and gate of each of the nanoscale or microscale FETs (“… the semiconductor can be undoped or doped (e.g., p-type or n-type). For example, in one set of embodiments, a nanoscale wire may be a p-type semiconductor nanoscale wire or an n-type semiconductor nanoscale wire, and can be used as a component of a transistor such as a field effect transistor ("FET"). For instance, the nanoscale wire may act as the "gate" of a source-gate-drain arrangement of a FET, while metal leads or other conductive pathways (as discussed herein) are used as the source and drain electrodes.”, [0061]; “… individual nanowire field-effect transistor (NWFET) devices were lithographically patterned and integrated into free-standing macroporous scaffolds…”, [0141]).
Regarding claim 12, Harvard discloses the method of claim 1 wherein at least two of the nanoscale or microscale FETs in the 3D FET sensor array have one or more different characteristics (“The overall size of the structure (x-y-z) was 300-400-200 micrometers. The solid and dashed open boxes indicate two NWFET devices located on different planes along x axis.”, [0149]).
Regarding claim 13, Harvard discloses the method of claim 12 wherein the one or more different characteristics includes different geometries, materials, and/or doping profiles. (“The overall size of the structure (x-y-z) was 300-400-200 micrometers. The solid and dashed open boxes indicate two NWFET devices located on different planes along x axis.” [0149]).
Regarding claim 14, Harvard discloses a 3D FET sensor array fabricated in accordance with the method of claim 1 (“The scaffolds in this and the following examples were prepared by planar lithography with nanowire transistors serving as sensor elements and metal interconnects sandwiched between biocompatible polymeric scaffold networks.”, [0140]; “… forming 3D NWFETs matrices (nanoelectric scaffolds) by self- or manual organization and hybridization with synthetic biomaterials …”, [0142]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Harvard.
Regarding claim 9, Harvard discloses the method of claim 1 wherein the nanoscale or microscale FETs each have a dimension in size (FIG. 5 shows a NWFET 3D distribution in fibrous nanos; 14 NWFETs were distributed in the construct shown in FIG. 4B; “Individual devices are shown as solid spheres. The overall size of the scaffold, x-y-z was ~300-400-200 micrometers. The NWFET devices within the scaffold were separated in 3 dimensions by 7.3 micrometers to 324 micrometers.”, [ 0145]).
Harvard fails to explicitly disclose the nanoscale or microscale FETs each have a maximum dimension that is less than 1 mm in size.
However, it has been held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (MPEP 2144.04 IV A).
Regarding claim 10, Harvard discloses the method of claim 1 wherein the nanoscale or microscale FETs each have a dimension in size (FIG. 5 shows a NWFET 3D distribution in fibrous nanos; 14 NWFETs were distributed in the construct shown in FIG. 4B; “Individual devices are shown as solid spheres. The overall size of the scaffold, x-y-z was ~300-400-200 micrometers. The NWFET devices within the scaffold were separated in 3 dimensions by 7.3 micrometers to 324 micrometers.”, [0145]).
Harvard fails to explicitly disclose the nanoscale or microscale FETs each have a maximum dimension that is less than 1 μm in size.
However, it has been held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (MPEP 2144.04 IV A).
Regarding claim 11, Harvard discloses the method of claim 1 wherein the nanoscale or microscale FETs each have a dimension in size (FIG. 5 shows a NWFET 3D distribution in fibrous nanos; 14 NWFETs were distributed in the construct shown in FIG. 4B; “Individual devices are shown as solid spheres. The overall size of the scaffold, x-y-z was -300-400-200 micrometers. The NWFET devices within the scaffold were separated in 3 dimensions by 7.3 micrometers to 324 micrometers.”, [0145]).
Harvard fails to explicitly disclose the nanoscale FETs each have a maximum dimension that is less than 100 nm in size.
However, it has been held that, where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device (MPEP 2144.04 IV A).
Claims 2, 4, 6, and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Harvard in view of a US Patent Application Publication to The Board of Trustees of the University of Illinois (US 2016/0381789 A1; hereinafter, “Illinois”).
Regarding claim 2, Harvard discloses the method of claim 1 wherein fabricating the 2D precursor FET sensor array includes: fabricating a 2D FET structure on a first substrate (“… the devices could also be made closer together (for example, less than 0.5 micrometers), e.g., by depositing the nanowires more densely on the substrate, for instance, to improve the spatial resolution of nanoelectronic sensors; the span of device separations and scaffold heights can also be increased substantially using larger field lithography.”, [0145]; FIG. 5 shows a NWFET 3D distribution in fibrous nanos; 14 NWFETs were distributed in the construct shown in FIG. 4B).
Harvard fails to explicitly disclose transferring the 2D FET structure from the first substrate to a second substrate; depositing, patterning or etching materials on the second substrate after transferring the 2D FET structure to the second substrate; and forming a plurality of additional functional layers on the second substrate to define the 2D precursor FET sensor array.
Illinois is in the field of sensors ([0141]) and teaches transferring the 2D FET structure from the first substrate to a second substrate (“… providing two-dimensional control of component relief features, thereby providing spatial control over the bendability of a device or device component.”, [0155]; “Similar to the results for uniaxial stretching of a flat substrate, this "bending" stretching is reversible. At any stage of expansion, that maximizes conformal contact with a curved surface, the array may be transferred to the curved surface by any means known in the art.”, [0179]);
depositing, patterning or etching materials on the second substrate after transferring the 2D FET structure to the second substrate; and forming a plurality of additional functional layers on the second substrate to define the 2D precursor FET sensor array (“Once cool, metal lines or contacts are deposited via electrodeposition, photolithograph and etching/lift-off, and/or evaporation through a shadowmask. Treat the metal on SU-8 with MPTMS for 1 hour and then cast elastomeric substrate against it. When removed, the PDMS has wavy surface relief with smoothed peaks and valleys along with transferred metal structures. FIG. 55 is a photograph of the a [sic] wavy stretchable electrode made by the process summarized in FIG. 54, and also provides measured electrical resistance data of the stretchable wavy metal electrodes as a function of applied tensile strain (up to 30%).”, [0164]; “Essentially every functional component of a complex electronic system can be integrated in a design-specific, mechanically compliant form using the methods taught herein.”, [0342]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the method of Harvard to include transferring the 2D FET structure from the first substrate to a second substrate; depositing, patterning or etching materials on the second substrate after transferring the 2D FET structure to the second substrate; and forming a plurality of additional functional layers on the second substrate to define the 2D precursor FET sensor array as taught by Illinois. The motivation being to provide Shape-conforming devices have a variety of applications ranging from flexible displays and electronic fabrics to conformable biological and physical sensors (Illinois, para. 0012).
Regarding claim 4, modified Harvard fails to explicitly disclose the method of claim 2 wherein the second substrate is a prestrained stretchable and flexible substrate and further comprising causing the 2D precursor sensor array to buckle or fold by releasing strain in the prestrained stretchable and flexible substrate, which compresses the 2D precursor FET sensor array to buckle or fold and thereby extend into a third dimension.
Illinois teaches the second substrate is a prestrained stretchable and flexible substrate and further comprising causing the 2D precursor sensor array to buckle or fold by releasing strain in the prestrained stretchable and flexible substrate, which compresses the 2D precursor FET sensor array to buckle or fold and thereby extend into a third dimension (“… the strain is generated by stretching an underlying elastomeric substrate to which at least a portion of the interconnect is bonded.”, [0140]; “A component in "conformal contact" with a substrate refers to a component that covers a substrate and retains a three-dimensional relief feature whose pattern is governed by the pattern of relief features on the substrate.”, [0143]; “Interconnects can have any number of geometries or shape, so long as the geometry or shape facilitates interconnect bending or stretching without breakage. A general interconnect geometry can be described as "buckled" or "wavy." In an aspect, that geometry can be obtained by exerting a force (e.g., a strain) on the interconnect by exerting a force on an underlying deformable substrate, such that a change in a dimension of the underlying substrate generates buckles or waves in the interconnect because portions of the interconnect are bonded to the substrate, and regions between the bound portions are not bonded.”, [0147]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the method of Harvard to include the second substrate is a prestrained stretchable and flexible substrate and further comprising causing the 2D precursor sensor array to buckle or fold by releasing strain in the prestrained stretchable and flexible substrate, which compresses the 2D precursor FET sensor array to buckle or fold and thereby extend into a third dimension as taught by Illinois. The motivation being to provide, “Shape-conforming devices have a variety of applications ranging from flexible displays and electronic fabrics to conformable biological and physical sensors.” (Illinois, [0012]).
Regarding claim 6, modified Harvard fails to explicitly disclose the method of claim 4 wherein the prestrained flexible and stretchable substrate is a prestrained elastomer substrate.
Illinois teaches the prestrained flexible and stretchable substrate is a prestrained elastomer substrate (“… an elastomeric substrate having a receiving surface is provided having a first level of strain, where the strain is optionally zero, compressive, or elongating. One or more device components are bonded to the receiving surface having the first level of strain. A force is applied to the elastomeric substrate so as generate a change in the level of strain from the first to a second different level of strain.”, [0033]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the method of Harvard to include the prestrained flexible and stretchable substrate is a prestrained elastomer substrate as taught by Illinois. The motivation being to provide, “Shape-conforming devices have a variety of applications ranging from flexible displays and electronic fabrics to conformable biological and physical sensors.” (Illinois, [0012]).
Regarding claim 8, modified Harvard fails to explicitly disclose the method of claim 4 wherein transferring the 2D precursor FET sensor array includes laminating the 2D precursor FET sensor array onto the prestrained stretchable and flexible substrate so that the 2D precursor FET sensor array is bonded to the prestrained stretchable and flexible substrate at bonding sites defined by one or more exposed portions of the mechanical supporting layer.
Illinois teaches transferring the 2D precursor FET sensor array includes laminating the 2D precursor FET sensor array onto the prestrained stretchable and flexible substrate so that the 2D precursor FET sensor array is bonded to the prestrained stretchable and flexible substrate at bonding sites defined by one or more exposed portions of the mechanical supporting layer (“Laminating the processed SOI or GaAs wafers against a UVO treated, pre-stretched PDMS substrate (ribbons oriented parallel to the direction of prestrain), baking in an oven at 90° C. for minutes, and removing the wafer transferred all of the ribbons to the surface of the PDMS (step iv). Heating facilitates conformal contact and the formation of strong siloxane bonds (i.e., --O—Si—O--) between the native SiO2 layer on the Si ribbons or the deposited SiO2 layer on the GaAs ribbons and the activated areas of the PDMS … Relaxing the strain in the PDMS generates buckles through the physical separation of the ribbons from the inactivated regions of the PDMS (step v). The ribbons remain tethered to the PDMS in the activated regions due to the strong chemical bonding. The resulting 3D ribbon geometries (i.e. the spatially varying pattern of buckles) depend on the magnitude of prestrain and the patterns of surface activation (e.g., shape and dimensions of Win and Wact).”, [0184]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the method of Harvard to include transferring the 2D precursor FET sensor array includes laminating the 2D precursor FET sensor array onto the prestrained stretchable and flexible substrate so that the 2D precursor FET sensor array is bonded to the prestrained stretchable and flexible substrate at bonding sites defined by one or more exposed portions of the mechanical supporting layer as taught by University of Illinois. The motivation being to provide, “Shape-conforming devices have a variety of applications ranging from flexible displays and electronic fabrics to conformable biological and physical sensors.” (Illinois, [0012]).
Claims 3 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Harvard in view of Illinois as applied to claims 1 and 2 above, and further in view of a US Patent Application Publication to Trusov (US 2012/0032286 A1; hereinafter, “Trusov”).
Regarding claim 3, modified Harvard fails to explicitly disclose the method of claim 2 wherein the additional functional layers include at least one metallization layer in which electrical interconnects are defined and at least one mechanical supporting layer in which a plurality of hinge locations are defined at which the 2D precursor FET sensor array is able to buckle or fold.
Illinois teaches the additional functional layers include at least one metallization layer in which electrical interconnects are defined and at least one mechanical supporting layer in which a plurality of locations are defined at which the 2D precursor FET sensor array is able to buckle or fold (“… the invention relates to various methods for making a buckled component or interconnect capable of establishing electrical contact with device components. In an aspect, a pattern of bond sites is applied to an elastomeric substrate surface, the components or interconnects, or to both. A force is exerted to strain the substrate and the components or interconnects contacted with the substrate. The pattern of bond sites provides bonding between specific components or interconnect locations and the substrate. Upon relaxation of the substrate (by removal of the force), buckled components or interconnects are generated. Varying one or more of the magnitude of prestrain, bond site patterning, geometry and spacing generates components or interconnects with different buckled or wavy geometry.”, [0041]; “The metal feature 10 is retrieved with a compliant elastomer stamp 30. Subsequent deformation of the stamp 30 generates in the metal feature 10 a wavy or buckled geometry 40. Generation of the buckles is provided by stamp 30 that is under strain when the metal feature 10 is retrieved and subsequently releasing the applied tension, or by compressing stamp 30 after the metal feature is retrieved.”, [0160]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the method of Harvard to include the additional functional layers include at least one metallization layer in which electrical interconnects are defined and at least one mechanical supporting layer in which a plurality of locations are defined at which the 2D precursor FET sensor array is able to buckle or fold as taught by Illinois. The motivation being to provide “Shape-conforming devices have a variety of applications ranging from flexible displays and electronic fabrics to conformable biological and physical sensors.” (Illinois, [0012]).
Further, Trusov is in the field of sensors ([0010]) and teaches a plurality of hinge locations (Flexible polymer hinges connecting faces of the folded structures are defined on the same substrate and incorporate electrical interconnects, para. 0014).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the method of Harvard to include a plurality of hinge locations as taught by Trusov. The motivation being to connect faces of the folded structures are defined on the same substrate and incorporate electrical interconnects (Trusov, para. 0014).
Regarding claim 7, modified Harvard fails to explicitly disclose the method of claim 3 wherein defining the hinge locations includes removing the mechanical supporting layer at the hinge locations.
Trusov teaches defining the hinge locations includes removing the mechanical supporting layer at the hinge locations (“To remove the folded structures from the manufactured wafer 16, etching is done from the backside through the glass 7 4 and silicon layers 84. Once the flexible hinge material 86 is reached, the devices are removed from the manufactured wafer 16 as shown in FIG. 10e.”, [0081]).
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the method of Harvard to include defining the hinge locations includes removing the mechanical supporting layer at the hinge locations as taught by Trusov. The motivation being to connect faces of the folded structures are defined on the same substrate and incorporate electrical interconnects (Trusov, [0014]).
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The Harvard reference is considered to the closest prior art to instant claim 20. However, Harvard does not anticipate or render obvious coating a surface of the cell-penetrating three-dimensional FET sensor array with a bilayer of parylene and a hydrophobic surface layer of SiO2.
Interview with the Examiner
If at any point during the prosecution it is believe an interview with the Examiner would further the prosecution of an application, please consider this option.
The Automated Interview Request form (AIR) is available to request an interview to be scheduled with the Examiner. First, an authorization for internet communications regarding the case should be filed prior or with an AIR online request.
The internet communication authorization form (SB/0439), which authorizes or withdraws authorization for internet-based communication (e.g., video conferencing, email, etc.) for the application must be signed by the applicant or the attorney/agent for applicant. The form can be found at:
https://www.uspto.gov/sites/default/files/documents/sb0439.pdf
The AIR form can be filled out online, and is automatically forwarded to the Examiner, who will call to confirm a requested time and date, or set up a mutually convenient time for the interview. The form can be found at:
https://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html
The Examiner encourages, but does not require, interviews by the USPTO Microsoft Teams video conferencing. This system allows for file-sharing along audio conferencing. Microsoft Teams can be used as an internet browser add-on in Microsoft IE, Google Chrome, or Mozilla Foxfire, or as a temporary Java-based application on these browsers. Steps for joining an Examiner setup Microsoft Teams can be found at the USPTO website:
https://www.uspto.gov/patents/laws/interview-practice#step3
Additionally, a blank email to the Examiner at the time of a telephonic interview can be used for a reply to easily allow for Microsoft Teams communication. Please note, policy guidelines regarding Internet communications are detailed at MPEP §500-502.3, and office policy regarding interviews are detailed at MPEP §713.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN C BALL whose telephone number is (571)270-5119. The examiner can normally be reached M - F, 9 am - 5:30 pm.
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/J. Christopher Ball/ Primary Examiner, Art Unit 1795