Prosecution Insights
Last updated: July 17, 2026
Application No. 18/566,621

NON-CLIFFORD QUANTUM GATES

Non-Final OA §101§103
Filed
Dec 01, 2023
Priority
Jun 04, 2021 — AU 2021901663 +1 more
Examiner
ALSHACK, OSMAN M
Art Unit
Tech Center
Assignee
UNIVERSITY OF TECHNOLOGY SYDNEY
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
453 granted / 525 resolved
+26.3% vs TC avg
Moderate +14% lift
Without
With
+14.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
34 currently pending
Career history
557
Total Applications
across all art units

Statute-Specific Performance

§101
8.4%
-31.6% vs TC avg
§103
74.2%
+34.2% vs TC avg
§102
4.2%
-35.8% vs TC avg
§112
6.3%
-33.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 525 resolved cases

Office Action

§101 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of Claims 2. Claims 1-17 are presented for examination. Abstract 3. The abstract of the disclosure is acceptable for examination purposes. Oath Declaration 4. The Oath complies with all the requirements set forth in MPEP 602 and therefore is accepted. Priority 5. Acknowledgment is made of applicant's claim for foreign priority under 35 U.S.C.119 (a)-(d) for Australian Patent Application No. AU2021901663, filed on Jun. 04, 2021. Information Disclosure Statement 6. The references listed in the information disclosure statement (IDS) submitted on 12/01/2023 & 08/27/2024 have been considered. The submission complies with the provisions of 37 CFR 1.97. Form PTO- 1449 is signed and attached hereto. Specification 7. The specification is objected to because: - Paragraph [0045] of the specification states that “--- an odd number of bi flip errors in the data qubits, there will be an odd number of flips of the ancilla qubit---.” The Examiner believes that the applicant inadvertently made a typographical error by using the word "bi" instead of "bit". Therefore, the Examiner respectfully request correction if the applicant believes is in error. Appropriate correction is required. - Paragraph [0064] of the specification states that “---the exact non-Clifford gate can be calculated as described below. More particularly, the non-Clifford that that is applied to the physical qubits can be calculated based on the distance of the error correction code and based on the desired quantum gate at the logical level, such as a logical T gate. The Examiner believes that the applicant inadvertently made a typographical error by recited the word “that” twice consecutively. Appropriate correction is required. - Paragraph [0065] of the specification states that “---the next step of method 300 as evaluating 301 the stabilizer quantum error correction code to realise a desired quantum logic function and suppress quantum errors---.” The evaluating 301 step needs to be corrected to evaluating 302 instead of 301 since the step 301 has been described for the initialising physical states 301. See Fig. 3. Drawings 8. The drawings are objected to because: The two steps of Fig. 3 were labeled “301”. Therefore, the evaluating 301 the stabilizer quantum error correction code needs to be label “302.” Appropriate correction is required. PNG media_image1.png 213 554 media_image1.png Greyscale Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 101 35 U.S.C. 101 reads as follows: Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title. 9. Claims 1-17 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. As per claim 1: The claim recites “A method for processing encoded quantum information in a quantum computer using a stabilizer quantum error correction code, the method comprising: initialising physical states of physical data qubits in a logical block of the stabilizer quantum error correction code by applying a physical non-Clifford gate to each of the physical data qubits, to define an encoded quantum state encoded by the physical data qubits in the logical block; and evaluating the stabilizer quantum error correction code to realise a desired quantum logic function and suppress quantum errors, wherein evaluating the stabilizer quantum error correction code comprises consuming the encoded quantum state, resulted from applying the physical non-Clifford gate to each of the physical data qubits, to realise a logical non-Clifford gate on the encoded quantum information.” At step 2A prong 1: The claim recites the following limitations directed to an abstract idea “evaluating the stabilizer quantum error correction code to realise a desired quantum logic function and suppress quantum errors, wherein evaluating the stabilizer quantum error correction code comprises consuming the encoded quantum state, resulted from applying the physical non-Clifford gate to each of the physical data qubits, to realise a logical non-Clifford gate on the encoded quantum information,” as drafted, is a process that, under the broadest reasonable interpretation , covers a mathematical relationship of the mathematical concept grouping. The terms of the claims are presumed to have their plain meaning consistent with the specification as it would be interpreted by one of ordinary skill in the art. Thus, if a claim limitation, under its broadest reasonable interpretation, covers mathematical concepts, then it falls into the mathematical relationship as part of the mathematical grouping of abstract idea. Accordingly, the claim recites an abstract idea. At Step 2A, Prong Two: This judicial exception is not integrated into a practical application because the additional limitations of “initialising physical states of physical data qubits in a logical block of the stabilizer quantum error correction code by applying a physical non-Clifford gate to each of the physical data qubits, to define an encoded quantum state encoded by the physical data qubits in the logical block” do not integrate the abstract idea into a practical application because is a generic computer function of data initialising. These extra-solution activities do not provide practical application. At step 2B: The additional elements of “processing encoded quantum information in a quantum computer using a stabilizer quantum error correction code” is generic component that are well understood, routine and conventional used as a tool to perform the processes and do not result in the claim as a whole amounting to significantly more than the abstract idea. In Berkheimer v. HP, Inc., 881 F.3d 1360, 125 USPQ2d 1649 (Fed. Cir. 2018), in which the patentee claimed methods for parsing and evaluating data using a computer processing system. See CHAMBERLAND, C. et al., 'Building a fault-tolerant quantum computer using concatenated cat codes', arXiv:2012.04108v1,7 December 2020; and US 20200334107 A1 by Katabarwa. Therefore, the claim is not patent eligible. In regards to claims 16 and 17, the claims recite similar feature of claim 1 and are also rejected for the same rationale applied to claim 1. Dependent claims 2-15 fail to remedy the exception by integrating it into a practical application or adding elements that amount to significantly more than the exception – the process steps all still comprise mathematical concepts. Accordingly, for the reasons provided above, claims 1-17 are directed to an abstract idea, hence, not patent eligible under 35 USC 101. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 10. Claims 1-17 are rejected under 35 U.S.C. 103 (a) as being unpatentable over CHAMBERLAND, C. et al., 'Building a fault-tolerant quantum computer using concatenated cat codes', arXiv:2012.04108v1,7 December 2020 “here after as Christopher” in view of Narayanan Rengaswamy, Classical Coding Approaches to Quantum Applications. Duke University. 2020 April. 6 Pages. arXiv:2004.06834 “herein after as Rengaswamy.” As per claims 1 and 16: Christopher substantially teaches or discloses a method for processing encoded quantum information in a quantum computer using a stabilizer quantum error correction code, the method comprising (see abstract, Section 1, subsection A, 2nd paragraph): initialising physical states of physical data qubits in a logical block of the stabilizer quantum error correction code by applying a physical non-Clifford gate to each of the physical data qubits, to define an encoded quantum state encoded by the physical data qubits in the logical block (see section IV, subsection A, 3rd paragraph, to simulate universal quantum computation with Toffoli [i.e. non-Clifford] gates, "we introduce in Section VI a new protocol to fault-tolerantly prepare TOF magic states encoded in the repetition code. Due to the fault-tolerant properties of our protocol, all gates required in our circuits can be implemented at the physical level. Hence we refer to such an approach as a bottom-up approach for preparing TOF magic states. The main insight is that a TOF state can be prepared by measuring a single Clifford observable, which can be achieved using a sequence of physical CNOT and TOF gates.", sec Section 1, subsection A, 14th para (page 4, last para page 5, 1st para); Toffoli gates acting on cat qubits [i.e. initialising physical states of physical data qubits], see Section III, 1st para; "Prior to the application of these non-Clifford gates, errors on the encoded code- blocks need to be corrected without having access to a round of perfect syndrome measurements (since the data qubits cannot be measured directly prior to applying the non-Clifford gates). Hence, it is important to have a decoder which is robust to measurement errors occurring in the last round when rounds of perfect syndrome measurements cannot effectively be applied in the hardware); and evaluating the stabilizer quantum error correction code to realise a desired quantum logic function and suppress quantum errors (see page 29, section VI, A measurement error on the ancilla results in a logical ZA failure and so the measurement of gA needs to be re peated (similar repetitions are needed for the preparation of logical computational basis states, see Appendix I); and magic state injection is performed using the circuit in Fig. 13 to realize a logical Toffoli gate, see Section V, 4th para; Section VI, 1st-4th paras, fig. 13), wherein evaluating the stabilizer quantum error correction code comprises consuming the encoded quantum state, resulted from applying the physical non-Clifford gate to each of the physical data qubits (see pages 83, left column, herein When performing physical non-Clifford operations in between rounds of error correction (EC), in order to maintain the full effective code distance, it is crucial to use a fault-tolerant error correction protocol which satisfies the following definition (taken from [101, 102]); and page 84, right column, herein apart from being useful for proving thresholds of fault tolerant error correction schemes based on code concatenation [103], such a definition of fault-tolerant error correction is also relevant when performing physical non-Clifford operations on encoded qubits before directly measuring the data qubits). Christopher does not explicitly teach realise a logical non-Clifford gate on the encoded quantum information. However, Rengaswamy in the same the field of endeavor teaches realise a logical non-Clifford gate on the encoded quantum information (see section 6.1 on page 133, herein for realizing a logical non-Clifford gate on a stabilizer code we need to implement a physical non-Clifford gate). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the quantum computing system of Christopher with the teachings of Rengaswamy by realising a logical non-Clifford gate on the encoded quantum information. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the realising a logical non-Clifford gate on the encoded quantum information would have improved the quality of solutions produced by the algorithm (see page 131 of Rengaswamy). As per claim 2: Christopher teaches that wherein the physical states for initialising the physical data qubits in the logical block are identical (see page 34, right column, herein states encoded in repetition codes) As per claim 3: Christopher teaches that wherein the method further comprises determining the physical states based on a desired logical non-Clifford gate on the encoded quantum information (see abstract, pages 22, the data qubits are measured directly as part of the quantum algorithm or During the implementation of state injection for performing non-Clifford gates (see Refs. [60–62] andFig.43), and section VI, 1st-4th paras). As per claim 4: Christopher teaches that wherein determining the physical states comprises solving one or more equations for two factors that define a superposition of two respective ground states of the physical data qubits (see section 2, Lemma 1; consider its action on each term in the superposition using Eq. (N10)). As per claim 5: Christopher teaches that wherein the one or more equations are based on a code distance of the stabilizer quantum error correction code (see section 2, Lemma 1; and section V11 last para, using a square surface code distance d, the factory requires 12d _ 6d qubits and takes 5:5d surface code cycles). As per claim 6: Christopher teaches that wherein the method further comprises determining the encoded quantum state based on the physical non-Clifford gate applied to each of the physical data qubits (see abstract, page 83, right column, herein when performing physical non-Clifford operations in between rounds of error correction (EC), in order to maintain the full effective code distance, it is crucial to use a fault-tolerant error correction protocol which satisfies the following definition (taken from [101, 102]) , and Section VI, 1st-4th paragraphs). As per claim 7: Christopher teaches that wherein determining the encoded quantum state comprises analytically calculating the encoded quantum state as a function of the physical non-Clifford gate (see abstract, page 84, left column, Apart from being useful for proving thresholds of fault tolerant error correction schemes based on code concatenation[103], such a definition of fault-tolerant error correction is also relevant when performing physical non-Clifford operations on encoded qubits before directly measuring the data qubits , and Section VI, 1st-4th paragraphs). As per claim 8: Christopher teaches that extracting syndrome information by measuring multiple physical ancilla qubits to suppress the quantum errors (see page 8 in fig. 2 Hardware implementation of the repetition- and surface-cat codes. In the 2D grid on the right, yellow circles represent data qubits where the logical information is encoded, and gray circles represent ancilla qubits which are used to measure the stabilizers and extract error syndromes. Both data and ancilla qubits are encoded as Schrodinger cat states of localized acoustic modes of phononic-crystal-defect resonators (PCDRs), and are stabilized through a driven-dissipative two-phonon interaction with an engineered reservoir; Section VI, 1st-4th paragraphs). As per claim 9: Christopher teaches that wherein the logical non-Clifford gate on the encoded quantum information is a T gate (see page 33, right column We use the Trotterization scheme and analysis of Ref. [80] to count the required Toffoli and T gates. Using catalysis, 1 TOF state can perform 2 T-gates, and VIII, 2nd paragraph). As per claim 10: Christopher teaches that wherein the logical non-Clifford gate together with one or more logical Clifford gates, form a universal gate set for universal error-corrected computation (see page 27, herein all these operations are either Clifford group gates or Pauli measurements, so some non-Clifford operation is required to complete a universal gate set). As per claim 11: Christopher teaches that wherein the number of data qubits is identical to the number of data qubits required to realise logical Clifford gates (see section VI, 1st - 5th paragraphs, both CNOT and Toffoli gates utilize a repetition code with the same distance d [implying identical number of data qubits). As per claim 12: Christopher teaches that wherein the stabilizer quantum error correction code comprises a surface code (see abstract, page 24, right column throughout this paper, we use the surface code with only a fixed number of error correction round, and section IV, 1st paragraph, The two codes that we use in our architecture for implementing quantum algorithms are the repetition code and the rotated surface code [59]). As per claim 13: Christopher teaches that wherein realising the logical non-Clifford gate comprises using the encoded quantum information and the encoded quantum state as respective inputs to a Clifford gate (see abstract, Section VI, 1st paragraph, in magic state distillation schemes, the goal is to distill magic states with circuits that require only stabilizer operations [30, 31, 33]. The circuits used to distill such magic states are typically not fault-tolerant to all Clifford gate errors and thus must be implemented using a sufficiently large error-correcting code). As per claim 14: Christopher teaches that wherein the Clifford gate is a CNOT gate (see abstract, Section VI, 1st-4th paragraphs). As per claim 15: Christopher teaches that wherein one or both of the physical non-Clifford gate and the logical non-Clifford gate is a rotated gate (see section III, 1st paragraph). As per claim 17: Christopher substantially teaches or discloses a quantum processor comprising: multiple physical data qubits operable in a stabilizer quantum error correction code (see abstract, page 57, right column In Fig. 25 we show how these stabilization constraints can be satisfied. In the top panel of the figure, we show four (out of six, state preparation and measurement not show) time steps of the surface-code stabilizer measurement) a first quantum circuit configured to operate on the multiple physical data qubits and comprising a physical non-Clifford gate to initialise physical states of the multiple physical data qubits in a logical block of the stabilizer quantum error correction code, to define an encoded quantum state encoded by the physical data qubits in the logical block (see section IV, subsection A, 3rd paragraph, to simulate universal quantum computation with Toffoli [i.e. non-Clifford] gates, "we introduce in Section VI a new protocol to fault-tolerantly prepare TOF magic states encoded in the repetition code. Due to the fault-tolerant properties of our protocol, all gates required in our circuits can be implemented at the physical level. Hence we refer to such an approach as a bottom-up approach for preparing TOF magic states. The main insight is that a TOF state can be prepared by measuring a single Clifford observable, which can be achieved using a sequence of physical CNOT and TOF gates.", sec Section 1, subsection A, 14th para (page 4, last para page 5, 1st para); Toffoli gates acting on cat qubits [i.e. initialising physical states of physical data qubits], see Section III, 1st para; "Prior to the application of these non-Clifford gates, errors on the encoded code- blocks need to be corrected without having access to a round of perfect syndrome measurements (since the data qubits cannot be measured directly prior to applying the non-Clifford gates). Hence, it is important to have a decoder which is robust to measurement errors occurring in the last round when rounds of perfect syndrome measurements cannot effectively be applied in the hardware); and a second quantum circuit configured to operate on the encoded quantum state and on encoded quantum information and comprising only one or more logical Clifford gates to realise, by taking the encoded quantum state as an input (see page 28, section VI, In magic state distillation schemes, the goal is to distill magic states with circuits that require only stabilizer operations [30, 31, 33]. The circuits used to distill such magic states are typically not fault-tolerant to all Clifford gate errors and thus must be implemented using a sufficiently large error-correcting code). Christopher does not explicitly teach realise a logical non-Clifford gate on the encoded quantum information. However, Rengaswamy in the same the field of endeavor teaches realise a logical non-Clifford gate on the encoded quantum information (see section 6.1 on page 133, herein for realizing a logical non-Clifford gate on a stabilizer code we need to implement a physical non-Clifford gate). Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to modify the quantum computing system of Christopher with the teachings of Rengaswamy by realising a logical non-Clifford gate on the encoded quantum information. This modification would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, because one of ordinary skill in the art would have recognized the realising a logical non-Clifford gate on the encoded quantum information would have improved the quality of solutions produced by the algorithm (see page 131 of Rengaswamy). Examiner Notes 11. When amending the claims, applicants are respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. Prior Art 12. The prior art of record, considered pertinent to the applicant’s disclosure, is listed in the attached PTO-892 form. Conclusion 13. Any inquiry concerning this communication or earlier communications from the examiner should be directed to OSMAN ALSHACK whose telephone number is (571)272-2069. The examiner can normally be reached on MON-FRI 8:30 AM-5:00 PM EST, also please fax interview request to (571) 273- 2069. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, ALBERT DECADY can be reached on 5712723819. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /OSMAN M ALSHACK/Examiner, Art Unit 2112
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Prosecution Timeline

Dec 01, 2023
Application Filed
Jun 09, 2026
Non-Final Rejection mailed — §101, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
99%
With Interview (+14.3%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 525 resolved cases by this examiner. Grant probability derived from career allowance rate.

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