DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 2013/03/16, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2023/12/04 and 2023/12/11 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show
a "Gm" gate-terminal connection at the substrate terminal SUB of FIG. 1, as described in the specification (¶[0026]: "a gate terminal Gm electrically connected to the substrate terminal SUB of the substrate").
transistor 361 and AND gate 360 connected within the complete circuit of FIG. 3A, as described in the specification (¶s [0075–0077]).
Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d).
The drawings are further objected to because
FIG. 4C's axis label "IA(A)" does not correspond to the current "1A" as described in the specification (¶s [0090–0092]).
FIG. 5C's axis labels "IB(A)" and "IC(A)" do not correspond to the currents "1B" and "1C" as described in the specification (¶s [0101–0104]).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Battery Protection Circuit Having Bidirectional Transistor-Set Current Paths.
The disclosure is objected to because of the following informalities:
¶[0025]: "P/2" should be "P/L2".
¶[0042]: "gate metal layer 144" should be "gate metal layer 114".
¶[0095]: "the transistors 515, 515 and 519" duplicates numeral 515 where 514 was evidently intended (per the parallel ¶[0084] "414, 415, and 419" pattern).
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites that "the second node electrically connects to a cathode of the battery." Claim 16 recites that the regulation circuit's second node electrically connects to a cathode of the battery. The term "cathode" identifies a terminal by its electrochemical polarity during discharge; during charging, the same physical terminal functions as an anode. Claims 1 and 16 do not specify whether "cathode" designates a fixed physical terminal or is limited to the battery's discharge-mode polarity, and the specification does not resolve this ambiguity.
Claims 2–15 are rejected as depending from claim 1 and failing to cure this deficiency.
Claims 17–20 are rejected as depending from claim 16 and failing to cure this deficiency.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 16 – 18, 21 – 23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by MANDAI (US 2006/0076931 A1).
FIG. 3A, Instant Application
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FIG. 3, MANDAI (US 2006/0076931 A1)
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In re claims 1, 16, MANDAI discloses the following limitations (see FIG. 3 above):
a circuitry (protection circuit 2) electrically connected to a battery (secondary battery 1), comprising:
a regulation circuit (first MOSFET 5), comprising
a first node (node formed by source 52 of first MOSFET 5 joined to source 72 of third MOSFET 7),
a second node (node formed by drain 51 of first MOSFET 5 joined to drain 61 of second MOSFET 6) and
a third node (shared node formed by back-gate 58 of first MOSFET 5, back-gate 68 of second MOSFET 6, and back-gate 78 of third MOSFET 7),
wherein the first node electrically connects to a power source (FIG. 3: "Battery charging current / Battery discharging current" terminal), and
the second node electrically connects to the battery (secondary battery 1);
a first transistor set (third MOSFET 7),
electrically connecting to the first node and the third node of the regulation circuit (FIG. 3); and
a second transistor set (second MOSFET 6),
electrically connecting to the second node and the third node of the regulation circuit (FIG. 3);
wherein when the circuitry is operated in a first mode (¶[0052]: first control terminal 9 at "L" level and second control terminal 10 at "H" level, turning on third MOSFET 7),
the first node electrically connects to the third node through the first transistor set to create a first path from the first node to the second node (¶[0040]: current path formed from source 72, through third MOSFET 7 to drain 71, continuing via parasitic diode 65 to drain 61); and
when the circuitry is operated in a second mode (¶[0051]: first control terminal 9 at "H" level and second control terminal 10 at "L" level, turning on second MOSFET 6),
the second node electrically connects to the third node through the second transistor set to create a second path from the second node to the first node (¶[0039]: current path formed from drain 61, through second MOSFET 6 to source 62, continuing via parasitic diode 75 to source 72).
As to claim 16, MANDAI further discloses:
turning off the regulation circuit when the circuitry is operated in a first mode (¶s [0040, 0048, 0070]: AND of "L" from first control terminal 9 and "H" from second control terminal 10 yields gate 54 output "L," turning first MOSFET 5 off); and
turning off the regulation circuit when the circuitry is operated in a second mode (¶s [0039, 0048, 0074]: AND of "H" from first control terminal 9 and "L" from second control terminal 10 yields gate 54 output "L," turning first MOSFET 5 off).
In re claims 17 – 18, MANDAI discloses the following limitations:
when the circuitry is operated in a third mode (¶s [0036, 0050]: H/H control-terminal state), turning on the regulation circuit (¶s [0036, 0050]: first MOSFET 5 turned on)
for passing through the first path from the first node to the second node (¶s [0036, 0050]: current flows from the first node to the second node when source 72 is at a higher potential than drain 61) and
passing through the second path from the second node to the first node (¶s [0036, 0050]: current flows from the second node to the first node when drain 61 is at a higher potential than source 72)..
As for claim 18, MANDAI further discloses:
when the circuitry is operated in a fourth mode (¶[0053]: L/L control-terminal state),
turning off the regulation circuit to disable the second path or the first path (¶[0053]: MOSFETs 5, 6, 7 all off, no current paths formed).
In re claim 21, MANDAI discloses the following limitations (see FIG. 3 above):
a regulation circuit (switching element 3), comprising:
a first transistor (first MOSFET 5),
wherein a drain electrode of the first transistor (¶[0027]: source 52, interpretable as a drain per express source/drain equivalence) connects to a first node coupling to a power source (FIG. 3: "Battery charging current / Battery discharging current" terminal), and
a source electrode of the first transistor (drain 51) connects to a second node coupling to a battery (secondary battery 1);
a second transistor (second MOSFET 6),
wherein a gate electrode of the second transistor connects to a gate electrode of the first transistor (gate 64 and gate 54 connected via AND gate circuit 11), and
a source electrode of the second transistor (drain 61) connects to the second node (FIG. 3); and
a third transistor (third MOSFET 7),
wherein a gate electrode of the third transistor connects to the gate electrode of the first transistor (gate 74 and gate 54 connected via AND gate circuit 11), and
a source electrode of the third transistor (source 72) connects to the first node (FIG. 3);
wherein the regulation circuit is configured to allow carrying a first path during a first mode (¶[0039]: current path from the second node to the first node, enabled when first control terminal 9 "H" second control terminal 10 "L") and
carrying a second path during a second mode (¶[0040]: current path from the first node to the second node, enabled when first control terminal 9 "L" second control terminal 10 "H").
In re claims 22 – 23, MANDAI discloses the following limitations
wherein during the first mode (¶s [0048, 0051]: first control terminal 9 at "H" level, second control terminal 10 at "L" level), the regulation circuit is turned off (¶[0051]: AND of "H" and "L" turns first MOSFET 5 off) and
enables carrying the first path from the battery to the power source (¶s [0039, 0051, 0075]: current flowing from the second node to the first node via parasitic diode 56 and parasitic diode 75).
As to claim 23, MANDAI further discloses:
wherein during the second mode (¶s [0048, 0052]: first control terminal 9 at "L" level, second control terminal 10 at "H" level), the regulation circuit is turned off (¶[0052]: AND of "L" and "H" turns first MOSFET 5 off) and
enables carrying the second path from the power source to the battery (¶s [0040, 0052, 0071]: current flowing from the first node to the second node via parasitic diode 55 and parasitic diode 65).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claims 24 – 25 are rejected under 35 U.S.C. 103 as being unpatentable over MANDAI (US 2006/0076931 A1), in view of SHONO (US 2012/0275076 A1).
In re claim 24, MANDAI is silent to wherein the first transistor comprises: a substrate; a first nitride semiconductor layer on the substrate; and a second nitride semiconductor layer on the first nitride semiconductor layer, wherein a band gap of the second nitride semiconductor layer is greater than that of the first nitride semiconductor layer.
SHONO teaches the following limitations:
a substrate (substrate 20);
a first nitride semiconductor layer on the substrate (¶[0032]: undoped GaN electron transit layer 22 formed above substrate 20); and
a second nitride semiconductor layer on the first nitride semiconductor layer (¶[0032]: n-type AlGaN electron supply layer 23 formed directly on electron transit layer 22),
wherein a band gap of the second nitride semiconductor layer is greater than that of the first nitride semiconductor layer (¶[0032]: AlGaN electron supply layer 23's band gap necessarily greater than GaN electron transit layer 22's, given their heterojunction).
It would have been obvious for a PHOSITA to modify MANDAI's first transistor to include a first nitride semiconductor layer on a substrate and a second nitride semiconductor layer on the first nitride semiconductor layer, as taught by SHONO, necessarily giving the second nitride semiconductor layer a greater band gap than the first, in order to obtain the low-resistance, high-mobility channel that such a layer arrangement provides.
In re claim 25, MANDAI discloses the following limitations:
wherein a drain electrode of the second transistor connects to a drain electrode of the third transistor (¶s [0025 – 0027, 0029 – 0031]: source 62 of second MOSFET 6, interpretable as a drain per express source/drain equivalence, joined to drain 71 of third MOSFET 7),
and the second transistor and the third transistor are NMOS transistors (¶s [0069 – 0071, 0074 – 0075]: parasitic diode 75 of third MOSFET 7 and parasitic diode 65 of second MOSFET 6 conducting in the source-to-drain direction characteristic of an N-channel MOSFET body diode).
Allowable Subject Matter
Claims 2 – 15, 19 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 2/19 requires the regulation circuit to further comprise a first, second, and third transistor arranged as recited — the first transistor's drain and source electrodes connected to the first and second nodes, respectively, and the second and third transistors' gate electrodes each tied to the first transistor's gate electrode, with their source electrodes connected to the second and first nodes, respectively — superimposed on, and in addition to, the first and second transistor sets already required by claim 1/16. MANDAI's switching element 3 comprises only three MOSFETs, all of which are already consumed by claim 1's/16’s own first/second-transistor-set mapping; no MOSFETs remain in MANDAI's disclosure to also supply claim 2's/19’s additional three-transistor structure without reusing the same physical devices in two mutually exclusive claimed roles. No reference identified during the prior art search discloses or suggests this additional first/second/third-transistor bridging arrangement, and no combination of the references of record discloses or suggests it absent impermissible hindsight reconstruction.
Claims 3-15 depend from claim 2 and therefore include all of the limitations of claim 2, which has been found to recite allowable subject matter over the prior art of record.
Claim 20 depends from claim 19 and therefore includes all of the limitations of claim 19, which has been found to recite allowable subject matter over the prior art of record.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
MOORE (US 5,764,032): discloses a replicable three-MOSFET common-node battery-switching cell, in which two independently-controlled transistors share a common node and may be implemented in any mix of n-channel and p-channel conductivity types (subject to parasitic body diode orientation). This is analogous to battery-protection switching architectures that split a single switching path into multiple common-node transistors.
MURAKAMI (US 2014/0146426 A1): discloses an AND-gate-qualified discharge transistor, which discharges an internal circuit node only when two control signals both satisfy a specified logic condition, avoiding the unnecessary power consumption of an unconditioned discharge path. This is analogous to AND-gate-controlled discharge switching used to selectively shut down or discharge a circuit node.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHANN DJANAL-MANN whose telephone number is (571)272-4697. The examiner can normally be reached Monday - Thursday 8:00 - 17:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Drew Dunn can be reached at (571) 272-2312. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D. JOHANN DJANAL-MANN/ Examiner, Art Unit 2859
/DREW A DUNN/ Supervisory Patent Examiner, Art Unit 2859
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