DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending.
Claim Objections
Claims 1-3 and 6-9 are objected to because of the following informalities:
Please insert a colon ":" after comprises, line 4, so that a processor is in the body of the claim.
Claims 2-3 and 6-9 are depending on claim 1 and therefore they are also objected.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 4-7, 12-13, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Wang (Pub. No.: US 20160197719 A1), hereinafter Wang, in view of Chandra et al. (Pub. No.: US 20150113186 A1), hereinafter Chandra.
With respect to claim 1, Wang teaches A time synchronization device for synchronizing an internal time with a time distributed from one host device among a plurality of host devices and for synchronizing a subordinate device with the internal time (FIG. 5, [0088], slave device, master device, backup master device), the time synchronization device comprises
selecting the one host device from among the plurality of host devices ([0047], slave device selects the master device from among the plurality of backup master device);
calculating a time correction value that is a correction value for correcting the internal time such that the one host device and the time synchronization device synchronize with each other ([0102], slave device calculates time correction value / time offset that is a correction value / T1 for correcting the internal time such that the one host device and the time synchronization device synchronize with each other);
a previous time correction value used for correcting the internal time ([0052, 0085, 0102], a previous time correction value / time offset as T1 used for correcting the internal time);
adjusting, in a case where the one host device is switched, adjusts a time correction value calculated for a switching destination host device on the basis of the stored previous time correction value ([0049-0053], switched from master device to backup master device, adjusts / corrects a time correction value calculated for a switching destination host device / backup master device on the basis of the stored previous time correction value); and
correcting the internal time on the basis of the adjusted time correction value ([0102-0106], slave device time synchronizes on the basis of the adjusted time correction value).
Wang does not explicitly teach a processor configured to execute operations comprising, and storing a previous time correction value.
However, Chandra teaches a processor configured to execute operations comprising ([0039], processor), and storing a previous time correction value (see claim 6, a time-offset register to store a determined time offset value).
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing data of the claimed invention to modify the teachings of Wang with the teachings of Chandra, in order provide multi-protocol tunneling across a multi-protocol I/O interconnect of a computer apparatus (Chandra, [0002]).
With respect to claim 4, Wang teaches A time synchronization method for synchronizing an internal time with a time distributed from one host device among a plurality of host devices and for synchronizing the internal time with a subordinate device, the time synchronization method comprising (FIG. 5, [0088], slave device, master device, backup master device):
selecting the one host device from among the plurality of host devices ([0047], slave device selects the master device from among the plurality of backup master device);
calculating a time correction value that is a correction value for correcting the internal time such that the one host device and the time synchronization device synchronize with each other ([0102], slave device calculates time correction value / time offset that is a correction value / T1 for correcting the internal time such that the one host device and the time synchronization device synchronize with each other);
a previous time correction value used for correcting the internal time ([0052, 0085, 0102], a previous time correction value / time offset as T1 used for correcting the internal time);
adjusting, in a case where the one host device is switched, adjusts a time correction value calculated for a switching destination host device on the basis of the stored previous time correction value ([0049-0053], switched from master device to backup master device, adjusts / corrects a time correction value calculated for a switching destination host device / backup master device on the basis of the stored previous time correction value); and
correcting the internal time on the basis of the adjusted time correction value ([0102-0106], slave device time synchronizes on the basis of the adjusted time correction value).
Wang does not explicitly teach a processor configured to execute operations comprising, and storing a previous time correction value.
However, Chandra teaches a processor configured to execute operations comprising ([0039], processor), and storing a previous time correction value (see claim 6, a time-offset register to store a determined time offset value).
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing data of the claimed invention to modify the teachings of Wang with the teachings of Chandra, in order provide multi-protocol tunneling across a multi-protocol I/O interconnect of a computer apparatus (Chandra, [0002]).
With respect to claim 5, Wang teaches A computer-readable non-transitory recording medium storing a computer-executable program instructions that when executed by a computer system to execute operations comprising (FIG. 5, [0088], slave device):
selecting the one host device from among the plurality of host devices ([0047], slave device selects the master device from among the plurality of backup master device);
calculating a time correction value that is a correction value for correcting the internal time such that the one host device and the time synchronization device synchronize with each other ([0102], slave device calculates time correction value / time offset that is a correction value / T1 for correcting the internal time such that the one host device and the time synchronization device synchronize with each other);
a previous time correction value used for correcting the internal time ([0052, 0085, 0102], a previous time correction value / time offset as T1 used for correcting the internal time);
adjusting, in a case where the one host device is switched, adjusts a time correction value calculated for a switching destination host device on the basis of the stored previous time correction value ([0049-0053], switched from master device to backup master device, adjusts / corrects a time correction value calculated for a switching destination host device / backup master device on the basis of the stored previous time correction value); and
correcting the internal time on the basis of the adjusted time correction value ([0102-0106], slave device time synchronizes on the basis of the adjusted time correction value).
Wang does not explicitly teach a processor configured to execute operations comprising, and storing a previous time correction value.
However, Chandra teaches a processor configured to execute operations comprising ([0039], processor), and storing a previous time correction value (see claim 6, a time-offset register to store a determined time offset value).
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing data of the claimed invention to modify the teachings of Wang with the teachings of Chandra, in order provide multi-protocol tunneling across a multi-protocol I/O interconnect of a computer apparatus (Chandra, [0002]).
With respect to claim 6, the combination of Wang and Chandra teaches the device of claim 1. Wang teaches wherein the time synchronization device represents a Boundary Clock device for synchronizing the internal time according to at least in part Precision Time Protocol (FIG. 5, [0004, 0049-0053]).
With respect to claim 7, the combination of Wang and Chandra teaches the device of claim 1. Wang teaches wherein the plurality of host devices operates according to Precision Time Protocol (FIG. 5, [0004, 0049-0053]).
With respect to claim 12, this claim recites the device of claim 6, and it is rejected for at least the same reasons.
With respect to claim 13, this claim recites the device of claim 7, and it is rejected for at least the same reasons.
With respect to claim 18, the combination of Wang and Chandra teaches the computer-readable non-transitory recording medium of claim 5. Wang teaches
wherein the time synchronization device represents a Boundary Clock device for synchronizing the internal time according to at least in part Precision Time Protocol (FIG. 5, [0004, 0049-0053]), and wherein the plurality of host devices operates according to Precision Time Protocol (FIG. 5, [0004, 0049-0053]).
Claims 3, 11, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Wang , in view of Chandra, and further in view of Sato (Pub. No.: US 20050185744 A1), hereinafter Sato.
With respect to claim 3, the combination of Wang and Chandra teaches the device of claim 1. Wang teaches wherein in a case where the one host device is switched, the adjusting further comprises correcting the internal time on the basis of the adjusted time correction value ([0102-0106]), and correcting the internal time on the basis of the time correction value calculated for the switching destination host device ([0102-0106]).
The combination of Wang and Chandra does not explicitly teach during a predetermined period of time after the predetermined period of time elapses.
However, Sato teaches a processor configured to execute operations comprising ([0039], processor), and storing a previous time correction value (see claim 6, a time-offset register to store a determined time offset value).
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing data of the claimed invention to modify the teachings of Sato with the teachings of Wang and Chandra, in order for the mobile station to properly perform the synchronization determination due to the change of external environments (Sato, [0002, 0007]).
With respect to claim 11, this claim recites the device of claim 3, and it is rejected for at least the same reasons.
With respect to claim 17, this claim recites the device of claim 3, and it is rejected for at least the same reasons.
Claims 8, 14, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Wang , in view of Chandra, and further in view of York (Pub. No.: US 20110170534 A1), hereinafter York.
With respect to claim 8, the combination of Wang and Chandra teaches the device of claim 1. Wang teaches wherein the one host device is switched ([0102-0106]).
The combination of Wang and Chandra does not explicitly teach according to Best Master Clock Algorithm.
However, York teaches according to Best Master Clock Algorithm ([0108]).
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing data of the claimed invention to modify the teachings of York with the teachings of Wang and Chandra, in order to determine the "best" or most accurate clock within the system to which all other clocks in the system will then synchronize to (York, [0108]).
With respect to claim 14, this claim recites the device of claim 8, and it is rejected for at least the same reasons.
With respect to claim 19, this claim recites the device of claim 8, and it is rejected for at least the same reasons.
Claims 9, 15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Wang , in view of Chandra, and further in view of Miyazaki (Pub. No.: US 20020167920 A1), hereinafter Miyazaki.
With respect to claim 9, the combination of Wang and Chandra teaches the device of claim 1. Wang teaches wherein the correcting the internal time on the basis of the adjusted time correction time in the time correction value caused by the one host device being switched to the switching destination host device ([0102-0106]).
The combination of Wang and Chandra does not explicitly teach suppresses a sudden change.
However, Miyazaki teaches suppresses a sudden change ([0093]).
Therefore, it would have been obvious to one of the ordinary skills in the art before the effective filing data of the claimed invention to modify the teachings of Miyazaki with the teachings of Wang and Chandra, in order to provide a point-to-multipoint type radio access system of communication between the base station and the subscriber stations (Miyazaki, [0002]).
With respect to claim 15, this claim recites the device of claim 9, and it is rejected for at least the same reasons.
With respect to claim 20, this claim recites the device of claim 9, and it is rejected for at least the same reasons.
Allowable Subject Matter
Claims 2, 10, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Pub. No.: US 20090016475 A1; “Rischar”, ([0046])
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/KIET TANG/
Primary Examiner, Art Unit 2469