DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 12 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Phillippe et al, FR2810768 . Phillippe et al disclose a method for fabricating of hybrid smart cards comprising: a chip card module (page 1, line 2; pages 9-13; figure 3) comprising a first metal layer (130) and a second metal layer (150) surrounding a layer of dielectric material (2+3), the first metal layer (130) defining a grid of contacts that is intended to be flush with the surface of a chip card ("contact pads 130"), the second metal layer being etched (method feature merely indicating that the layer is structured) with patterns defining metal conductors for connecting contact pads of an integrated circuit (10) to the grid of contacts through openings (170) provided in the layer of dielectric material, with an integrated circuit placed between the first and second metal layers inside the layer of dielectric material (figure 3). Claim(s) 12 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Yoshioka, US Pub. 2015/0271924 . Yoshioka et al disclose a chip card module (paragraph [1] "memory card"; figure 41) comprising a first metal layer (301a) and a second metal layer (308a) surrounding a layer of dielectric material (306), the first metal layer defining a grid of contacts ("terminals 301a") that is intended to be flush with the surface of a chip card (implicit; see figure 41), the second metal layer being etched (method feature merely indicating that the layer is structured) with patterns defining metal conductors ("wiring") for connecting contact pads (305a) of an integrated circuit (305) to the grid of contacts through openings provided in the layer of dielectric material (paragraph [147]), with an integrated circuit placed between the first and second metal layers inside the layer of dielectric material (figure 41). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-11 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshioka et al in v iew of Kowalski et al, US Patent No. 6,319,827 . Regarding claim 1, Yoshioka et al disclose a method for producing a chip card module (paragraph [l] "memory card"; figure 4; paragraphs [138]-[156]), comprising the steps of: providing a first metal sheet (301) ; at least one reference mark ; depositing and gluing at least one electronic component (305) on an upper face of the metal sheet at a location locali ze d ; relative to the at least one reference mark ] ; depositing a first layer of dielectric material (306) on the upper face of the metal sheet and on the electronic component ; producing openings in the first layer of hardened dielectric material (figure 4G; paragraph [147]: carrying out a groove and hole forming step) ; depositing a first conductive layer (figure 4G; paragraph [147] ", a plating step (wiring forming step)") ; covering all of the surface of the first layer of dielectric material ; depositing a second conductive layer filling the openings (implicit due to the method described in paragraph [147]; see also figure 1 disclosing a similar method with openings 107), etching the first metal sheet (figure 41; paragraph [152]) ; a nd the first conductive layer ; in order to produce conductor patterns, the etching of the first metal sheet forming a chip card contact grid. Yoshioka et al fail to disclose that the first metal sheet comprises at least one reference mark , the location is locali z ed relative to the at least one reference mark; depositing a first conductive layer covering all of the surface of the first layer of dielectric material. Kowalski et al disclose an integrated electronic micromodule and method for making the same comprising; (see figure 3; column 4, line 34 - column 5, line 18; in particular figure 3A) alternative methods for integrating a chip into a printed circuit by a layer of dielectric material which is deposited on an electronic component. It would have been obvious for an ordinary artisan to employ the alternate method of integrating the chip in the printed circuit of Yoshioka et al in order to better isolate the electrical components and prevent short circuit. With respect to providing a reference mark providing and localizing a reference, such limitation is common in the art for increasing efficiency and precision during production. Therefore, it would have been an obvious extension as taught by the prior art. Regarding claims 2-3, Yoshioka et al disclose providing a conductive layer by electrodeposition for contacting the electronic component. It is well known to provide a conductive priming material before the electrodeposition step. The subject matter in these claim s are considered to be an obvious alternative for producing a conductive layer for contacting the electronic component. Regarding claim 4, Yoshioka et al disclos e a laser for making openings (paragraph [112]). Regarding claims 5-7, the type of dielectric material, such as polyester, epoxy resin, polyimide, are common in the art, and/or the method of applying the material is a matter of choice for meeting specific customer requirement, which therefore, obvious. Regarding claim 8, Yoshioka et al disclose a semiconductor chip 305 . Regarding claim 9, Kowalski et al implicitly disclosed in the context of figure 3D "The layer of copper 9 is then etched so that the flat windings in the form of coils 10 appear, with each winding connected to a silicon chip 1. In view of such teaching, these steps easily apply to in the production of the smart cards of Yoshioka et al. Regarding claims 10-11 and 13 , in addition to the rejection of claim 1 above, a person skilled in the art is familiar with providing additional layers, in particular with respect to Kowalski et al (figure 9). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Finn, US Patent No. 11,755,873, discloses an RFID enabled metal transaction cards. Osborn et al, US Patent No. 10,860,914, disclose a contactless card and a method for assembly . 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