DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Pueschner et al, US Pub. 2015/0339565, in view of Yeap et al, US Pub. 2023/0274123.
Regarding claims 1 and 13, Pueschner et al disclose a smart module, a smart card, and a method for producing a smart card comprising: a substrate and a semiconductor chip 102; a first metal structure 108 and a dielectric layer 109; a second metal structure 162; plate through openings 110/160 and a contact array; the first metal structure 108 comprises electrically conductive material including copper, aluminum, gold, silver, nickel or other metals; the conductive structure is formed by forming a metal layer and subsequently etching the metal layer (structure 108 and 114); the openings may be formed by punching, etching, laser drilling, formed after formation of dielectric partial layer 109b and before formation of second structure 162. With respect to the fabrication order, positioning an electronic component at a predetermined location and embedding and/or protecting the component in dielectric material constituted known semiconductor packaging practice which would be obvious in order to protect the semiconductor within the conductive/dielectric stark while preserving the electrical interconnection. (See Fig. 1A-1G; par. 0027-0061).
Pueschner et al do not disclose that the antenna-bearing on the rear of the smart card module forming from the first conductive layer.
Yeap et al disclose an electronic circuit for smart card, a card chip module, and a method for manufacturing a smart card chip module comprising contacts 5 on the front face and antenna on the rear face 7 (see Fig, 3, par. 0024).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to configure Pueschner et al antenna bearing conductive structure on the read surface as expressly taught by Yeap et al in order to have the front surface providing standardized contact interface while the opposite surface provides the antenna for contactless communication. Such modification would allow the dual interface card to operate more effectively. Therefore, it would have been an obvious extension as taught by prior art.
Regarding claim 2 (wherein the steps of depositing the first and second conducting layers are carried out simultaneously and comprise a step of depositing a conductive priming material on the first layer of dielectric material and in the openings, followed by a step of electrodeposition of copper), Pueschner et al disclose metalizing openings and providing conductive metallic material in the openings and teach copper as a suitable material. Forming the conductive structure using conductive seed/priming layer followed by copper deposition was a conventional metallization technique. Therefore, such technique would have been an obvious fabrication choice for providing a conductive copper layer and conductive vias. Therefore, Pueschner et al as modified by Yeap et al render the claim obvious.
Regarding claim 3 (wherein the step of depositing the first conducting layer is done by depositing a second metal foil prior to the hot rolling step and the step of producing openings simultaneously produces openings in the first layer of dielectric material and in the second metal foil), Pueschner et al disclose multilayer metallic structures separated by dielectric material and teach forming openings through the layered structure by punching , drilling, laser drilling or etching it would have been obvious to form the opening through the laminated layers in a common operation to provide the require interlayer connection and to reduce manufacturing operation. Therefore, Pueschner et al as modified by Yeap et al render the claim obvious.
Regarding claim 4 (wherein the step of making openings is carried out by laser), Pueschner et al disclose that the plated through hole 160 may be formed punching, laser, after formation of dielectric partial layer 109b and before formation of second metal structure 162. Therefore, Pueschner et al as modified by Yeap et al render the claim obvious.
Regarding claim 5 (wherein the dielectric material is chosen from one of the following materials: polyester, epoxy resin, polyimide), accordingly such limitation would have been an obvious choice for meeting customer requirements. Therefore, Pueschner et al as modified by Yeap et al render the claim obvious.
Regarding claim 6 (wherein the first layer of dielectric material is a thermosetting material deposited in liquid or pasty phase and wherein the method comprises a step of hot rolling in order to flatten and harden the first layer of dielectric material) Pueschner et al, disclose a dielectric/adhesive material and hot lamination, including heating a thermoplastic dielectric beyond its melting point to develop its adhesive effect. Such conventional thermal processing to consolidate and control the thickness of the dielectric layer would have been an obvious manufacturing implementation. Therefore, Pueschner et al as modified by Yeap et al render the claim obvious.
Regarding claim 7 (wherein the hot rolling step is carried out using a press having a control of the pressing height), it is common that once a thermal pressing/rolling is employed to establish the dielectric/module thickness, controlling the displacement or pressing height represents a predictable process controlling technique for obtaining a predetermined laminated thickness. Therefore, Pueschner et al as modified by Yeap et al render the claim obvious.
Regarding claim 8 (wherein the electronic component is an integrated circuit), Pueschner et al disclose a semiconductor chip 102 as an electronic component. Therefore, Pueschner et al as modified by Yeap et al render the claim obvious.
Regarding claim 9 (wherein the step of etching the first metal foil and the first conducting layer comprises the steps of: depositing photosensitive layers on the first conducting layer and on the bottom surface of the first metal foil, insulating the photosensitive layers with a negative mask of the patterns defining the parts to be insulated, removing the insulated part; of the photosensitive layers, acid-etching the first conducting layer; and the bottom surface of the first metal foil on the areas where the insulated photosensitive layers have been removed), Pueschner et al disclose forming/structuring its metallic layers using lithographic and etching method, Employing the conventional photoresist mask development metal etching sequence for implementing Pueschner et al lithographic etching would have been obvious to one of ordinary skill because that sequence was a standard technique for selectively removing exposed portions of copper/metallization. Therefore, Pueschner et al as modified by Yeap et al render the claim obvious.
Regarding claims 10 and 13 ( wherein, at the end of the step of etching the first conducting layer, said method comprises the following steps: depositing a second layer of dielectric material on the first etched conducting layer, hot-rolling in order to flatten and harden the second layer of dielectric material, making openings; in the second layer of hardened dielectric material, depositing a third conducting layer; covering the entire surface of the second layer of dielectric material, depositing a fourth conducting layer filling the openings, etching the third conducting layer in order to produce patterns of conductors), Pueschner et al contemplates additional dielectric partial layers beyond dielectric layers 109a and 109b and teach additional metallization layers, dielectric separation, plated through hole, and patterned conductive structure, the dielectric layers may be provided and that additional metallization may be laminated onto the substrate. Repeating the process disclosed by Pueschner et al would have been obvious where additional electrical interconnection was required. Therefore, Pueschner et al as modified by Yeap et al render the claim obvious.
Regarding claim 11 (wherein the step of etching the third conducting layer comprises the steps of: depositing a photosensitive layer on the third conducting layer, insulating the photosensitive layer with a mask defining the parts to be insulated, removing the insulated part of the photosensitive layer, acid-etching the third conducting layer on the areas where the insulated photosensitive layer has been removed) Pueschner et al disclose forming/structuring its metallic layers using lithographic and etching method, Employing the conventional photoresist mask development metal etching sequence for implementing Pueschner et al lithographic etching would have been obvious to one of ordinary skill because that sequence was a standard technique for selectively removing exposed portions of copper/metallization. Therefore, Pueschner et al as modified by Yeap et al render the claim obvious.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Remarks:
In response to the applicant’s general argument regarding the antenna being formed in the rear surface of the card module, the examiner respectfully disagrees. The new prior art, Yeap et al disclose an electronic circuit for smart card, a card chip module, and a method for manufacturing a smart card chip module comprising contacts 5 on the front face and antenna on the rear face 7 (see Fig, 3, par. 0024). It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to configure Pueschner et al antenna bearing conductive structure on the read surface as expressly taught by Yeap et al in order to have the front surface providing standardized contact interface while the opposite surface provides the antenna for contactless communication. The applicant’s argument is not persuasive. Refer to the rejection above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL ST CYR whose telephone number is (571)272-2407. The examiner can normally be reached M to F 8:00-8:00.
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DANIEL ST CYR
Primary Examiner
Art Unit 2876
/DANIEL ST CYR/Primary Examiner, Art Unit 2876
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