Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
1. Applicant's arguments filed July 15th, 2026, have been fully considered but they are not persuasive.
Applicant argues, with respect to the rejections of the independent claims, that the combination of Ju and Shapiro fails to teach the limitations regarding “tiling being performed based on ‘a dimension of the array of values…’”, as “Ju is completely silent with respect to tiling being performed based on the number of SIMD processors”, as “the tiling unit is a component of a graphics processor 1840”, and “Shapiro’s processing elements are components of a systolic array architecture, which is fundamentally different from SIMD processors”.
In response to the above argument, Examiner respectfully disagrees. Applicant is arguing elements of the individual references without accounting for the nature of the combination of the references as applied in the Non-Final Rejection. Ju is not relied upon for teaching tiling being based on any of the claimed limitations, as Ju’s disclosure of a tiling unit and other tiled processing paradigms are not used specifically for splitting tensors inputs as required by the independent claims. Shapiro discloses the tiling of input tensor data (see Shapiro Abstract, Summary), and is relied upon for this aspect of the independent claims. While Shapiro is not relied upon for disclosing the use of SIMD processors, the assertion that systolic array architecture and SIMD processors are “fundamentally different” is not substantiated by any evidence or understand of the prior art. Both Ju and Shapiro disclose techniques for performing parallel processing on large types of input data (i.e., tensors), and Ju explicitly contemplates the exemplary graphics processing units (which may operate according to a SIMD paradigm) as being embodied in an “array” (Ju [0381], [0397-0403]). Therefore, Applicant’s arguments are not considered persuasive and the rejections are maintained.
The rest of Applicant’s arguments are based on the arguments addressed above. Above responses are thus applicable.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-4, 9, 11, 13-20, 25, 27, and 29-31 are rejected under 35 U.S.C. 103 as being unpatentable over Ju (US 2022/0324666) in view of Shapiro et al (US 2024/0412045, herein Shapiro).
Regarding claim 1, Ju teaches a method for reducing memory latency utilizing thread tiling, comprising:
receiving a tensor input as an array of values, the tensor input having a size including a first dimension, a second dimension, and a third dimension ([0060-0062], tensor inputs and outputs with three dimensions, [0146], tensor descriptor including vector size of tensor elements);
determining an operation type applied to the received tensor input ([0225], [0318], [0399], different types of operations on tensor data);
splitting the received tensor input into a plurality of processing elements based on: a dimension of the array of values, a number of single instruction multiple data (SIMD) processors, and an amount of available internal memory ([0063], [0099], [0104-0108], splitting of input tensor data according to mapping of tensor dimensions & [0168], [0172], [0439], [0483], assigning data to processing elements according to memory and resource availability & [0230], [0423], embodying processors as SIMD); and
processing the tensor on a SIMD processor ([0171], execution resources, [0225], tensor processing units & [0230], [0423], SIMD processors).
Ju fails to teach wherein the processing elements are a plurality of tiles.
Shapiro teaches a method for processing tensors ([0004], tensor processing) using a plurality of tiles ([0003-0005], [0050-0052], tiling of tensor data) and processing each tile of the plurality of tiles ([0021], [0042], processing of tensor data).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Ju and Shapiro to utilized tensor tiling. While Ju does not explicitly teach that the tensors may be split or operated upon using a tiled execution paradigm, Ju does account for an embodiment of a graphics processor which includes a tiling unit (Ju [0373]) and other operations that utilize types of tiling (Ju [0408], [0541]). Therefore, including the tiling of tensor data for processing, as taught by Shapiro, would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 2, the combination of Ju and Shapiro teaches the method of claim 1, further comprising: determining a size of a kernel; wherein the received tensor input is split further based on the determined size of the kernel (Ju [0126], [0536], use of computation and driver kernels, reshaping data based on amount of operations within computation kernels).
Regarding claim 3, the combination of Ju and Shapiro teaches the method of claim 2, further comprising: configuring the SIMD processor to perform the determined operation type between the kernel and each tile of the plurality of tiles (Ju [0126], [0600], use of computation kernels & [0521], SIMD units, Shapiro [0021], [0042], processing of tensor data by tile).
Regarding claim 4, the combination of Ju and Shapiro teaches the method of claim 2, further comprising: wherein the size of the kernel includes: a value of the first dimension, a value of the second dimension, and a value of the third dimension (Ju [0063], [0099], [0104-0108], splitting of input tensor data according to mapping of tensor dimensions & [0126], [0600], use of computation kernels).
Regarding claim 9, the combination of Ju and Shapiro teaches the method of claim 1, further comprising: splitting the tensor input into a plurality of slices based on the first dimension and the second dimension (Ju [0106-0108], splitting of tensor inputs based on multiple dimensions & [0333], [0346], [0377], processing elements split into slices of resources).
Regarding claim 11, the combination of Ju and Shapiro teaches the method of claim 1, further comprising: splitting the tensor input into a plurality of slices based on the second dimension and the third dimension (Ju [0106-0108], splitting of tensor inputs based on multiple dimensions & [0333], [0346], [0377], processing elements split into slices of resources).
Regarding claim 13, the combination of Ju and Shapiro teaches the method of claim 1, wherein the tensor input is split further based on the largest value of: the first dimension, the second dimension, and the third dimension (Ju [0106], split according to largest dimensional stride value & Shapiro [0031], [0121], tiling of large size tensors).
Regarding claim 14, the combination of Ju and Shapiro teaches the method of claim 1, further comprising: detecting a symmetry in the tensor input, wherein the tensor input is split into the plurality of tiles based on the detected symmetry (Shapiro [0023], symmetrical tensor tiling [0054], splitting of tensor data depending on data being symmetrical, asymmetrical, equal, or unequal).
Regarding claim 15, the combination of Ju and Shapiro teaches the method of claim 1, further comprising: splitting the received tensor input into a plurality of tiles further based on any one of: a size of an available register, a number of currently available registers, a length of an SIMD lane, and a combination thereof (Ju [0063], [0099], [0104-0108], splitting of input tensor data according to mapping of tensor dimensions & [0168], [0172], [0439], [0483], assigning data to processing elements according to memory and resource availability).
Claim 16 refers to a medium embodiment of the method embodiment of claim 1. Therefore, the above rejection for claim 1 is applicable to claim 16.
Claims 17-20, 25, 27, and 29-31 refer to a system embodiment of the method embodiment of claims 1-4, 9, 11, and 13-15, respectively. Therefore, the above rejections for claims 1-4, 9, 11, and 13-15 are applicable to claims 17-20, 25, 27, and 29-31, respectively.
3. Claims 10, 12, 26, and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Ju and Shapiro as applied to claims above, and further in view of Kamenetskaya et al (US 2024/0338555).
Regarding claim 10, the combination of Ju and Shapiro teaches the method of claim 9, further comprising splitting each slice of the plurality of slices based on the third dimension (Ju [0063], [0099], [0104-0108], splitting of input tensor data according to mapping of tensor dimensions).
Ju and Shapiro fail to teach splitting the slices into a plurality of fibers.
Kamenetskaya teaches a method comprising splitting slices of a tensor input into fibers based on a dimension ([0026-0027], slices of processing system, [0030-0032], three-dimensional tensor inputs split into fibers comprising subsets of the tensor elements, [0049-0050], input tensors and kernel tensors both comprising fibers).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Ju and Shapiro with those of Kamenetskaya to utilize tensor elements embodied as fibers. While Ju and Shapiro do not explicitly state that the tensor data may be split into subsets such as fibers, all three of Ju, Shapiro, and Kamenetskaya disclose techniques for parallel tensor processing wherein the tensors inputs are manipulated or split in order to increase throughput and processor efficiency. Therefore, including the ability to embody tensor portions as fibers, as disclosed by Kamenetskaya would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Regarding claim 12, the combination of Ju and Shapiro teaches the method of claim 9, further comprising splitting each slice of the plurality of slices based on the third dimension (Ju [0063], [0099], [0104-0108], splitting of input tensor data according to mapping of tensor dimensions).
Ju and Shapiro fail to teach splitting the slices into a plurality of fibers.
Kamenetskaya teaches a method comprising splitting slices of a tensor input into fibers based on a dimension ([0026-0027], slices of processing system, [0030-0032], three-dimensional tensor inputs split into fibers comprising subsets of the tensor elements, [0049-0050], input tensors and kernel tensors both comprising fibers).
It would have been obvious for one of ordinary skill in the art before the effective filing date of the invention to combine the teachings of Ju and Shapiro with those of Kamenetskaya to utilize tensor elements embodied as fibers. While Ju and Shapiro do not explicitly state that the tensor data may be split into subsets such as fibers, all three of Ju, Shapiro, and Kamenetskaya disclose techniques for parallel tensor processing wherein the tensors inputs are manipulated or split in order to increase throughput and processor efficiency. Therefore, including the ability to embody tensor portions as fibers, as disclosed by Kamenetskaya would merely entail a simple substitution of known prior art elements to achieve predictable results, and thus would have been obvious to one of ordinary skill in the art.
Claims 26 and 28 refer to a system embodiment of the method embodiment of claims 10 and 12, respectively. Therefore, the above rejections for claims 10 and 12 are applicable to claims 26 and 28, respectively.
Allowable Subject Matter
4. Claims 5-8 and 21-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J METZGER whose telephone number is (571)272-3105. The examiner can normally be reached Monday-Friday 8:30-5.
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/MICHAEL J METZGER/ Primary Examiner, Art Unit 2183
