DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 12-14, and 18 are rejected under 35 U.S.C. 102a1 as being anticipated by BOE Technology (CN 113448114A), of record by Applicant.
Regarding independent claim 1, BOE Technology (‘114) teaches in figures 1-3 and the corresponding text an array substrate (no number), comprising: a pixel region (display areas RGB) and a peripheral region (20, 30) surrounding the pixel region, wherein the peripheral region comprises a chip bonding region (30), and wherein the array substrate comprises: a substrate (not shown); a pixel circuit (Gate), a data signal line (Data), a test pad group (20), and a test switch circuit (T) that are provided on a side of the substrate, wherein the data signal line is electrically connected with the pixel circuit, the test pad group is in the chip bonding region, the test switch circuit is in the peripheral region and at a side of the pixel region away from the chip bonding region, and the test switch circuit is configured to connect or disconnect (via switching transistor T) the data signal line and the test pad group.
Regarding dependent claim 12, BOE Technology (‘114) teaches the chip bonding region (30) is between a first edge and the pixel region of the array substrate, and the array substrate further comprises: a first type test trace comprising a control signal test line (102) and a plurality of data signal test lines (104), wherein the control signal test line and the plurality of data signal test lines are electrically connected with the test pad group, the control signal test line and the plurality of data signal test lines are electrically connected with the test switch circuit, the test switch circuit is configured to cause a data signal test line among the plurality of data signal test lines to be connected to or disconnected the data signal line under control of signals transmitted from the control signal test line, so as to connect or disconnect the data signal line and the test pad group; wherein, in an extension direction of the first edge, a part of the plurality of data signal test lines are at a side of the pixel region, and another part of the plurality of data signal test lines are at another side of the pixel region.
Regarding dependent claim 13, BOE Technology (‘114) teaches the data signal test lines comprise a red image test line (D-R), a green image test line (D-G), and a blue image test line (D-B), and in the extension direction of the first edge, two of the red image test line, the green image test line, and the blue image test line are at a side of the pixel region, and the control signal test line and remaining one of the red image test line, the green image test line, and the blue image test line are at another side of the pixel region.
Regarding dependent claim 14, BOE Technology (‘114) teaches the test switch circuit comprises a plurality of test transistors (T), source electrodes or drain electrodes of the plurality of test transistors are electrically connected with the plurality of data signal test lines correspondingly, and the other of the source electrodes and the drain electrodes of the plurality of test transistors are electrically connected with a plurality of data signal lines correspondingly, gate electrodes of the plurality of test transistors are electrically connected with the control signal test line, and the plurality of test transistors are distributed in the extension direction of the first edge.
Regarding dependent claim 18, BOE Technology (‘114) teaches a counter substrate (not shown) disposed opposite to the array substrate; a liquid crystal layer between the array substrate and the counter substrate.
Allowable Subject Matter
Claims 2-11 and 15-17 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding dependent claim 2, the prior art of record neither shows nor suggest the chip bonding region is provided with a chip output pad that is configured to bond to an output port of a chip, and wherein the test pad group is at a side of the chip output pad away from the pixel region.
Due to their dependency, claims 3-11 and 17 are necessarily allowable.
Regarding dependent claim 15, the prior art of record neither shows nor suggest the chip bonding region is between a first edge and the pixel region of the array substrate, and in an extension direction of the first edge, the pixel region comprises two edge pixel regions and an intermediate pixel region between the two edge pixel regions, and the chip bonding region is provided with a chip output pad that is configured to bond to an output port of a chip; an end of a data signal line electrically connected to a pixel circuit in an edge pixel region and close to the test switch circuit is electrically connected to the test switch circuit through first fan-out wires, and an end of the data signal line electrically connected to a pixel circuit in an edge pixel region and away from the test switch circuit is electrically connected to the chip output pad through second fan-out wires, wherein the first fan-out wires are symmetrically arranged to the second fan-out wires.
Due to their dependency, claim 16 is necessarily allowable.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lui et al. (US 2019/0139501) teaches the state of the art of circuit structure of a display device.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH L WILLIAMS whose telephone number is (571)272-2465. The examiner can normally be reached M-Th 6:30 AM- 5:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JAMES R. GREECE can be reached at (571) 272-3711. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JOSEPH L. WILLIAMS
Primary Examiner
Art Unit 2875
/JOSEPH L WILLIAMS/Primary Examiner, Art Unit 2875