Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This action is in response to the amendment filed on 12/25/2025. Claims 1, 4-6, 9, 10, 13, 14, 18, and 19 have been amended while claims 2-3, 11-12, and 16-17 have been cancelled. Applicant added claims 21-24. Amended claim limitations have been fully considered but only claim 6 has been persuasive if placed with all of its narrow limitations into independent claim form. 1, 4-5, 7-10, 13-15 and 18-24 remain rejected in the application while claim 6 is objected to.
Response to Arguments
In response to applicant’s arguments regarding Paltashev failing to disclose any rule of dispatcher to core connections, arguments fully considered but is not persuasive. Paltashev explicitly discloses those limitations [Paltashev: 0035 “a unified shader pool 104 that includes one or more SIMD compute processing cores”][Paltashev: 0062 “A dispatch controller 537 propagates command task execution to shader processor input and task allocation ( via the shader interface 525 ) for further execution”][Paltashev: 0063 “The graphics engine 515 includes a queue block 540 to provide queues , buffers , and other hardware . The queue block 540 is configured to store commands or context information requested by a prefetch parsing block 541 that is configured to efetch the commands , data or context information from the caches via the cache interface 520. The graphics engine 515 also includes a RISC micro - engine 542 that can perform metacommand and data processing using commands or data that are prefetched from the queue block 541 and a dispatch controller 543”][Paltashev: 0129 “The virtual graphics pipelines 1810-1812 share fixed function hardware resources 1850 and shader engines from a unified shader engine pool 1855. The fixed function hardware resources 1850 and the unified shader engine pool 1855 contain multiple physical processing blocks”](teaches 2 distinct dispatch controllers and the unified shader pool with multiple cores) [Paltashev: 0062 “A dispatch controller 537 propagates command task execution to shader processor input and task allocation ( via the shader interface 525 ) for further execution .”][Paltashev: 0072 “the front - end 710 can provide context information associated with the commands via buses in the set 730 to configure the registers or state machines in the set 730 to determine an operational state of one or more of the virtual graphics pipelines 726-729 .”](teaches routes dispatcher output to cores ‘via the shader interface’, and identifies concrete on chip buses used for command/data conveyance corresponding to the claimed limitation). Claims 1, 4-5, 7-10, 13-15 and 18-24 remain rejected in the application.
In response to applicant’s argument regarding Gandhi failing to disclose dispatchers connected to different numbers of cores, arguments fully considered but is not persuasive. Gandhi explicitly teaches those limitations [Gandhi: 0019 “total amount of available resources of the GPU . For example , if GPU 102 has a 4 , 000 core processor 104 and a 4 GB memory 106 , it can be divided into 4 containers of slices with 1 , 000 cores with 1 GB of memory each . In this way , the total amount of allocated resources between the containers does not exceed the total amount of available resources”](teaches integer factor partitioning of the N cores into equal slices of size N/m, assigning a dispatcher per slice yields dispatchers connected to N/m cores) [Gandhi: 0020 “For example , if GPU 102 has a 4 , 000 core processor 104 and a 4 GB memory 106 , it can be divided into 16 containers with slices of 1 , 000 cores with 1 GB of memory each.”](teaches integer divisor counts of N (16), 2 such valid counts can be chosen as adjacent integers (mi, mi, +1) that divide N). Claims 1, 4-5, 7-10, 13-15 and 18-24 remain rejected in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 5, 8, 9, 10, 13, 14, 18, 19, 21, 22, 23, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over Paltashev et al. (U.S. Patent Publication No. 2021/0049729), in view of Gandhi et al. (U.S. Patent Publication No. 2017/0256017).
Regarding claim 1, Paltashev discloses a graphics processing unit, comprising data-and- command dispatchers and N graphics processing unit cores (interpreted as a GPU that has 2 or more dispatcher blocks that send commands/data and >= 2 GPU cores)[Paltashev: 0035 “a unified shader pool 104 that includes one or more SIMD compute processing cores”][Paltashev: 0062 “A dispatch controller 537 propagates command task execution to shader processor input and task allocation ( via the shader interface 525 ) for further execution”][Paltashev: 0063 “The graphics engine 515 includes a queue block 540 to provide queues , buffers , and other hardware . The queue block 540 is configured to store commands or context information requested by a prefetch parsing block 541 that is configured to efetch the commands , data or context information from the caches via the cache interface 520. The graphics engine 515 also includes a RISC micro - engine 542 that can perform metacommand and data processing using commands or data that are prefetched from the queue block 541 and a dispatch controller 543”][Paltashev: 0129 “The virtual graphics pipelines 1810-1812 share fixed function hardware resources 1850 and shader engines from a unified shader engine pool 1855. The fixed function hardware resources 1850 and the unified shader engine pool 1855 contain multiple physical processing blocks”](teaches 2 distinct dispatch controllers and the unified shader pool with multiple cores), wherein each one of the data-and-command dispatchers is connected to a configured number of the graphics processing unit cores (interpreted as every dispatcher has a path to at least one core)[Paltashev: 0060 “The shader interface 525 provides an interface to one or more shader engines”][Paltashev: 0062 “A dispatch controller 537 propagates command task execution to shader processor input and task allocation ( via the shader interface 525 ) for further execution”](teaches the dispatch controllers connect to cores through the shader interface, which interfaces to the shader engines (cores)), through data-and- command transmission lines, wherein configured numbers of the graphics processinq unit cores correspondinq to the data-and-command dispatchers are determined as follows: (interpreted as at least one dispatcher to core connection is realized over on chip signal lines/buses that carry commands/data)[Paltashev: 0062 “A dispatch controller 537 propagates command task execution to shader processor input and task allocation ( via the shader interface 525 ) for further execution .”][Paltashev: 0072 “the front - end 710 can provide context information associated with the commands via buses in the set 730 to configure the registers or state machines in the set 730 to determine an operational state of one or more of the virtual graphics pipelines 726-729 .”](teaches routes dispatcher output to cores ‘via the shader interface’, and identifies concrete on chip buses used for command/data conveyance corresponding to the claimed limitation); wherein at the same time, the graphics processing unit is configured to provide n virtual graphics processing unit according to a received instruction, and each one of the n virtual graphics processing unit includes one of the data-and-command dispatchers and some or all of the configured number of the graphics processing unit cores connected to said data-and-command dispatcher (interpreted as the GPU can represent 1 or more virtual GPUs, each vGPU bundles one dispatcher with a set of cores wired to it)[Paltashev: 0064 “FIG . 6 is a block diagram of a graphics processing system 600 that supports multiple reconfigurable virtual graphics pipelines ( or virtual GPUs”][Paltashev: 0064 “Each of the asynchronous compute engines 610-612 is able to support a different virtual graphics pipeline”][Paltashev: 0131 “access the unified shader pool 1855 via a set of queues 1865. Some embodiments of the queues 1865 include thread group queues that are used to support multiple shader pipes that concurrently issue executable compute kernels to an arbitration and dispatch unit 1870. The arbitration and dispatch unit 1870 can perform arbitration in the manner discussed herein with regard to FIG . 8. Some embodiments of the arbitration and dispatch unit 1870 form thread group queues that hold SIMD compute waves for dispatch to the unified shader pool 1855.”](the reference equates virtual graphics pipelines with virtual GPUs and ties each pipeline to an asynchronous compute engines. The asynchronous compute engines includes a dispatch controller and each pipeline issues work to cores in the unified shader pool via the dispatch unit), but fails to explicitly disclose one of the data-and-command dispatchers is connected to N qraphics processinq unit cores, andmi-mi+1 of the data-and-command dispatchers are connected to N/ migraphics processing unit cores, wherein mi and mi+1 are adjacent positive integers capable of beinq divided by N, and 1 < mi+1 <mi < N, wherein n is any positive integer less than or equal to N.
However, Gandhi discloses one of the data-and-command dispatchers is connected to N qraphics processinq unit cores [Gandhi: 0019 “total amount of available resources of the GPU . For example , if GPU 102 has a 4 , 000 core processor 104 and a 4 GB memory 106 , it can be divided into 4 containers of slices with 1 , 000 cores with 1 GB of memory each . In this way , the total amount of allocated resources between the containers does not exceed the total amount of available resources”](teaches integer factor partitioning of the N cores into equal slices of size N/m, assigning a dispatcher per slice yields dispatchers connected to N/m cores), andmi-mi+1 of the data-and-command dispatchers are connected to N/ migraphics processing unit cores, wherein mi and mi+1 are adjacent positive integers capable of beinq divided by N, and 1 < mi+1 <mi < N, wherein n is any positive integer less than or equal to N [Gandhi: 0020 “For example , if GPU 102 has a 4 , 000 core processor 104 and a 4 GB memory 106 , it can be divided into 16 containers with slices of 1 , 000 cores with 1 GB of memory each.”](teaches integer divisor counts of N (16), 2 such valid counts can be chosen as adjacent integers (mi, mi, +1) that divide N).
Paltashev and Ghandi are considered analogous to the claimed invention because they are in the same field of GPU virtualization. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Paltashev to incorporate Ghandi’s teachings of dividing N GPU cores into m partitions with N/m cores, so that one dispatcher maps to the full unified shader pool while additional dispatchers map to partitions of size N/mi. The motivation for such a combination would provide the benefit of balanced and predictable core allocation.
Regarding claim 4, Paltashev and Gandhi disclose the graphics processing unit according to claim 1, wherein the graphics processing unit includes N data-and-command dispatchers (interpreted as the GPU has N dispatcher blocks that issue data/commands)[Paltashev: 0101 “Some embodiments of the front - end 1205 are implemented using parallel hardware and firmware components that monitor and arbitrate multiple input queues via interaction with multiple sets of queue / context status descriptors ( or registers ) in the descriptor sets 1220-1222 . The status of any queue can be updated by the applications and confirmed using special message signaling or doorbells which could be detected by command processor 1200 using monitoring hardware in the front - end 1205. An arbitrated dispatch block 1225 is used to dispatch commands to the processor core 1210.”][Paltashev: 0062 “A dispatch controller 537 propagates command task execution to shader processor input and task allocation ( via the shader interface 525 ) for further execution . For example , the dispatch con troller 537 can dispatch commands to shader pool resources”][Paltashev: 0063 “The graphics engine 515 also includes a RISC micro - engine 542 that can perform metacommand and data processing using commands or data that are prefetched from the queue block 541 and a dispatch controller 543 that propagates command task execution to shader processor input and task allocation via the shader interface 525.”](teaches multiple dispatches controllers in the GPU front end (at least 537 and 543), ‘includes N’ is disclosed because the architecture has a plurality of dispatchers, N is the count).
Regarding claim 5, Paltashev and Gandhi disclose the graphics processing unit according to claim 4, wherein the graphics processing unit further includes at least one data selector [Paltashev: 0131 “The virtual graphics pipelines 1810-1812 access the unified shader pool 1855 via a set of queues 1865. Some embodiments of the queues 1865 include thread group queues that are used to support multiple shader pipes that concurrently issue executable compute kernels to an arbitration and dispatch unit 1870. The arbitration and dispatch unit 1870 can perform arbitration in the manner discussed herein with regard to FIG . 8.”](teaches ‘arbitration and dispatch unit 1870’ that sits between multiple shader pipes (command sources) and the unified shader pool 1855 (the processing cores). This arbitration and dispatch unit functions as a data selector by performing arbitration between multiple sources accessing the cores. An arbiter/selector performs the same function, selecting among multiple inputs to route to an output), and one of the graphics processing unit cores connecting with at least two data-and- command dispatchers is connected to the data-and-command dispatchers through the data selector [Paltashev: 0131 “Some embodiments of the queues 1865 include thread group queues that are used to support multiple shader pipes that concurrently issue executable compute kernels to an arbitration and dispatch unit 1870.”] [Paltashev: 0077 “The shader kernel executing on the compute unit 805 issues a call 808 to a fixed function hardware block 810 . The call 808 is received at an arbiter 815 that performs access arbitration between the call 808 and other calls that are received from other shader kernels . The arbiter 815 is able to provide the call 808 to a fixed function hardware scheduler 820”](teaches that multiple shader pipes (command sources/dispatchers) access the unified shader pool 1855 (cores) through the arbitration and dispatch unit 1870, this shows cores receiving from multiple dispatcher sources through an arbiter/selector).
Regarding claim 8, Paltashev and Gandhi disclose the graphics processing unit according to claim 1, wherein the data-and-command dispatchers are fully connected to the graphics processing unit cores (interpreted as the data and command dispatchers have connectivity to all GPU cores) [Paltashev: 0129 “The virtual graphics pipelines 1810-1812 share fixed function hardware resources 1850 and shader engines from a unified shader engine pool 1855. The fixed function hardware resources 1850 and the unified shader engine pool 1855 contain multiple physical processing blocks or physical pipe fragments that can be allocated to any pipeline fragments in one of the virtual graphics pipeline 1810-1812”][Paltashev: 0075 “Access to the shared on - chip hardware resources is controlled by blocks 787 , 786 perform access arbitration , scheduling , and queuing of tasks such as commands that are to be executed by the shader engines in the set 781 or the fixed function hardware units 783-786 .”](teaches connectivity between dispatchers and cores).
Claims 9 and 10 are chip graphics processing unit and an electronic device claims corresponding to claim 1 without any additional limitations. Thus, claims 9 and 10 are rejected for the same reasons as claim 1 above.
Claims 13 and 18 are chip graphics processing unit and an electronic device claims corresponding to claim 4 without any additional limitations. Thus, claims 13 and 18 are rejected for the same reasons as claim 4 above.
Claims 14 and 19 are chip graphics processing unit and an electronic device claims corresponding to claim 5 without any additional limitations. Thus, claims 14 and 19 are rejected for the same reasons as claim 5 above.
Regarding claim 21, Paltashev discloses the graphics processing unit according to claim 1, but fails to explicitly disclose wherein each one of the N graphics processing unit cores includes a set of graphics processing lines.
However, Gandhi discloses wherein each one of the N graphics processing unit cores includes a set of graphics processing lines [Gandhi: 0029 “multiple GPU cores comprises a plurality of hardware threads”].
Paltashev and Ghandi are considered analogous to the claimed invention because they are in the same field of GPU virtualization. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Paltashev to incorporate Ghandi’s teachings of utilizing hardware threads. The motivation for such a combination would provide the benefit of utilizing a known technique in the art.
Regarding claim 22, Paltashev discloses the graphics processing unit according to claim 1, but fails to explicitly disclose wherein each one of the N graphics processing unit cores is only contained in one of the n virtual graphics processing units at the same time.
However, Gandhi discloses wherein each one of the N graphics processing unit cores is only contained in one of the n virtual graphics processing units at the same time [Gandhi: 0030 “the second application and may make the second slice inaccessible to the first application , i . e . , the slices are in isolation with respect to one another”](teaches assigned resources at a given time, meaning the resources are contained in a specific GPU at the same time).
Paltashev and Ghandi are considered analogous to the claimed invention because they are in the same field of GPU virtualization. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Paltashev to incorporate Ghandi’s teachings of utilizing assigned resources in a GPU at a specific time. The motivation for such a combination would provide the benefit of utilizing a known technique in the art.
Regarding claim 23, Paltashev and Gandhi disclose the graphics processing unit according to claim 1, wherein each one of the N graphics processing unit cores comprises one or more selected from the group consisting of a shader module [Paltashev: 0001 “pixel shaders”], a transform feedback module [Paltashev: 0070 “The graphics processing system 700 includes feedback queues 701 that receives commands”], a position primitive assembly module, a final primitive assembly module [Paltashev: 0130 “primitive assembly , vertex shading”], a pixel engine module [Paltashev: 0130 “perform pixel shading”], and other modules.
Regarding claim 24, Paltashev and Gandhi disclose the graphics processing unit according to claim 1, wherein each one of the data selectors selects at most one data-and-command dispatcher to be connected to one or more graphics processing unit cores at the same time [Paltashev: 0062 “A dispatch controller 537 propagates command task execution to shader processor input and task allocation ( via the shader interface 525 ) for further execution .”][Paltashev: 0072 “the front - end 710 can provide context information associated with the commands via buses in the set 730 to configure the registers or state machines in the set 730 to determine an operational state of one or more of the virtual graphics pipelines 726-729 .”](teaches routes dispatcher output to cores ‘via the shader interface’, and identifies concrete on chip buses used for command/data conveyance meaning it selects data to be connected to the GPU).
Claims 7, 15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Paltashev et al. (U.S. Patent Publication No. 2021/0049729), in view of Gandhi et al. (U.S. Patent Publication No. 2017/0256017), in further view of Bisht et al. (U.S. Patent No. 10,812,079).
Regarding claim 7, Paltashev and Gandhi disclose the graphics processing unit according to claim 1, but fail to explicitly disclose wherein the number of physical layers of the graphics processing unit is configured according to the number of the data-and-command transmission lines.
However, Bisht discloses wherein the number of physical layers of the graphics processing unit is configured according to the number of the data-and-command transmission lines (interpreted as the count of on chip wiring layers is set based on how many signal lines must be routed for data/command traffic)(Bisht: Col. 1, Lines 53-60 “With the proliferation of multi-core chip architectures, the need for many wiring layers to interconnect all the different support components 12 and the microprocessors 14 to each 55 other has greatly proliferated. Accordingly, a large number of buses 1, along with bus bridge circuits 18, are now used”)(teaches that bus signal line count to the number of metal layers required and shows buses carried in specific layers, this teaches that configuring the number of layers according to the number of transmission lines to be routed).
Paltashev, Gandhi, and Bisht are both considered analogous to the claimed invention because they are in the same field of GPU virtualization. Therefore, it would have been obvious to someone of ordinary skill in the art before the effective filing date of the claimed invention to modify the system of Paltashev and Gandhi to incorporate Bisht’s teachings of sizing the number of layers according to the number of data and command transmission lines. The motivation for such a combination would provide the benefit of predictable rout-ability and timing closure.
Claims 15 and 20 are chip graphics processing unit and an electronic device claims corresponding to claim 7 without any additional limitations. Thus, claims 15 and 20 are rejected for the same reasons as claim 7 above.
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to AHMED TAHA whose telephone number is (571)272-6805. The examiner can normally be reached 8:30 am - 5 pm, Mon - Fri. Examiner interviews are available via telephone, in person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, XIAO WU can be reached at (571)272-7761. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786- 9199 (IN USA OR CANADA) or 571-272-1000.
/AHMED TAHA/Examiner, Art Unit 2613
/XIAO M WU/Supervisory Patent Examiner, Art Unit 2613