DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/11/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-3, 5-9 and 21-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. U.S. Patent Publication No. 2024/0005858 in view of Kang et al. U.S. Patent Publication No. 2017/0124939 (hereinafter Kang).
Consider claim 1, Zhang teaches a pixel circuit, comprising: a first power line (Figure 12, PVDD); a second power line (Figure 12, PVEE); a driving transistor, a first light-emitting control transistor and a light-emitting device connected in series between the first power line and the second power line (Figure 12, MT, M1, D), wherein one of a source or a drain of the driving transistor is connected with the first power line, and a cathode of the light-emitting device is connected with the second power line (Figure 12, MT, D, PVDD and PVEE), and wherein the light-emitting device should have an intrinsic capacitor (Light-emitting device D should have an intrinsic capacitor due to the physical properties of the LED (see below Kang)); a first node, between the first light-emitting control transistor and the light-emitting device (Figure 12, Nm); a first initialization line, electrically connected to the first node through a first initialization transistor (Figure 12, M8); a first capacitor, connected between the first node and a potential transmission line (Figure 12, C1); and a first transistor, connected between the first node and the light-emitting device (Figure 12, M2); a first terminal of the first capacitor is connected to the first node, and a second terminal of the first capacitor is connected to the potential transmission line (Figure 12, C1 and respective connections).
Zhang’s figure 12 does not appear to specifically disclose wherein the potential transmission line is the first power line.
However, Zhang teaches in [0050], the constant voltage signal line V1 may be a positive voltage signal line that outputs a positive voltage signal, such as a positive voltage signal of +3V, +5V, or other positive voltage values. In other examples, the constant voltage signal line V1 may also be a negative voltage signal line that outputs a negative voltage signal, such as a negative voltage signal of −3V, −5V or other negative voltage values, which is not limited in the embodiments of the present application. [0077], The first power supply voltage signal line PVDD is configured to provide a positive voltage signal, such as a voltage signal of +3.3V or other positive voltage values.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a particular potential in order to meet design choice since Zhang suggests +3,+5 or other positive voltage signal. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955).It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art, In re Antonie, 195 USPQ 6 (C.C.P.A. 1977).
Zang does not appear to specifically disclose wherein a first terminal of the intrinsic capacitor is connected to an anode of the light- emitting device, and a second terminal of the intrinsic capacitor is connected to the cathode of the light-emitting device and the second power line.
However, in a related field of endeavor, Kang teaches a pixel circuit in figure 1 and further teaches wherein a first terminal of the intrinsic capacitor is connected to an anode of the light- emitting device, and a second terminal of the intrinsic capacitor is connected to the cathode of the light-emitting device and the second power line (Figure 1, Coled; [0047], Coled….(e.g. exhibited by) the organic light emitting diode LD).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to consider Coled as taught by Kang with the benefit that Coled may be included in (e.g., exhibited by) the organic light emitting diode LD as suggested in [0047].
Consider claim 2, Zhang and Kang teach all the limitations of claim 1. In addition, Zhang teaches wherein a gate of the first light-emitting control transistor is connected with a light-emitting control line (Figure 12, M1), a gate of the first initialization transistor is connected with a first control line (Figure 12, M8), and a gate of the first transistor is connected with a second control line (Figure 12, M2).
Consider claim 3, Zhang and Kang teach all the limitations of claim 1. In addition, Zhang teaches wherein the potential transmission line is used to transmit a constant voltage signal (Figure 12 and [0050], V1).
Consider claim 5, Zhang and Kang teach all the limitations of claim 2. In addition, Zhang teaches wherein a channel type of the first light-emitting control transistor is the same as a channel type of the first transistor (Figure 12, p-type M1, p-type M2), and the second control line is a luminescent control line (Figure 12, EM2).
Consider claim 6, Zhang and Kang teach all the limitations of claim 2. In addition, Zhang teaches a second initialization transistor, one of a source or a drain of the second initialization transistor is connected with a gate of the driving transistor, the other of the source or the drain of the second initialization transistor is connected to a second initialization line, and a gate of the second initialization transistor is connected to a third control line (Figure 12, M4 and respective connections).
Consider claim 7, Zhang and Kang teach all the limitations of claim 6. In addition, Zhang teaches a second light- emitting control transistor, one of the source or drain of the second light-emitting control transistor is connected to the source or the drain of the driving transistor, the other of the source or drain of the second light-emitting control transistor is connected to the first power line (Figure 12, M6 and respective connections).
Zhang’s figure 12 does not show a gate of the second light-emitting control transistor is connected to the light-emitting control line or the second control line.
However, Zhang teaches in [0063], EM1 and EM2 may be the same.
Therefore, It would have been obvious to one of the ordinary skill in the art before effective filing date of the claimed invention to provide EM1 and EM2 with the same signal as taught by Zhang with the benefit that a number of wirings in the display panel where the pixel circuit is located and a number of shift registers can be reduced, a wiring space can be saved, so as to facilitate realizing a narrow border as suggested in [0064].
Consider claim 8, Zhang and Kang teach all the limitations of claim 1. In addition, Zhang teaches wherein in a writing stage of the pixel circuit ([0090] suggests writing of a data voltage signal and compensation during t2), the first initialization line receives the first initialization signal, the first light-emitting control transistor and the first transistor are cut-off (Figure 10, EM1 and EM2 are high during t2 and thus M1 and M2 are cut-off), and the first initialization signal is transmitted to the first capacitor through the first initialization transistor ([0099], before the light emitting stage t3, for example, in the initialization stage t1 or the threshold compensation stage t2, the eighth transistor M8 is turned on in response to the turn-on level of the third scan signal line S3, and transmits the reference voltage signal from the reference voltage signal line Vref to the second electrode plate of the first storage capacitor C1, so as to reset the second electrode plate of the first storage capacitor C1).
Consider claim 9, Zhang and Kang teach all the limitations of claim 1. In addition, Zhang teaches wherein in the light-emitting stage of the pixel circuit, the first light-emitting control transistor, a second light-emitting control transistor connected to the driving transistor, the driving transistor, and the first transistor are turned on (Figure 10, EM1 and EM2 are low during t3 and thus M6, MT, M1 and M2 are ON), and charge stored in the intrinsic capacitor of the light-emitting device flows to the first capacitor through the first transistor ([0050-0051], voltage regulator module 205 maintain the potential of the target node Nm and thus charge flows through the capacitor C1. Intrinsic capacitor made by the light-emitting D in figure 12 (see also Kang’s figure 1, parasitic Coled)).
Consider claim 21, Zhang and Kang teach all the limitations of claim 1. In addition, Zhang teaches wherein a conduction time period of the first light-emitting control transistor is the same as a conduction time period of the first transistor ([0091], in the light emitting stage…At the same time, a driving current of the driving transistor MT is transmitted to the first electrode of the light emitting element D through the first transistor M1 and the second transistor M2, and the light emitting element D emits light).
Consider claim 22, Zhang and Kang teach all the limitations of claim 1. In addition, Zhang teaches wherein a cut-off period of the first light-emitting control transistor is the same as a cut-off period of the first transistor ([0090] and figure 12, turn-off level, EM1-EM2 and M1-M2).
Claim(s) 10, 12-13, 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang and Kang and further in view of Yamashita et al. U.S. Patent Publication No. 2007/0152920 (hereinafter Yamashita).
Consider claim 10, Zhang teaches a display panel, comprising a plurality of pixel circuits (Figure 16, pixel circuits 20), each of the pixel circuit comprising: a first power line (Figure 12, PVDD); a second power line (Figure 12, PVEE); a driving transistor, a first light-emitting control transistor and a light-emitting device connected in series between the first power line and the second power line (Figure 12, MT, M1, D), wherein one of a source or a drain of the driving transistor is connected with the first power line, and a cathode of the light-emitting device is connected with the second power line (Figure 12, MT, PVDD, D and PVEE), and wherein the light-emitting device should have an intrinsic capacitor (Light-emitting device D should have an intrinsic capacitor due to the physical properties of the LED (see below Kang)); a first node, between the first light-emitting control transistor and the light-emitting device (Figure 12, Nm); a first control line (Figure 12, S3); a first initialization transistor, having a gate connected to the first control line (Figure 12, M8): a first initialization line, electrically connected to the first node through a source and a drain of the first initialization transistor (Figure 12, M8 and respective connections); a first capacitor, connected between the first node and a potential transmission line (Figure 12, C1), a first transistor, connected between the first node and the light-emitting device(Figure 12, M2); a data line; and a write transistor, wherein one of a source or a drain of the write transistor is connected to the data line, the other of the source or the drain of the write transistor is connected to the source or the drain of the driving transistor (Figure 12, M3 and respective connections), and a gate of the write transistor is connected to a first control line (Figure 12, S4); a first terminal of the first capacitor is connected to the first node, and a second terminal of the first capacitor is connected to the potential transmission line (Figure 12, C1 and respective connections).
Figure 12 does not show a first initialization transistor, having a gate connected to the first control line and a gate of the write transistor is connected to the first control line. In addition, Zhang’s figure 12 does not appear to specifically disclose wherein the potential transmission line is the first power line.
However, Zhang teaches in [0099], before the light emitting stage t3, for example, in the initialization stage t1 or the threshold compensation stage t2, the eighth transistor M8 is turned on in response to the turn-on level of the third scan signal line S3, and transmits the reference voltage signal from the reference voltage signal line Vref to the second electrode plate of the first storage capacitor C1, so as to reset the second electrode plate of the first storage capacitor C1. [0090] In the threshold compensation stage t2, the first scan signal line S1, the fourth scan signal line S4 and the sixth scan signal line S6 output a turn-on level (see also figure 10). [0092] suggests the fourth scan signal line S4 and the sixth scan signal line S6 may be a same signal line. Thus, [0099], [0090] and [0092] suggests a same line for S4, S6 and S3 since they provide a turn-on level at the same time.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a same first control line as suggested by Zhang in [0099], [0090] and [0092] with the benefit that a number of wirings in the display panel where the pixel circuit is located and a number of shift registers can be reduced, a wiring space can be saved, so as to facilitate realizing a narrow border as suggested in [0092].
In addition, Zhang teaches in [0050], the constant voltage signal line V1 may be a positive voltage signal line that outputs a positive voltage signal, such as a positive voltage signal of +3V, +5V, or other positive voltage values. In other examples, the constant voltage signal line V1 may also be a negative voltage signal line that outputs a negative voltage signal, such as a negative voltage signal of −3V, −5V or other negative voltage values, which is not limited in the embodiments of the present application. [0077], The first power supply voltage signal line PVDD is configured to provide a positive voltage signal, such as a voltage signal of +3.3V or other positive voltage values.
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide a particular potential in order to meet design choice since Zhang suggests +3,+5 or other positive voltage signal. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art, In re Aller, 105 USPQ 233 (C.C.P.A. 1955).It has been held that discovering an optimum value of a result effective variable involves only routine skill in the art, In re Antonie, 195 USPQ 6 (C.C.P.A. 1977).
Zang does not appear to specifically disclose wherein a first terminal of the intrinsic capacitor is connected to an anode of the light- emitting device, and a second terminal of the intrinsic capacitor is connected to the cathode of the light-emitting device and the second power line.
However, in a related field of endeavor, Kang teaches a pixel circuit in figure 1 and further teaches wherein a first terminal of the intrinsic capacitor is connected to an anode of the light- emitting device, and a second terminal of the intrinsic capacitor is connected to the cathode of the light-emitting device and the second power line (Figure 1, Coled; [0047], Coled….(e.g. exhibited by) the organic light emitting diode LD).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to consider Coled as taught by Kang with the benefit that Coled may be included in (e.g., exhibited by) the organic light emitting diode LD as suggested in [0047].
Zhang does not appear to specifically disclose wherein in the display panel, capacitances of the first capacitors in the plurality of pixel circuits are fixed and identical.
However, in a related field of endeavor, Choi teaches a pixel circuit in figure 2 and further teaches wherein in the display panel, capacitances of the first capacitors in the plurality of pixel circuits are fixed and identical ([0089], the capacitance Cs needs to be of a common value for the R, G, B pixels).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to provide same capacitance among pixels as taught by Choi in order to provide the common correcting time t for the R, G, B pixels as suggested in [0089].
Consider claim 12, it includes the limitations of claim 2 and thus rejected by the same reasoning.
Consider claim 13, it includes the limitations of claim 3 and thus rejected by the same reasoning.
Consider claim 15, it includes the limitations of claim 5 and thus rejected by the same reasoning.
Consider claim 16, it includes the limitations of claim 6 and thus rejected by the same reasoning.
Consider claim 17, it includes the limitations of claim 7 and thus rejected by the same reasoning.
Consider claim 18, it includes the limitations of claim 8 and thus rejected by the same reasoning.
Consider claim 19, it includes the limitations of claim 9 and thus rejected by the same reasoning.
Consider claim 20, Zhang, Kang and Choi teach all the limitations of claim 10. In addition, Zhang teaches wherein a conduction time period of the first light-emitting control transistor is the same as a conduction time period of the first transistor (Figure 10, EM1, EM2, M1 and M2).
Response to Arguments
Applicant's arguments filed 02/11/2026 have been fully considered but they are not persuasive.
On page 9, Applicant argues that “the first capacitor is not connected in parallel with the intrinsic capacitor. Kang therefore fails to teach the specific circuit structure now recited in amended claim 1.” The Office respectfully disagrees for the following reasons.
Examiner is using Kang for the purpose of showing an intrinsic capacitor. Thus, if Coled is included in D in Zhang’s figure 12. Thus, C1 and Coled in Zhang do not have a parallel connection.
On pages 9-10, Applicant argues that “A parasitic capacitance is distinct from an intrinsic capacitor, and even for the same light-emitting device, these two capacitances may differ.” The Office respectfully disagrees for the following reasons.
Kang teaches in [0047], Coled….may be included in (“e.g. exhibited by”) the organic light emitting diode LD and thus intrinsic.
On page 10, Applicant argues that “The claimed first capacitor is defined not merely by its capacitance value, but also by its placement and interconnections within the claimed circuit. A capacitor cannot be meaningfully compared in isolation from the circuit context in which it operates. The capacitor labeled "Cs" in Figure 2 of Yamashita is therefore not equivalent to the claimed first capacitor, at least because "Cs" occupies a different circuit position and serves a different functional role.” The Office respectfully disagrees for the following reasons.
C1 in Zhang’s figure 12 teach placement and interconnections within the claimed circuit. Consequently, these arguments have been considered but they are not persuasive.
Conclusion
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/ROBERTO W FLORES/Primary Examiner, Art Unit 2621