DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office Action is in response to Applicant’s amendment filed on April 23, 2026. Claims 1, 4-5, 7, 12-13, 15, 17 and 19 have been amended. No claims have been added. Claim 6 has been cancelled. Currently, claims 1-5 and 7-20 are pending.
Response to Arguments
Applicant’s arguments filed 04/23/2026 with respect to claims 1, 13 & 17 have been considered but are not persuasive. The reason is set forth below,
Regarding Amended Claim 1, 13 & 17, page 10-12, of the applicant’s arguments recites that “TAKENAKA discloses only a single gate electrode 7 on one side of the active structure layer (see TAKENAKA, FIG. 1A, [0016]). TAKENAKA does not disclose a double-gate structure, nor does TAKENAKA disclose the specific relationship between the gate electrodes and the top portion of the insulating layer, or that the gate electrodes do not cover the top surface of the second conductor portion.”.
However, in the original claim 1 the applicant claimed only a gate electrode and no mentions of the double gate, therefore did not required double gate recited in presently amended claims 1, 13 and 17. Furthermore, for the amended claims 1, 13 and 17, TAKENAKA et al. discloses the gate electrode 7 does not cover the top of the second conductor 4 and Chu et al. discloses double gate, therefore TAKENAKA et al. in view of Chu et al. still disclose the limitations of claim 4 and 6 which are incorporated to the independent claims 1, 13 and 17.
Furthermore, applicant added new limitation “the first gate electrode and the second gate electrode do not cover a surface of the second conductor portion away from the substrate in the orthographic projection direction.”
Upon further searching the newly found prior art Shepard; Joseph F. (US 5574294 A) “Shepard et al.” Figs. 2-7 shows the gate electrodes 100’ and 100” do not cover a surface of the second conductor portion away from the substrate in the orthographic projection direction.
For the stated reasons above a final rejection has been made using over TAKENAKA, SATOSHI (JP H11284191 A) “TAKENAKA et al.”, in view of Chu, Jack Oon ((US5689127A)) “Chu et al.” further in view of Shepard; Joseph F. (US 5574294 A) “Shepard et al.”
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7-8, 13-20 are rejected under 35 U.S.C. 103 as being unpatentable over TAKENAKA, SATOSHI (JP H11284191 A) “TAKENAKA et al.”, in view of Chu, Jack Oon ((US5689127A)) “Chu et al.” further in view of Shepard; Joseph F. (US 5574294 A) “Shepard et al.”.
Regarding Independent Claim 1, TAKENAKA et al. Figs. 1-7 a semiconductor device, comprising:
a substrate (“substrate 8” ¶ [0016]); and
at least one thin film transistor (“a TFT” ¶ [0016]) disposed on the substrate; wherein the thin film transistor comprises:
an active structure layer (“a channel forming region 3 forming a channel between the first source / drain region 2 and the second source / drain region 4” ¶ [0016]) disposed on the substrate, wherein the active structure layer comprises
a first conductor portion (“first source / drain region 2” ¶ [0016]), a channel portion (“a channel forming region 3” ¶ [0016]), and a second conductor portion (“second source / drain region 4” ¶ [0016]), wherein the first conductor portion is disposed on the substrate (Fig. 1A shows first conductor portion 2 is disposed on the substrate 8), the channel portion 3 is disposed on a side of the first conductor portion 2 away from the substrate 8 (Fig. 1A shows the channel portion 3 is disposed on a side of the first conductor portion 2 away from the substrate 8), and the second conductor 4 portion is disposed on a side of the channel portion 3 away from the substrate 8 (Fig. 1A shows the second conductor 4 portion is disposed on a side of the channel portion 3 away from the substrate 8);
a first insulating layer (“a gate insulating film 6” ¶ [0016]), wherein the first insulating layer covers the active structure layer and the substrate (Figs. 1-7 shows film 6 covers the active structure and the substrate);
a gate electrode (“gate electrode 7” ¶ [0016]),
the gate electrode 6 is overlapped with at least a side of the channel portion in a direction parallel to an extension direction of the substrate (Figs.1-7 shows the gate electrode 6 is overlapped with at least a side of the channel portion); and
a first electrode and a second electrode, wherein the first electrode is connected to the first conductor portion, and the second electrode is connected to the second conductor portion (“a first source/drain electrode 12 and a second source/drain electrode 13 are electrically connected to the first source/drain region 2 and the second source/drain region 4, respectively,” ¶ [0019]);
wherein a material of the channel portion is polysilicon (“the channel formation region 3 is formed of a polycrystalline semiconductor film 301” ¶ [0020]), and a growth direction of a crystal grain of the polysilicon is consistent with a moving direction of a carrier (“the polycrystalline semiconductor film 301 has a column axis (indicated by arrow A) aligned in the film deposition direction during film formation, i.e., in the out-of-plane direction of the substrate 8.) will have a columnar structure. In this columnar structure, in order to indicate that the column axis A is perpendicular to the substrate 8, the grain boundary is represented by a vertical line Bin the channel formation region 3 (polycrystalline semiconductor film 301)” ¶ [0020]).
However, TAKENAKA et al. does not disclose, wherein the gate electrode comprises a first gate electrode and a second gate electrode, the first gate electrode is located on a side of the active structure layer, and the second gate electrode is located on another side of the active structure layer;
wherein the active structure layer comprises a first side and a second side oppositely disposed, the first gate electrode covers a side of the first insulating layer facing the first side, the second gate electrode covers a side of the first insulating layer facing the second side, the first insulating layer comprises a top portion, and the top portion covers a side of the active structure layer away from the substrate;
in an orthographic projection direction of the semiconductor device, the first gate electrode and the second gate electrode are flush with a side of the top portion away from the substrate,
In the similar field of endeavor of vertical gate semiconductor device, Chu et al. Figs. 1A-6 discloses, wherein the gate electrode comprises a first gate electrode (left gate 34) and a second gate electrode (right gate 34), the first gate electrode is located on a side of the active structure layer (an active structural layer comprises a source layer 12, a channel layer 14, a drain layer 18), and the second gate electrode is located on another side of the active structure layer (FIGS. 1E, 2E and 3E show the first gate electrode (left gate 34) is located on a side of the active structure layer (an active structural layer comprises a source layer 12, a channel layer 14, a drain layer 18), and the second gate electrode (right gate 34) is located on another side of the active structure layer);
wherein the active structure layer (12, 14, 18) comprises a first side (left side of (12, 14, 16)) and a second side (right side of (12, 14, 16)) oppositely disposed, the first gate electrode (left gate 34) covers a side of the first insulating layer facing the first side, the second gate electrode covers (right gate 34)a side of the first insulating layer facing the second side, the first insulating layer comprises a top portion (passivation cap 28), and the top portion covers a side of the active structure layer away from the substrate 10;
in an orthographic projection direction of the semiconductor device, the first gate electrode and the second gate electrode are flush with a side of the top portion away from the substrate (Figs. 1-5 show an orthographic projection direction of the semiconductor device, the first gate electrode and the second gate electrode are flush with a side of the top portion away from the substrate).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the semiconductor device of TAKENAKA et al. with the chip including the vertical double-gate transistors of Chu et al. in order to avoids the alignment problems referred to hereinabove which problems are typically associated with horizontal double-gate transistors (Chu et al. Column 4, Lines 65-67).
However, Chu et al. does not disclose, the first gate electrode and the second gate electrode do not cover a surface of the second conductor portion away from the substrate in the orthographic projection direction.
In the similar field of endeavor of vertical gate semiconductor device, Shepard et al. Figs. 2-7 discloses, the first gate electrode and the second gate electrode (“regions 100' and 100"” ¶ Column 5, Line 8) do not cover a surface of the second conductor portion (Figs. 6-7 shows the side electrodes are not wrap around and does not cover the top electrode) away from the substrate (“a substrate with an insulating surface layer 10” Column 3, Lines 61-62) in the orthographic projection direction.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the gate electrodes of TAKENAKA et al. as modified by Chu et al. with the gate electrodes of Shepard et al. in order to overcome many of the process difficulties associated with the prior art processes by the formation of the sidewall TFT channel, in a self-aligned manner and without use of separate photomasks, along the sidewalls of a gate electrode. Further, the top and bottom gate electrodes are connected together by use of the top electrode layer in a novel manner (Shepard et al., Column 3, Lines 50-56).
Regarding Claim 2, TAKENAKA et al. as modified by Chu et al. and Shepard et al. discloses the limitations of claim 1. TAKENAKA et al. Figs. 1-7 further discloses wherein a slope angle of the active structure layer ranges from 80o to 90o (“a side end surface 302 of the polycrystalline semiconductor film 301 constituting the channel formation region 3 is perpendicular to the substrate 8, and the gate electrode 7 faces this side end surface 302 via the gate insulating film 6.” ¶ [0021]; as the orientation is perpendicular so the angle is 90o).
Regarding Claim 3, TAKENAKA et al. as modified by Chu et al. and Shepard et al. discloses the limitations of claim 1. TAKENAKA et al. Figs. 1-7 further discloses, wherein a thickness of the channel portion ranges from 5 nm to 1 mm (“semiconductor film 300 such as an amorphous silicon film having a thickness of about 500 angstroms to several um is formed.” ¶ [0025]).
Regarding Claim 4, TAKENAKA et al. as modified by Chu et al. and Shepard et al. discloses the limitations of claim 2. However, TAKENAKA et al. does not disclose, wherein in the direction parallel to the extension direction of the substrate, a side of the first conductor portion, a side of the channel portion, and a side of the second conductor portion are overlapped with the first gate electrode; another side of the first conductor portion, another side of the channel portion, and another side of the second conductor portion are overlapped with the second gate electrode.
In the similar field of endeavor of semiconductor device, Chu et al. Figs. 1A-6 discloses, wherein in the direction parallel to the extension direction of the substrate, a side of the first conductor portion, a side of the channel portion, and a side of the second conductor portion are overlapped with the first gate electrode; another side of the first conductor portion, another side of the channel portion, and another side of the second conductor portion are overlapped with the second gate electrode (FIGS. 1E, 2E and 3E show, the second gate (right gate 34) are located on both sides of the active structure layer, respectively; the two sides of the source, channel, drain layers 12, 14, 18 overlap the first and second gates, respectively).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the semiconductor device of TAKENAKA et al. with the chip including the vertical double-gate transistors of Chu et al. in order to avoids the alignment problems referred to hereinabove which problems are typically associated with horizontal double-gate transistors (Chu et al. Column 4, Lines 65-67).
Regarding Claim 5, TAKENAKA et al. as modified by Chu et al. and Shepard et al. discloses the limitations of claim 1. However, TAKENAKA et al. does not disclose, wherein a thickness of the first insulating layer is less than a thickness of the first conductor portion.
In the similar field of endeavor of semiconductor device, Chu et al. Figs. 1A-6 discloses, wherein a thickness (FIGS. 1D, 2D and 3D show wherein a thickness of the first insulating layer 30 is less than a thickness of the first conductor portion 12.) of the first insulating layer (“gate oxide 30” Column 4, Lines 25-26) is less than a thickness of the first conductor portion (“source layer 12” Column 4, Line 29).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the thickness of the insulating layer of TAKENAKA et al. with the thickness of insulating layer of Chu et al. in order to provide a smaller capacitance value relative to that provided by the oxide overlapping the channel layer 14, thus minimizing the input capacitance created by the gate oxide overlapping the source layer 12 and the drain layer 18 (Chu et al. Column 4, Lines 31-34).
Regarding Claim 7, TAKENAKA et al. as modified by Chu et al. and Shepard et al. discloses the limitations of claim 1. However, TAKENAKA et al. does not disclose, wherein at least two of the thin film transistors are provided, and in an orthographic projection of the semiconductor device, the gate electrode and the active structure layer are alternately arranged at intervals along a first direction, wherein the first direction is perpendicular to a direction of a long axis of the channel portion; each of the at least two thin film transistors comprises two gate electrodes, wherein in a same thin film transistor, one of the two gate electrodes is disposed on a side of the active structure layer, and other one of the two gate electrodes is disposed on another side of the active structure layer; and the first electrode, the second electrode, and the gate electrode are shared by two adjacent thin film transistors.
In the similar field of endeavor of semiconductor device, Chu et al. Figs. 4-5 discloses, wherein at least two the thin film transistors are provided, and in an orthographic projection of the semiconductor device, the gate electrode and the active structure layer are alternately arranged at intervals along a first direction, wherein the first direction is perpendicular to a direction of a long axis of the channel portion; each of the at least two thin film transistors comprises two gate electrodes, wherein in a same thin film transistor, one of the two gate electrodes is disposed on a side of the active structure layer, and other one of the two gate electrodes is disposed on another side of the active structure layer; and the first electrode, the second electrode, and the gate electrode are shared by two adjacent thin film transistors (In FIGS. 4-5, two adjacent transistors share a source layer, a drain layer, and a gate, and in FIG. 4, a connection portion connected to a drain layer of the at least two transistors, a connection portion connected to a source layer of the at least two transistors, a connection portion connected to a channel layer of the at least two transistors overlaps and extends in a direction perpendicular to a long axis of the channel layer. While the gates are disposed around the active structure layers in connection with Figure 2G, those skilled in the art will be able to obtain structures in which the gates are alternately and spaced apart from the active structure layers.).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the semiconductor device of TAKENAKA et al. with the chip including the vertical double-gate transistors of Chu et al. in order to avoids the alignment problems referred to hereinabove which problems are typically associated with horizontal double-gate transistors (Chu et al. Column 4, Lines 65-67).
Regarding Claim 8, TAKENAKA et al. as modified by Chu et al. and Shepard et al. discloses the limitations of claim 7. However, TAKENAKA et al. Figs. 1-7 further discloses, wherein the semiconductor device further comprises a first connecting portion provided in a same layer as the first conductor portion, the first connecting portion is connected to a side of first conductor portions of the at least two thin film transistors, and the first electrode is connected to the first connecting portion through a first via (Fig. 1 shows a first source/drain region 2 in contact with a first source drain electrode 12, which is connected to a first source/drain region 201 through a contact hole 111); the semiconductor device further comprises a second connecting portion provided in a same layer as the second conductor portion, the second connecting portion is connected to a side of second conductor portions of the at least two thin film transistors, and the second electrode is connected to the second connecting portion through a second via (Fig. 1 shows second source/drain region 4 in contact with a twelfth source-drain electrode 13, which is connected to a second source/drain region 401 through a contact hole 112, corresponds to a second connection).
Regarding Claim 13, TAKENAKA et al. Figs. 1-7 a display panel (“a liquid crystal display device” ¶ [0002]), comprising a semiconductor device, wherein the semiconductor device, comprising:
a substrate (“substrate 8” ¶ [0016]); and
at least one thin film transistor (“a TFT” ¶ [0016]) disposed on the substrate; wherein the thin film transistor comprises:
an active structure layer (“a channel forming region 3 forming a channel between the first source / drain region 2 and the second source / drain region 4” ¶ [0016]) disposed on the substrate, wherein the active structure layer comprises
a first conductor portion (“first source / drain region 2” ¶ [0016]), a channel portion (“a channel forming region 3” ¶ [0016]), and a second conductor portion (“second source / drain region 4” ¶ [0016]), wherein the first conductor portion is disposed on the substrate (Fig. 1A shows first conductor portion 2 is disposed on the substrate 8), the channel portion 3 is disposed on a side of the first conductor portion 2 away from the substrate 8 (Fig. 1A shows the channel portion 3 is disposed on a side of the first conductor portion 2 away from the substrate 8), and the second conductor 4 portion is disposed on a side of the channel portion 3 away from the substrate 8 (Fig. 1A shows the second conductor 4 portion is disposed on a side of the channel portion 3 away from the substrate 8);
a first insulating layer (“a gate insulating film 6” ¶ [0016]), wherein the first insulating layer covers the active structure layer and the substrate (Figs. 1-7 shows film 6 covers the active structure and the substrate);
a gate electrode (“gate electrode 7” ¶ [0016]),
the gate electrode 6 is overlapped with at least a side of the channel portion in a direction parallel to an extension direction of the substrate (Figs.1-7 shows the gate electrode 6 is overlapped with at least a side of the channel portion); and
a first electrode and a second electrode, wherein the first electrode is connected to the first conductor portion, and the second electrode is connected to the second conductor portion (“a first source/drain electrode 12 and a second source/drain electrode 13 are electrically connected to the first source/drain region 2 and the second source/drain region 4, respectively,” ¶ [0019]);
wherein a material of the channel portion is polysilicon (“the channel formation region 3 is formed of a polycrystalline semiconductor film 301” ¶ [0020]), and a growth direction of a crystal grain of the polysilicon is consistent with a moving direction of a carrier (“the polycrystalline semiconductor film 301 has a column axis (indicated by arrow A) aligned in the film deposition direction during film formation, i.e., in the out-of-plane direction of the substrate 8.) will have a columnar structure. In this columnar structure, in order to indicate that the column axis A is perpendicular to the substrate 8, the grain boundary is represented by a vertical line Bin the channel formation region 3 (polycrystalline semiconductor film 301)” ¶ [0020]),
wherein a slope angle of the active structure layer ranges from 80o to 90o (“a side end surface 302 of the polycrystalline semiconductor film 301 constituting the channel formation region 3 is perpendicular to the substrate 8, and the gate electrode 7 faces this side end surface 302 via the gate insulating film 6.” ¶ [0021]; as the orientation is perpendicular so the angle is 90o).
However, TAKENAKA et al. does not disclose, wherein the gate electrode comprises a first gate electrode and a second gate electrode, the first gate electrode is located on a side of the active structure layer, and the second gate electrode is located on another side of the active structure layer;
wherein the active structure layer comprises a first side and a second side oppositely disposed, the first gate electrode covers a side of the first insulating layer facing the first side, the second gate electrode covers a side of the first insulating layer facing the second side, the first insulating layer comprises a top portion, and the top portion covers a side of the active structure layer away from the substrate;
in an orthographic projection direction of the semiconductor device, the first gate electrode and the second gate electrode are flush with a side of the top portion away from the substrate,
In the similar field of endeavor of vertical gate semiconductor device, Chu et al. Figs. 1A-6 discloses, wherein the gate electrode comprises a first gate electrode (left gate 34) and a second gate electrode (right gate 34), the first gate electrode is located on a side of the active structure layer (an active structural layer comprises a source layer 12, a channel layer 14, a drain layer 18), and the second gate electrode is located on another side of the active structure layer (FIGS. 1E, 2E and 3E show the first gate electrode (left gate 34) is located on a side of the active structure layer (an active structural layer comprises a source layer 12, a channel layer 14, a drain layer 18), and the second gate electrode (right gate 34) is located on another side of the active structure layer);
wherein the active structure layer (12, 14, 18) comprises a first side (left side of (12, 14, 16)) and a second side (right side of (12, 14, 16)) oppositely disposed, the first gate electrode (left gate 34) covers a side of the first insulating layer facing the first side, the second gate electrode covers (right gate 34)a side of the first insulating layer facing the second side, the first insulating layer comprises a top portion (passivation cap 28), and the top portion covers a side of the active structure layer away from the substrate 10;
in an orthographic projection direction of the semiconductor device, the first gate electrode and the second gate electrode are flush with a side of the top portion away from the substrate (Figs. 1-5 show an orthographic projection direction of the semiconductor device, the first gate electrode and the second gate electrode are flush with a side of the top portion away from the substrate).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the semiconductor device of TAKENAKA et al. with the chip including the vertical double-gate transistors of Chu et al. in order to avoids the alignment problems referred to hereinabove which problems are typically associated with horizontal double-gate transistors (Chu et al. Column 4, Lines 65-67).
However, Chu et al. does not disclose, the first gate electrode and the second gate electrode do not cover a surface of the second conductor portion away from the substrate in the orthographic projection direction.
In the similar field of endeavor of vertical gate semiconductor device, Shepard et al. Figs. 2-7 discloses, the first gate electrode and the second gate electrode (“regions 100' and 100"” ¶ Column 5, Line 8) do not cover a surface of the second conductor portion (Figs. 6-7 shows the side electrodes are not wrap around and does not cover the top electrode) away from the substrate (“a substrate with an insulating surface layer 10” Column 3, Lines 61-62) in the orthographic projection direction.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the gate electrodes of TAKENAKA et al. as modified by Chu et al. with the gate electrodes of Shepard et al. in order to overcome many of the process difficulties associated with the prior art processes by the formation of the sidewall TFT channel, in a self-aligned manner and without use of separate photomasks, along the sidewalls of a gate electrode. Further, the top and bottom gate electrodes are connected together by use of the top electrode layer in a novel manner (Shepard et al., Column 3, Lines 50-56).
Regarding Claim 14, TAKENAKA et al. as modified by Chu et al. and Shepard et al. discloses the limitations of claim 13. TAKENAKA et al. Figs. 1-7 further discloses, wherein a thickness of the channel portion ranges from 5 nm to 1 mm (“semiconductor film 300 such as an amorphous silicon film having a thickness of about 500 angstroms to several um is formed.” ¶ [0025]).
Regarding Claim 15, TAKENAKA et al. as modified by Chu et al. and Shepard et al. discloses the limitations of claim 14. However, TAKENAKA et al. does not disclose, wherein in the direction parallel to the extension direction of the substrate, a side of the first conductor portion, a side of the channel portion, and a side of the second conductor portion are overlapped with the first gate electrode; another side of the first conductor portion, another side of the channel portion, and another side of the second conductor portion are overlapped with the second gate electrode.
In the similar field of endeavor of semiconductor device, Chu et al. Figs. 1A-6 discloses,
wherein in the direction parallel to the extension direction of the substrate, a side of the first conductor portion, a side of the channel portion, and a side of the second conductor portion are overlapped with the first gate electrode; another side of the first conductor portion, another side of the channel portion, and another side of the second conductor portion are overlapped with the second gate electrode (FIGS. 1E, 2E and 3E show, the second gate (right gate 34) are located on both sides of the active structure layer, respectively; the two sides of the source, channel, drain layers 12, 14, 18 overlap the first and second gates, respectively).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the semiconductor device of TAKENAKA et al. with the chip including the vertical double-gate transistors of Chu et al. in order to avoids the alignment problems referred to hereinabove which problems are typically associated with horizontal double-gate transistors (Chu et al. Column 4, Lines 65-67).
Regarding Claim 16, TAKENAKA et al. as modified by Chu et al. and Shepard et al. discloses the limitations of claim 15. However, TAKENAKA et al. does not disclose, wherein a thickness of the first insulating layer is less than a thickness of the first conductor portion.
In the similar field of endeavor of semiconductor device, Chu et al. Figs. 1A-6 discloses, wherein a thickness (FIGS. 1D, 2D and 3D show wherein a thickness of the first insulating layer 30 is less than a thickness of the first conductor portion 12.) of the first insulating layer (“gate oxide 30” Column 4, Lines 25-26) is less than a thickness of the first conductor portion (“source layer 12” Column 4, Line 29).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the thickness of the insulating layer of TAKENAKA et al. with the thickness of insulating layer of Chu et al. in order to provide a smaller capacitance value relative to that provided by the oxide overlapping the channel layer 14, thus minimizing the input capacitance created by the gate oxide overlapping the source layer 12 and the drain layer 18 (Chu et al. Column 4, Lines 31-34).
Regarding Claim 17, TAKENAKA et al. Figs. 1-7 a semiconductor device, wherein the semiconductor device, comprising:
a substrate (“substrate 8” ¶ [0016]); and
at least one thin film transistor (“a TFT” ¶ [0016]) disposed on the substrate; wherein the thin film transistor comprises:
an active structure layer (“a channel forming region 3 forming a channel between the first source / drain region 2 and the second source / drain region 4” ¶ [0016]) disposed on the substrate, wherein the active structure layer comprises
a first conductor portion (“first source / drain region 2” ¶ [0016]), a channel portion (“a channel forming region 3” ¶ [0016]), and a second conductor portion (“second source / drain region 4” ¶ [0016]), wherein the first conductor portion is disposed on the substrate (Fig. 1A shows first conductor portion 2 is disposed on the substrate 8), the channel portion 3 is disposed on a side of the first conductor portion 2 away from the substrate 8 (Fig. 1A shows the channel portion 3 is disposed on a side of the first conductor portion 2 away from the substrate 8), and the second conductor 4 portion is disposed on a side of the channel portion 3 away from the substrate 8 (Fig. 1A shows the second conductor 4 portion is disposed on a side of the channel portion 3 away from the substrate 8);
a first insulating layer (“a gate insulating film 6” ¶ [0016]), wherein the first insulating layer covers the active structure layer and the substrate (Figs. 1-7 shows film 6 covers the active structure and the substrate);
a gate electrode (“gate electrode 7” ¶ [0016]),
the gate electrode 6 is overlapped with at least a side of the channel portion in a direction parallel to an extension direction of the substrate (Figs.1-7 shows the gate electrode 6 is overlapped with at least a side of the channel portion); and
a first electrode and a second electrode, wherein the first electrode is connected to the first conductor portion, and the second electrode is connected to the second conductor portion (“a first source/drain electrode 12 and a second source/drain electrode 13 are electrically connected to the first source/drain region 2 and the second source/drain region 4, respectively,” ¶ [0019]);
wherein a material of the channel portion is polysilicon (“the channel formation region 3 is formed of a polycrystalline semiconductor film 301” ¶ [0020]), and a growth direction of a crystal grain of the polysilicon is consistent with a moving direction of a carrier (“the polycrystalline semiconductor film 301 has a column axis (indicated by arrow A) aligned in the film deposition direction during film formation, i.e., in the out-of-plane direction of the substrate 8.) will have a columnar structure. In this columnar structure, in order to indicate that the column axis A is perpendicular to the substrate 8, the grain boundary is represented by a vertical line Bin the channel formation region 3 (polycrystalline semiconductor film 301)” ¶ [0020]),
wherein a slope angle of the active structure layer ranges from 80o to 90o (“a side end surface 302 of the polycrystalline semiconductor film 301 constituting the channel formation region 3 is perpendicular to the substrate 8, and the gate electrode 7 faces this side end surface 302 via the gate insulating film 6.” ¶ [0021]; as the orientation is perpendicular so the angle is 90o).
However, TAKENAKA et al. does not disclose a chip,
wherein the gate electrode comprises a first gate electrode and a second gate electrode, the first gate electrode is located on a side of the active structure layer, and the second gate electrode is located on another side of the active structure layer;
wherein the active structure layer comprises a first side and a second side oppositely disposed, the first gate electrode covers a side of the first insulating layer facing the first side, the second gate electrode covers a side of the first insulating layer facing the second side, the first insulating layer comprises a top portion, and the top portion covers a side of the active structure layer away from the substrate;
in an orthographic projection direction of the semiconductor device, the first gate electrode and the second gate electrode are flush with a side of the top portion away from the substrate.
In the similar field of endeavor of vertical gate semiconductor device, Chu et al. Figs. 1A-6 discloses, a chip (“a fundamental building block in the field of integrated circuits” Column 1, Lines 9-10).
wherein the gate electrode comprises a first gate electrode (left gate 34) and a second gate electrode (right gate 34), the first gate electrode is located on a side of the active structure layer (an active structural layer comprises a source layer 12, a channel layer 14, a drain layer 18), and the second gate electrode is located on another side of the active structure layer (FIGS. 1E, 2E and 3E show the first gate electrode (left gate 34) is located on a side of the active structure layer (an active structural layer comprises a source layer 12, a channel layer 14, a drain layer 18), and the second gate electrode (right gate 34) is located on another side of the active structure layer);
wherein the active structure layer (12, 14, 18) comprises a first side (left side of (12, 14, 16)) and a second side (right side of (12, 14, 16)) oppositely disposed, the first gate electrode (left gate 34) covers a side of the first insulating layer facing the first side, the second gate electrode covers (right gate 34)a side of the first insulating layer facing the second side, the first insulating layer comprises a top portion (passivation cap 28), and the top portion covers a side of the active structure layer away from the substrate 10;
in an orthographic projection direction of the semiconductor device, the first gate electrode and the second gate electrode are flush with a side of the top portion away from the substrate (Figs. 1-5 show an orthographic projection direction of the semiconductor device, the first gate electrode and the second gate electrode are flush with a side of the top portion away from the substrate).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the semiconductor device of TAKENAKA et al. with the chip including the vertical double-gate transistors of Chu et al. in order to exhibit carrier flow from source to drain in a direction transverse to the plane of the substrate (e.g. vertical) on which they are formed (Chu et al. Column 1, Lines 15-17) and to avoids the alignment problems referred to hereinabove which problems are typically associated with horizontal double-gate transistors (Chu et al. Column 4, Lines 65-67).
However, Chu et al. does not disclose, the first gate electrode and the second gate electrode do not cover a surface of the second conductor portion away from the substrate in the orthographic projection direction.
In the similar field of endeavor of vertical gate semiconductor device, Shepard et al. Figs. 2-7 discloses, the first gate electrode and the second gate electrode (“regions 100' and 100"” ¶ Column 5, Line 8) do not cover a surface of the second conductor portion (Figs. 6-7 shows the side electrodes are not wrap around and does not cover the top electrode) away from the substrate (“a substrate with an insulating surface layer 10” Column 3, Lines 61-62) in the orthographic projection direction.
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the gate electrodes of TAKENAKA et al. as modified by Chu et al. with the gate electrodes of Shepard et al. in order to overcome many of the process difficulties associated with the prior art processes by the formation of the sidewall TFT channel, in a self-aligned manner and without use of separate photomasks, along the sidewalls of a gate electrode. Further, the top and bottom gate electrodes are connected together by use of the top electrode layer in a novel manner (Shepard et al., Column 3, Lines 50-56).
Regarding Claim 18, TAKENAKA et al. as modified by Chu et al. and Shepard et al. discloses the limitations of claim 17. TAKENAKA et al. Figs. 1-7 further discloses, wherein a thickness of the channel portion ranges from 5 nm to 1 mm (“semiconductor film 300 such as an amorphous silicon film having a thickness of about 500 angstroms to several um is formed.” ¶ [0025]).
Regarding Claim 19, TAKENAKA et al. as modified by Chu et al. and Shepard et al. discloses the limitations of claim 18. However, TAKENAKA et al. does not disclose, wherein in the direction parallel to the extension direction of the substrate, a side of the first conductor portion, a side of the channel portion, and a side of the second conductor portion are overlapped with the first gate electrode; another side of the first conductor portion, another side of the channel portion, and another side of the second conductor portion are overlapped with the second gate electrode.
In the similar field of endeavor of semiconductor device, Chu et al. Figs. 1A-6 discloses,
wherein in the direction parallel to the extension direction of the substrate, a side of the first conductor portion, a side of the channel portion, and a side of the second conductor portion are overlapped with the first gate electrode; another side of the first conductor portion, another side of the channel portion, and another side of the second conductor portion are overlapped with the second gate electrode (FIGS. 1E, 2E and 3E show, the second gate (right gate 34) are located on both sides of the active structure layer, respectively; the two sides of the source, channel, drain layers 12, 14, 18 overlap the first and second gates, respectively).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the semiconductor device of TAKENAKA et al. with the chip including the vertical double-gate transistors of Chu et al. in order to avoids the alignment problems referred to hereinabove which problems are typically associated with horizontal double-gate transistors (Chu et al. Column 4, Lines 65-67)
Regarding Claim 20, TAKENAKA et al. as modified by Chu et al. and Shepard et al. discloses the limitations of claim 19. However, TAKENAKA et al. does not disclose, wherein a thickness of the first insulating layer is less than a thickness of the first conductor portion.
In the similar field of endeavor of semiconductor device, Chu et al. Figs. 1A-6 discloses, wherein a thickness (FIGS. 1D, 2D and 3D show wherein a thickness of the first insulating layer 30 is less than a thickness of the first conductor portion 12.) of the first insulating layer (“gate oxide 30” Column 4, Lines 25-26) is less than a thickness of the first conductor portion (“source layer 12” Column 4, Line 29).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the thickness of the insulating layer of TAKENAKA et al. with the thickness of insulating layer of Chu et al. in order to provide a smaller capacitance value relative to that provided by the oxide overlapping the channel layer 14, thus minimizing the input capacitance created by the gate oxide overlapping the source layer 12 and the drain layer 18 (Chu et al. Column 4, Lines 31-34).
Claims 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over TAKENAKA, SATOSHI (JP H11284191 A) “TAKENAKA et al.”, in view of Chu, Jack Oon ((US5689127A)) “Chu et al.” further in view of Shepard; Joseph F. (US 5574294 A) “Shepard et al.” further in view of CAI, Jun-fei (CN112397579A) “CAI et al.”.
Regarding Claim 9, TAKENAKA et al. as modified by Chu et al. and Shepard et al. discloses the limitations of claim 8. TAKENAKA et al. further discloses a second insulating layer (Figs. 1-7 show an insulating film 9 is disposed between the gate and the first source/drain region 201 and exposes a portion of the first source/drain region 201).
However, TAKENAKA et al. does not disclose, wherein the semiconductor device further comprises a third connecting portion provided in a same layer as the gate electrode, the third connecting portion is connected to a side of gate electrodes of the at least two thin film transistors; in an orthographic projection direction of the semiconductor device, a second insulating layer is provided between the first connecting portion and the third connecting portion, the second insulating layer covers the first connecting portion and exposes the first conductor portion, and the third connecting portion is provided on a side of the second insulating layer away from the substrate.
In the similar field of endeavor of semiconductor device, CAI et al. Figs. 1-17 discloses wherein the semiconductor device further comprises a third connecting portion provided in a same layer as the gate electrode, the third connecting portion is connected to a side of gate electrodes of the at least two thin film transistors; in an orthographic projection direction of the semiconductor device, a second insulating layer is provided between the first connecting portion and the third connecting portion, the second insulating layer covers the first connecting portion and exposes the first conductor portion, and the third connecting portion is provided on a side of the second insulating layer away from the substrate (Figures 11-14, an end gate layer 26 connects one side of a plurality of sub-gate layers 25, disposed in the same layer as the gate 26).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify semiconductor device of TAKENAKA et al. with the connecting layers of CAI et al. in order to improve the integration of the three-dimensional thin film transistor, and reduce the projection area of the three-dimensional thin film transistor (CAI et al. ¶ [0067]).
Regarding Claim 10, TAKENAKA et al. as modified by Chu et al., Shepard et al. and CAI et al. discloses the limitations of claim 9. TAKENAKA et al. further discloses, wherein the semiconductor device further comprises a fourth connecting portion and a fifth connecting portion, the fourth connecting portion is provided in a same layer as the first conductor portion, and the fourth connecting portion is connected to another side of the first conductor portions of the at least two thin film transistors; the fifth connecting portion is provided in a same layer as the channel portion, and the fifth connecting portion is connected to a side of the channel portions of the at least two thin film transistors; the second connecting portion, the fourth connecting portion, and the fifth connecting portion extend in the first direction, wherein the second connecting portion, the fourth connecting portion, and the fifth connecting portion are overlapped in the orthographic projection direction of the semiconductor device (Fig. 1 shows a first source/drain region 2 on the right, a channel formation region 3 corresponds to a fourth connection and a fifth connection, the right half side of which has an overlapping portion in the direction of the orthogonal projection of the substrate).
Regarding Claim 11, TAKENAKA et al. as modified by Chu et al., Shepard et al. and CAI et al. discloses the limitations of claim 9. TAKENAKA et al. further discloses, wherein the channel portion and the second conductor portion extend in the direction of the long axis of the channel portion and cover a part of the second insulating layer (Fig. 5 shows the channel formation region 3 and the second source/drain region 4 extend in the long axis direction of the channel portion and cover portions of the insulating layer 9.).
Regarding Claim 12, TAKENAKA et al. as modified by Chu et al., Shepard et al. and CAI et al. discloses the limitations of claim 10. TAKENAKA et al. further discloses, wherein the first connecting portion, the fourth connecting portion and the first conductor portion are made of a same material and formed integrally, the second connecting portion and the second conductor portion are made of a same material and formed integrally (Figs. 1-7 shows a first connection and a fourth connection are placed on both sides of the first source/drain region 2, of the same material and are integrally formed, and a second connection is placed on one side of the second source/drain region 4, of the same material and are integrally formed; the fifth connection portion is provided on one side of the channel formation region and has the same material and is integrally formed.),
However, TAKENAKA et al. does not disclose, the third connecting portion and the gate electrode are made of a same material and formed integrally, and the fifth connecting portion and the channel portion are made of a same material and formed integrally.
In the similar field of endeavor of semiconductor device, CAI et al. Figs. 1-17 discloses wherein the third connecting portion and the gate electrode are made of a same material and formed integrally, and the fifth connecting portion and the channel portion are made of a same material and formed integrally (Figures 11-14, an end gate layer 26 connects one side of a plurality of sub-gate layers 25, disposed in the same layer as the gate 26).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify semiconductor device of TAKENAKA et al. with the connecting layers of CAI et al. in order to improve the integration of the three-dimensional thin film transistor, and reduce the projection area of the three-dimensional thin film transistor (CAI et al., Page 18).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
