CTFR 18/568,869 CTFR 78853 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Amendment/Arguments With the reply filed 2/5/26, Applicant has amended claim 1 to recite “a combiner circuit coupled to the plurality of filters and configured to: receive the respective filtered signal from the plurality of filters; and generate an equalized signal by non-linearly combining the received filtered signals according to a non-linear equalization function.” Claim 16 is similarly amended. Applicant states that the amendment finds support in the original disclosure: p. 5, l. 6 – p. 6, l. 2; p. 11, ll. 2-8, and Fig. 3. Applicant argues that the cited reference to Johansson fails to teach a “combiner circuit” configured to “generate an equalized signal by non-linearly combining the received filtered signals,” because Applicant contends that the linear combining performed by summer 117 of Johansson is not a non-linear combining. Applicant's arguments have been fully considered but they are not persuasive. It is noted that the claimed “combiner circuit” is supported by the elements of the disclosure mentioned above, which includes combiner circuit 130 of Fig. 3, which is a block that receives a plurality of parallel inputs (120-0 to 121-N-1), and provides an output Z n (102). Additionally, it is noted that the Office action maps the claimed “plurality of filters coupled in parallel” to filters 100-1 to 100-N of Johansson (see Fig. 5), and the claimed “combiner circuit” to elements including nonlinearity units 110-1 to 110N, second linear filters 115-1 to 115-N, and adder circuit 117 and subtractor unit 40a (Fig. 1) of Johansson. Although adder circuit 117 linearly combines parallel inputs to provide an output, the adder circuit 117 alone does not correspond to the claimed “combiner circuit,” but rather, the combination of elements stated above, which include non-linear elements 110-1 to 110-N correspond to an overall “combiner circuit,” and the functions of the non-linear elements provide a non-linear equalization function as part of the combiner circuit as claimed, as shown in Fig. 5 and described in paras. [0059], [0067]-[0068] and [0075]. As noted above, the combiner circuit of Johansson receives as input, the outputs from filters 100-1 to 100-N (see Fig. 5). Thus, the “combiner circuit” receives parallel inputs from filters 100-1 to 100-N, performs a non-linear equalization function on said inputs using non-linear elements 110-1 to 110-N, and provides an equalized signal output (i.e. at output port 42a), even though some linear combining is performed in an intermediate step internal to the combiner circuit. This is analogous to how the instant application states that “[t]he combiner circuit 130 may, e.g., linearly combine the outputs of the plurality of basis functions f for the input vector” (p. 5, ll. 16-17, emphasis added ), which also appears to occur internal to the disclosed combiner circuit 130. That is, despite a linear operation being performed internal to a combiner circuit, this does not preclude an overall combiner circuit from performing a non-linear combining of received filtered signals, where Johansson indicates the configuration to include nonlinear and linear functions (¶ [0059]. Accordingly, Johansson is considered to teach the limitations of the claims, as amended, and the rejection is maintained. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1, 2, 11-13, 16 and 17 are rejected under 35 U.S.C. 102( a)(1 ) as being anticipated by Johansson U.S. Pat. App. Pub. No. 2011/0276284 . Regarding claim 1, Johansson discloses an apparatus (e.g. see Fig. 5) for equalizing a digital input signal, as Johansson describes an apparatus for estimation and compensation of nonlinearity errors (¶¶ [0001], [0044]), comprising: an input node configured to receive the digital input signal (i.e. Fig. 5: digital input signal 32 – ¶ [0070]); a plurality of filters (100-1 to 100-N) coupled in parallel to the input node, wherein the plurality of filters are configured to filter the digital input signal and generate a respective filtered signal (i.e. outputs of each of filters 100-1 to 100-N – see Fig. 5); and a combiner circuit (i.e. including nonlinearity units 110-1 to 110-N, second linear filters 115-1 to 115-N and adder circuit 117, along with subtractor unit 40a [Fig. 1] receiving output 34 {¶ [0078]} from adder circuit 117) coupled to the plurality of filters (100-1 to 100-N) and configured to: receive the respective filtered signal from the plurality of filters (see Fig. 5); and generate an equalized signal (i.e. compensated digital output signal from subtractor 40a – Fig. 1, ¶ [0045]) by non-linearly combining the received filtered signals from filters (100-1 to 100-N) according to a non-linear equalization function, which includes the non-linear function provided by application of nonlinearity units 110-1 to 110-N – see ¶¶ [0059], [0067]-[0068], [0075]). Regarding claim 2, Johansson further discloses a respective impulse response function of the plurality of filters is fixed, as it has a given impulse response f k (n) (Fig. 4f, ¶¶[0068]-[0073]). Regarding claim 11, Johansson discloses a receiver comprising an apparatus (e.g. est. unit 30a) according to claim 1 (see Figs. 1, 5), and a non-linear system coupled to the apparatus and configured to output the digital input signal, as the input comes from a non-linear system (i.e. ADC 10), which causes a nonlinearity (see ¶ [0003]). Regarding claim 12, the non-linear system comprises an ADC 10 configured to output the digital input signal (see Fig. 1). Regarding claim 13, the non-linear system is configured to generate the digital input signal based on a radio frequency receive signal, as ADC 10 is part of a radio receiver that receives a continuous-time radio input signal (¶¶ [0015]-[0017]). Regarding claim 16, Johansson discloses a method for equalizing a digital input signal, as Johansson describes an apparatus for estimation and compensation of nonlinearity errors (¶¶ [0001], [0044]), comprising: receiving the digital input signal at an input node (i.e. Fig. 5: digital input signal 32 – ¶ [0070]); filtering the digital input signal using a plurality of filters (100-1 to 100-N) coupled in parallel to the input node to generate a respective filtered signal (i.e. outputs of each of filters 100-1 to 100-N – see Fig. 5); receiving the respective filtered signal from the plurality of filters at a combiner circuit (i.e. including nonlinearity units 110-1 to 110-N, second linear filters 115-1 to 115-N and adder circuit 117, along with subtractor unit 40a [Fig. 1] receiving output 34 {¶ [0078]} from adder circuit 117) coupled to the plurality of filters (100-1 to 100-N); and generating an equalized signal (i.e. compensated digital output signal from subtractor 40a – Fig. 1, ¶ [0045]) using the combiner circuit by non-linearly combining the received filtered signals according to a non-linear equalization function (i.e. function provided by application of nonlinearity units 110-1 to 110-N (see ¶¶ [0059], [0067]-[0068], [0075]). Regarding claim 17, Johansson discloses a respective impulse response function of the plurality of filters is fixed, as it has a given impulse response f k (n) (Fig. 4f, ¶¶[0068]-[0073]) . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim s 3, 4, 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Johansson in view of Ali Shah et al. U.S. Pat. App. Pub. No. 2014/0341267 . Regarding claims 3 and 18, Johansson discloses an apparatus and method using filters for equalizing a digital input, as described above, but does not expressly disclose that the filters are fractional delay filters. Ali Shah discloses the use of fractional-delay filters (¶ [0005]). It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to use fractional-delay filters as suggested by Ali Shah, for the filters in the apparatus of Johansson, in order to increase the tolerance against sampling phase errors and minimize noise enhancement arising from spectral nulls during aliasing, as indicated by Ali Shah (¶ [0005]). Regarding claims 4 and 19, the fractional delay filters are configured to delay the digital input signal by a respective fraction of a sampling period time (see Ali Shah, abstract) . 07-22-aia AIA Claim s 5 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Johansson in view of Ali Shah et al . as applied to claim s 3 and 18 above, and further in view of Nazarathy et al. U.S. Pat. App. Pub. No. 2017/0141943 . Regarding claims 5 and 20, Johansson in combination with Ali Shah disclose an apparatus and method for equalizing a digital input signal employing fractional delay equalizers, as described above, but do not expressly disclose that one delay may be zero. Nazarathy discloses that a fractional delay equalizer may be start at zero (¶ [0139]). It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to use a zero delay in a fractional delay equalizer, as suggested by Nazarathy, in the equalizer of Johansson in combination with Ali Shah, as it is a known implementation for a fractional delay equalizer to have one tap at a zero delay . 07-21-aia AIA Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Johansson in view of Laamanen et al. U.S. Pat. App. Pub. No. 2003/0035495 . Regarding claim 6, Johansson discloses an apparatus for equalizing a digital input signal, as described above, but does not expressly disclose that a sample rate of the equalized signal is equal to a sample rate of the digital input signal. Laamanen discloses that a sampling rate of an equalizer may be equal to the sampling rate of the incoming signal (¶ [0077]). It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to provide a sample rate of the equalized signal equal to a sample rate of the input signal, as suggested by Laamanen, in the apparatus of Johansson, to reduce complexity of the equalizer having to operate at faster than the incoming signal sampling rate . 07-21-aia AIA Claim s 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Johansson in view of Christensson et al. U.S. Pat. App. Pub. No. 2002/0065650 . Regarding claim 14, Johansson discloses a receiver for equalizing a digital input signal in a communication system, as described above, but does not expressly disclose that the receiver is part of a base station also including a transmitter. Christensson discloses a receiver 26 as part of a base station 3 which also includes a transmitter 32 (see Fig. 1). It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to include the receiver of Johansson in a base station as shown in Christensson, to provide communication in a mobile communication system. Regarding claim 15, Johansson discloses a receiver for equalizing a digital input signal in a communication system, as described above, but does not expressly disclose that the receiver is part of a mobile device also including a transmitter. Christensson discloses a receiver 40 as part of a mobile unit 2 which also includes a transmitter 18 (see Fig. 1). It would have been obvious to one of ordinary skill in the art, prior to the effective filing date of the claimed invention, to include the receiver of Johansson in a mobile as shown in Christensson, to provide communication in a mobile communication system . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 7-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion 07-39 AIA THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to David B. Lugo whose telephone number is 571-272-3043. The examiner can normally be reached M-F, 9-6. Examiner interviews are available via telephone and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hannah Wang can be reached at 571-272-9018. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID B LUGO/Primary Examiner, Art Unit 2631 6/3/2026 Application/Control Number: 18/568,869 Page 2 Art Unit: 2631 Application/Control Number: 18/568,869 Page 3 Art Unit: 2631 Application/Control Number: 18/568,869 Page 4 Art Unit: 2631 Application/Control Number: 18/568,869 Page 5 Art Unit: 2631 Application/Control Number: 18/568,869 Page 6 Art Unit: 2631 Application/Control Number: 18/568,869 Page 7 Art Unit: 2631 Application/Control Number: 18/568,869 Page 8 Art Unit: 2631 Application/Control Number: 18/568,869 Page 9 Art Unit: 2631
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