DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
2. The drawings are objected to because in the side perspective of the wiring circuit board of at least FIG. 5 and FIG. 6, the elements 12 (“base insulating layer”) and 21 (“dummy insulating layer”) appear to be the same part in the drawing. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
3. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant ), regards as the invention.
5. Claim 3 recites the limitation "cutting the insulating layer in the opening" in Line 3 on pg. 19 of the submitted claims. There seems to be insufficient antecedent basis for this limitation in the claim. Although Claim 3 recites “the supporting layer is etched to form an opening in the supporting layer,” it is not clear if “the opening” to be cut in the fifth step refers to this newly formed opening in the supporting layer or a different opening layer in the insulating layer itself.
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. Claims 1, 2, 3, 4, and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Kamei et al. in view of Ishii et al.
Kamei (US Pub. No. 2010/0155113 A1) is directed toward a wired circuit board assembly sheet (title). Ishii et al. (US Pub. No 2012/0033395 A1) is directed toward a printed circuit board assembly sheet and a method for manufacturing the same (title).
Regarding Claim 1, Kamei et al. discloses a method of manufacturing a wired circuit board assembly sheet 1 comprising:
a first step: setting a region for a suspension board with a circuit 2 (i.e.: “a pattern forming region”) and region for clearance grooves 9 (i.e.: “an opening forming region”) on a flat metal supporting board 18 (i.e.: “the supporting board”) (¶39, ¶43, ¶82-¶86; FIG. 1, FIG. 2, FIG. 3 and FIG. 4a of Kamei et al.);
a second step: simultaneously forming an insulating base layer 12 made of polyamide (i.e.: “insulating layer”) on the metal support board 18 in a pattern corresponding to the suspension board with circuits 2 (¶54, ¶87, FIG. 2, FIG. 3, and FIG. 4b of Kamei et al.);
a third step: simultaneously forming a conductive pattern 13 on the surface of the insulating base layer 12 and a striated portion 3 (i.e.: analogous to “the dummy pattern” of the instant application) on the surface of the metal supporting board 18 within the space between the circuit boards (i.e.: the opening forming region) via electrolytic copper plating (¶89, ¶90, ¶97, and FIG. 4c of Kamei et al.); and
a fourth step: forming openings in the metal supporting board 18 by a wet etching process using an aqueous solution of ferric chloride to form the clearance grooves 9 surrounding the circuit board (i.e.: etching at least a portion of the supporting layer in the opening forming region”) as indicated in ¶103, ¶104, ¶112, and FIG. 4e.
While Kamei et al. discloses the striated portion 3, this structure is not explicitly described as a dummy electrical pattern as required by Claim 1. Ishii et al. is directed toward a printed circuit board assembly sheet and method for manufacturing the same (title), so it is analogous art to Kamei et al. The PCB of Ishii et al. has a comparable structure to the PCB of Kamei et al. as described in the abstract of Ishii et al. (i.e.: support substrate, base insulating layer, dummy trace portion, and conductor traces).
Specifically, Ishii et al. describes that the non-functional metal features formed adjacent to the functional printed circuit board acts as a dummy trace portion (2) which comprises a series of dummy traces 15 and linear conductor trace 14 formed by using an electroplating process(¶43, ¶50-56, ¶60, FIG. 2, FIG. 4, and FIG. 6a). The use of dummy traces in the disclosure of Ishii et al. results in the formation of parallel metal tracks in the peripheral/interstitial zones. The presence of dummy metallic traces during electroplating acts would facilitate uniform distribution of current during plating across the PCB since the electrical resistance of the dummy trace is very low.
It would be obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the third step in the method of PCB preparation of Kamei et al. by using the explicit dummy traces taught by Ishii et al. The skilled artisan would be motivated to make the modification because the presence of the metallic dummy traces in the open regions would result in a lower electrical resistance throughout the PCB and facilitate a more uniform electrodeposition process.
Regarding Claim 2, Kamei et al. in view of Ishii et al. discloses the method for producing a wiring circuit board according to claim 1, wherein in the second step, the insulating layer is formed in the pattern forming region and the opening forming region, and in the third step, the dummy pattern is formed on the insulating layer in the opening forming region as evidenced by an embodiment in Kamei et al. where the striated portions 3 (i.e.: dummy patterns) are formed as a multi-layer stack by laminating the resin of the base layer 12 and the conductive metal pattern 13 sequentially (¶137-141 and FIG. 7). In the previously described configuration in Kamei et al., the insulating layer spans into the opening region and the plated metal dummy trace sits directly on top of it.
Regarding Claim 3, Kamei et al. in view of Ishii et al. discloses the method of producing a wiring circuit board according to Claim 2 further comprising the following series of steps:
the first step, a product region including the pattern forming region and the opening forming region and a frame region connected to the product region are further set in the supporting layer since Kamei et al. discloses the metal supporting board 18 sets up and defines a plurality of individual suspension boards with circuits 2 (i.e.: “the product region”) and a surrounding, continuous outer support sheet 4 (i.e.: “frame region”) configured to handle and support the panel assembly (¶39, ¶55, ¶81, and FIG. 1). Similarly, Ishii et al. teaches a comparable regional layout on its support substrate 10 which defines a plurality of printed circuit board (i.e.: product region) integrally supported with a quadrangular support frame FR (i.e.: “frame region”) as per ¶42-45 and FIG. 2).
and in the fourth step, the entire supporting layer in the opening forming region is etched to form an opening in the supporting layer, and a portion of the supporting layer between the product region and the frame region is etched to form an outer shape of a wiring circuit board along a shape of the product region and to form a frame connected to the wiring circuit board along a shape of the frame region as supported by Kamei et al. which teaches using a wet chemical etching process to completely dissolve and remove the full thickness of the metal supporting board 18 within the clearance groove 9 (¶104 and ¶112). This forms openings in the carrier layer and also carves out the exact outer shape of each suspension board 2 along the profile of the product region (Kamei et al. in ¶103 and ¶ 114). The etching step of Kamei et al. leaves the outer processing frame sheet 4 structurally connected to the circuit boards via un-etched metal supports 26 (¶82, ¶83, ¶114, ¶115, and FIG. 4e). Similarly. Ishii et al. teaches that regions of the metal support substrate 10 are selectively removed by wet chemical etching except certain regions of the suspension bodies 1a (¶64). The structural etching of Ishii et al. forms separation grooves TR and substrate openings, resulting in the isolation of the outer shape of the printed circuit boards (¶43 and ¶64). This process in Ishii et al. simultaneously leaves small coupling portions J that structurally bridge the circuit boards to the main support frame FR (¶43, ¶ 45, and FIG. 2).
and the method for producing the wiring circuit board, further comprising a fifth step of cutting the wiring circuit board from the frame and cutting the insulating layer in the opening from the wiring circuit board as supported by Kamei et al. in teaching that the completed individual suspension boards 2 are subsequently separated and appropriately cut away across the clearance grooves 9 from the continuous sheet framework for the final assembly (¶83). Ishii et al. explicitly teaches a standard de-paneling step by indicating that the physical portions J are cut in the final stage of the manufacturing steps (¶46). In the process of cutting described by Ishii et al., each finished circuit board is physically cut and separated from both of the surrounding support frame FR and adjacent dummy trace portion 2 (¶46 and ¶66).
While Kamei et al. discloses the general removal of the boards from the sheet structure as explained above, it does not explicitly describe a separate mechanical trimming cuts to isolate the inner insulation fields within the window layout. In contrast, Ishii et al. explicitly details that the individual board is mechanically severed at the coupling portions J to completely isolate it from the spent frame matrix and any surrounding dummy trace boundaries. It would be obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the fourth and fifth steps of Kamei et al. by using the explicit de-paneling and coupling steps of Ishii et al. The skilled artisan would be motivated to use the final mechanical trimming operation because severing the residual tabs and removing the extraneous structural/dummy borders is a necessary step in the production of cleanly singulated, self-contained wiring boards with specific geometric profiles.
Regarding Claim 4, Kamei et al. in view of Ishii et al. discloses the method of Claim 1, wherein in the second step, the insulating layer is formed in the pattern forming region and not formed in the opening forming region, and in the third step, the dummy pattern is formed on the supporting layer in the opening forming region according to Kamei et al. in ¶87, ¶89, ¶95-98 and depicted in FIG. 4b and FIG. 4c. In particular, Kamei et al. teaches that the insulating base layer 12 is formed only as a pattern corresponding to the functional suspension circuit board tracks while the plating resist allows the striated copper portions 3 to be electroplated directly on the base surface of the metal support board 18 within the opening zones.
Regarding Claim 5, Kamei et al. in view of Ishii et al. discloses the method of Claim 4, wherein in the fourth step, the entire supporting layer in the opening forming region is etched as supported by Kamei et al. in FIG. 4e, FIG. 5, ¶103-4, and ¶112-115 where the etchant used in the wet-etch step completely dissolves the exposed thickness of the metal supporting board 18 within the clearance groove 9 to create full through-hole openings.
Conclusion
9. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Higashitani et al. (US Pub. No. 2010/0032202 A1) is directed toward wiring a substrate and a method of manufacturing the wiring substrate (title).
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KEVIN SYLVESTER whose telephone number is (703)756-5536. The examiner can normally be reached Mon - Fri 8:15 AM to 4:30 PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Lin can be reached at (571)272-8902. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
11. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KEVIN SYLVESTER/Examiner, Art Unit 1794
/CIEL P CONTRERAS/Primary Examiner, Art Unit 1794
Prosecution Insights