DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because Figure 2, parts 100 and 300 recites the stages “DC to DC Prim.” [at 100] and “DC to DC Sec.” [at 300], which appears a typographical error of “DC to AC Prim.” [at 100] and “AC to DC Sec.” based on the Specification paragraph [0032] and conversion stages. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-7 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 2 and 4-7 of copending Application No. 18/569,220 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because:
Regarding claim 1, the copending Application discloses a submodule for a semiconductor transformer in single packaging with excellent performance of insulation and prevention against induction heating, comprising: a high voltage unit for matching high-voltage low-frequency AC power and converting the power into high-voltage AC power; a transforming unit for converting the high-voltage AC power into low-voltage AC power; and a low voltage unit for converting the low-voltage AC power into low-voltage DC power (see claim 1);
Regarding claim 2, the copending Application discloses the transforming unit has a partition wall of the high voltage unit and a partition wall of the low voltage unit removed (see claim 2);
Regarding claim 3, the copending Application discloses the transforming unit is placed between the high voltage unit and the low voltage unit by changing its size depending on voltage used in the high voltage unit and the low voltage unit or depending on potential difference between the high voltage unit and the low voltage unit (see claim 3);
Regarding claim 4, the copending Application discloses the transforming unit is placed between the high voltage unit and the low voltage unit by changing its size in a structure easy to change the size depending on physical constraints such as size of a transformer used in the transforming unit (see claim 4);
Regarding claim 5, the copending Application discloses the transforming unit is encompassed by an enclosure made of epoxy glass (see claim 5);
Regarding claim 6, the copending Application discloses a side cover of the transforming unit has vent holes (see claim 6);
Regarding claim 7, the copending Application discloses a side cover of the transforming unit near a side of the high voltage unit does not have vent holes (see claim 7).
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Zhirong et al. (CN 108923618; rejection based on English translation), hereinafter Zhirong.
Regarding claim 1, Zhirong discloses (see figures 1-6) a submodule for a semiconductor transformer in single packaging (figure 1, part submodule for a semiconductor transformer) with excellent performance of insulation and prevention against induction heating (figure 1, part through isolation stage 3) (page 5, paragraph 7; The rectifier, isolation, and inverter stages are directly connected into a single unit to achieve a highly integrated power electronic transformer), comprising: a high voltage unit (figure 5, part high voltage unit generated by IGBT1-4 and C1) for matching high-voltage low-frequency AC power (figure 5, part high voltage unit generated by IGBT1-4 and C1; at input a2/b2) and converting (figure 5, part high voltage unit generated by IGBT1-4 and C1) the power into high-voltage AC power (figure 5, part high voltage unit generated by IGBT1-4 and C1; output at a8/b8); a transforming unit (figure 5, part transforming unit generated by HFT) for converting the high-voltage AC power (figure 5, part high voltage unit generated by IGBT1-4 and C1; output at a8/b8) into low-voltage AC power (figure 5, part transforming unit generated by HFT; output at a11/b11); and a low voltage unit (figure 5, part low voltage unit generated by IGBT5-6 and C2) for converting the low-voltage AC power (figure 5, part transforming unit generated by HFT; output at a11/b11) into low-voltage DC power (figure 5, part low voltage unit generated by IGBT5-6 and C2; at output at a15/b15) (page 3 [paragraphs 4-7] and page 4 [paragraphs 1-6]; the high voltage module 2 includes: four high voltage insulated gate bipolar Transistors (ie, IGBT1 numbered 16 and IGBT2 17 numbered 17, IGBT 3 numbered 18, IGBT 4 numbered 19), high voltage DC capacitor C1 numbered 22, and high voltage composite busbar 25, of which four The high voltage insulated gate bipolar transistor and the high voltage DC capacitor 22 are disposed on the high voltage composite busbar 25. As shown in FIG. 5, the high voltage composite busbar 25 completes a2~a8, b2~b8 total 14 The connection of the electrical points is such that two high-voltage insulated gate bipolar transistors (IGBT3, IGBT4) are connected in parallel to form a high-frequency chopper in the isolation stage… the low voltage module 1 includes: two low voltage insulated gates. Bipolar transistors (ie, IGBT 5 numbered 20, IGBT 6 numbered 21), low voltage DC capacitor C2 numbered 23, and low voltage composite busbar 26, wherein the two low voltage insulated gate bipolar transistors ( That is, the IGBT 5 numbered 20, the IGBT 6 numbered 21, and the low voltage DC capacitor 23 are disposed on the low voltage composite busbar 26).
Regarding claim 2, Zhirong discloses everything claimed as applied above (see claim 1). Further, Zhirong discloses (see figures 1-6) the transforming unit (figure 5, part transforming unit generated by HFT) has a partition wall of the high voltage unit (figure 5, part high voltage unit generated by IGBT1-4 and C1) and a partition wall of the low voltage unit (figure 5, part low voltage unit generated by IGBT5-6 and C2) removed (figure 5, part no partition wall between transforming unit generated by HFT and high voltage unit generated by IGBT1-4 and C1/ low voltage unit generated by IGBT5-6 and C2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Zhirong et al. (CN 108923618; rejection based on English translation), hereinafter Zhirong.
Regarding claim 3, Zhirong discloses everything claimed as applied above (see claim 1). Further, Zhirong discloses (see figures 1-6) the transforming unit (figure 5, part transforming unit generated by HFT) is placed between the high voltage unit (figure 5, part high voltage unit generated by IGBT1-4 and C1) and the low voltage unit (figure 5, part low voltage unit generated by IGBT5-6 and C2); and voltage used in the high voltage unit (figure 5, part voltage used in the high voltage unit generated by IGBT1-4 and C1) and the low voltage unit (figure 5, part voltage used in the low voltage unit generated by IGBT5-6 and C2) or potential difference between the high voltage unit and the low voltage unit (figure 5, part potential difference between the high voltage unit generated by IGBT1-4 and C1 and the low voltage unit generated by IGBT5-6 and C2). However, Zhirong does not expressly disclose by changing its size depending on voltage used in the high voltage unit and the low voltage unit or depending on potential difference between the high voltage unit and the low voltage unit.
It would have been obvious matter of design choice to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the transforming unit (figure 5, part transforming unit generated by HFT) placed between the high voltage unit (figure 5, part high voltage unit generated by IGBT1-4 and C1) and the low voltage unit (figure 5, part low voltage unit generated by IGBT5-6 and C2) of Zhirong by changing its size depending on voltage used in the high voltage unit and the low voltage unit or depending on potential difference between the high voltage unit and the low voltage unit, in order to meet with the design requirements and obtain more accurate and efficient power conversion. Additional, the invention would perform equally well with the transforming unit as taught by Zhirong.
Regarding claim 4, Zhirong discloses everything claimed as applied above (see claim 1). Further, Zhirong discloses (see figures 1-6) the transforming unit (figure 5, part transforming unit generated by HFT) is placed between the high voltage unit (figure 5, part high voltage unit generated by IGBT1-4 and C1) and the low voltage unit (figure 5, part low voltage unit generated by IGBT5-6 and C2); and a transformer (figure 5, part HFT) used in the transforming unit (figure 5, part transforming unit generated by HFT). However, Zhirong does not expressly disclose by changing its size in a structure easy to change the size depending on physical constraints such as size of a transformer used in the transforming unit.
It would have been obvious matter of design choice to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the transforming unit (figure 5, part transforming unit generated by HFT) placed between the high voltage unit (figure 5, part high voltage unit generated by IGBT1-4 and C1) and the low voltage unit (figure 5, part low voltage unit generated by IGBT5-6 and C2) of Zhirong by changing its size in a structure easy to change the size depending on physical constraints such as size of a transformer used in the transforming unit, in order to meet with the design requirements and obtain more accurate and efficient power conversion. Additional, the invention would perform equally well with the transforming unit as taught by Zhirong.
Claims 5-7 are rejected under 35 U.S.C. 103 as being unpatentable over Zhirong et al. (CN 108923618; rejection based on English translation), hereinafter Zhirong, in view of Tianhong et al. (CN 2256601; rejection based on English translation), hereinafter Tianhong.
Regarding claim 5, Zhirong discloses everything claimed as applied above (see claim 1). Further, Zhirong discloses (see figures 1-6) the transforming unit (figure 5, part transforming unit generated by HFT) is encompassed by an enclosure (figure 4, part 4). However, Zhirong does not expressly disclose made of epoxy glass.
Tianhong teaches (see figures 1-6) the transforming unit is encompassed by an enclosure made of epoxy glass (figure 1) (paragraphs [0010]-[0011]; the composite type cabinet type transformer substation shell comprises (1)… in order to improve the heat-proof quality of shell, tank wall, case top and chamber door are the two-layer compound glass epoxy).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the transforming unit of Zhirong with the epoxy glass features as taught by Tianhong, because it provides more efficient transforming unit with the improvement of the heat-proof quality (paragraph [0011]).
Regarding claim 6, Zhirong and Tianhong teach everything claimed as applied above (see claim 5). Further, Zhirong discloses (see figures 1-6) a side cover of the transforming unit (figure 5, part transforming unit generated by HFT) has vent holes (figure 1, part vent holes in the middle area of the transforming unit generated by HFT).
Regarding claim 7, Zhirong and Tianhong teach everything claimed as applied above (see claim 5). Further, Zhirong discloses (see figures 1-6) a side cover of the transforming unit (figure 5, part transforming unit generated by HFT) near a side of the high voltage unit (figure 5, part voltage used in the high voltage unit generated by IGBT1-4 and C1) does not have vent holes (figure 1, part area of no holes at the high voltage unit 2).
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Zhirong et al. (CN 108923618; rejection based on English translation), hereinafter Zhirong, in view of Kim et al. (US 9,490,720), hereinafter Kim, and further in view of Xinhai et al. (CN 107578900; rejection based on English translation), hereinafter Xinhai.
Regarding claim 8, Zhirong discloses everything claimed as applied above (see claim 1). Further, Zhirong discloses (see figures 1-6) the low voltage unit (figure 5, part low voltage unit generated by IGBT5-6 and C2) and the low voltage AC power (figure 5, part transforming unit generated by HFT; output at a11/b11). However, Zhirong does not expressly disclose an inductor for matching the low voltage AC power; and a shield which surrounds the inductor by placing apart from the inductor in at least specific distance, and is made of a conductor with at least specified conductivity.
Kim teaches (see figures 1-3) the low voltage unit (figure 2B, part low voltage unit generated by 228, 224a/b, 232a/b and 234) includes: an inductor (figure 2B, part 228) for matching the low voltage AC power (figure 2B, part low voltage AC power output from 216).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the low voltage unit of Zhirong with the inductor features as taught by Kim, because it provides more efficient power conversion with more stability (column 4; lines 1-3).
Xinhai teaches (see figures 1-4) a shield (figures 1-4, part shield generated by 2 and 3) which surrounds the inductor (figures 1-4, part 1) by placing figures 1-4, part shield generated by 2 and 3) apart from the inductor in at least specific distance (figures 1-4, part 1), and is made of a conductor with at least specified conductivity (figures 1-4, part shield generated by 2 and 3; made of aluminum) (page 2; second paragraph; the hollow core inductor shielding device includes an upper shield 2 mounted above the hollow core inductor 1 and a lower shield 3 mounted below the hollow core inductor 1. The upper shield 2 and the lower shield 3 are made of aluminum).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the combination of Zhirong and Kim with the inductor shield features as taught by Xinhai and obtain the low voltage unit includes: an inductor for matching the low voltage AC power; and a shield which surrounds the inductor by placing apart from the inductor in at least specific distance, and is made of a conductor with at least specified conductivity, because it provides more efficient inductor with more protection insulation (page 1, paragraph 4).
Regarding claim 9, Zhirong, Kim and Xinhai teach everything claimed as applied above (see claim 8). However, Zhirong does not expressly disclose the specific distance is 10 mm or more.
Xinhai teaches (see figures 1-4) the specific distance is 10 mm or more (figures 1-4, part shield generated by 2 and 3) (page 2; paragraph 5; The equalizing ring on the upper shield 2/lower shield 3 is a solid ring with a radius of 25 mm. A cutting gap 4 corresponding to the number and direction of the cutting gaps 4 on the upper shield 2/lower shield 3 is respectively formed on the equalizing rings on the upper shield 2/lower shield 3).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the combination of Zhirong and Kim with the inductor shield features as taught by Xinhai, because it provides more efficient inductor with more protection insulation (page 1, paragraph 4).
Regarding claim 10, Zhirong, Kim and Xinhai teach everything claimed as applied above (see claim 8). However, Zhirong does not expressly disclose the specified conductivity is conductivity of aluminum.
Xinhai teaches (see figures 1-4) the specified conductivity is conductivity of aluminum (figures 1-4, part shield generated by 2 and 3; made of aluminum) (page 2; second paragraph; the hollow core inductor shielding device includes an upper shield 2 mounted above the hollow core inductor 1 and a lower shield 3 mounted below the hollow core inductor 1. The upper shield 2 and the lower shield 3 are made of aluminum).
It would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to configure the combination of Zhirong and Kim with the inductor shield features as taught by Xinhai, because it provides more efficient inductor with more protection insulation (page 1, paragraph 4).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Carlos O. Rivera-Pérez, whose telephone number is (571) 272-2432 and fax is (571) 273-2432. The examiner can normally be reached on Monday through Friday, 8:30 AM – 5:00 PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V. Tran can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/C.O.R. /
Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
Prosecution Insights