DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
The priority has been considered by the examiner. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The references cited in the Information Disclosure Statement (IDS) submitted on December 13, 2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered and accepted by the examiner.
Drawings
The drawing submitted on 12/13/2023, has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 72 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
With regard claim 72, the phrase limitation and a second partition wall portion having light reflectivity and overlapping the center of the mask portion in plan view is considered indefinite. Claim 72 depend of claim 1 and claim 1 don’t states “a first partition wall portion”. Is unclear if is a first partition wall portion too or is just a second partition wall portion.
For purpose of examination, the examiner interpreted “a second partition wall portion” as “a partition wall portion” or “a first partition wall portion”.
Appropriated correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 57, 58, 65 and 67 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nakamura et al. (JPH1146038, applicant submitted in the IDS, filed on December 13, 2023).
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Regarding claim 1, Nakamura disclose a semiconductor device, comprising:
a semiconductor substrate (see Annotation Figure 1, character 200) comprising a main substrate (see Annotation Figure 1, character 1, Abstract and paragraph [0013]), a base semiconductor part (see Annotation Figure 1, character 2, Abstract and paragraphs [0013 and 0020] and the reference called “n-type nitride semiconductor layer or n-contact layer”) located above the main substrate (see Annotation Figure 1, character 1), and a hole (see Annotation Figure 1, character 100, Abstract and paragraphs [0013 – 0015]) penetrating the main substrate (see Annotation Figure 1, character 1) in a thickness direction;
a compound semiconductor part (see Annotation Figure 1, character 201) located above the base semiconductor part (see Annotation Figure 1, character 2);
a first light reflector (see Annotation Figure 1, character 12, Abstract, paragraphs [0013 and 0016], the reference called “second-reflecting mirror” or second reflector”) located above the compound semiconductor part (see Annotation Figure 1, character 201); and
a second light reflector (see Annotation Figure 1, character 11, Abstract, paragraphs [0013 and 0016], the reference called “first-reflecting mirror” or first reflector”) disposed in the hole (see Annotation Figure 1, character 100), overlapping the first light reflector (see Annotation Figure 1, character 12), and below the first light reflector (see Annotation Figure 1, character 12).
Regarding claim 57, Nakamura disclose a first electrode (see Annotation Figures 1 and 2, character 9 and paragraph [0013], the reference called “p-electrode”) located above the compound semiconductor part (see Annotation Figure 1, character 201) and overlapping the first light reflector (see Annotation Figure 1, character 12) in plan view.
Regarding claim 58, Nakamura disclose a second electrode (see Annotation Figures 1 and 2, character 10 and paragraph [0013], the reference called “n-electrode”) located above the base semiconductor part (see Annotation Figure 1, character 200).
Regarding claim 65, Nakamura disclose the compound semiconductor part (see Annotation Figure 1, character 201) comprises a first type semiconductor layer (see Annotation Figure 1, character 3, paragraphs [0013 and 0021], the reference called “n-side cladding”), an active layer (see Annotation Figure 1, character 4, paragraphs [0013 and 0027]), and a second type semiconductor layer (see Annotation Figure 1, character 5, paragraphs [0013 and 0028], the reference called “p-side cladding layer”) in this order.
Regarding claim 67, Nakamura disclose the second light reflector (see Annotation Figure 1, character 11) is in contact with a void portion (see Annotation Figure 1) in the hole (see Annotation Figure 1, character 100).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 54 is rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (JPH1146038, applicant submitted in the IDS, filed on December 13, 2023) in view of Goldstein et al. (US 6,046,065).
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Regarding claim 54, Nakamura discloses the claimed invention except for the base semiconductor part does not include a bottom surface of the hole. Goldstein teaches a substrate (see Annotation Figure 1, character 300) include a main substrate (see Annotation Figure 1, character 1), a recess (see Annotation Figure 1, character 1) and a base semiconductor part (see Annotation Figure 1, character 2, the reference called “stop etching layer”), wherein the base semiconductor part does not include a bottom surface (see Annotation Figure 1, character 21) of the hole (see Annotation Figure 1, character 20, the reference called “recess”). However, it is well known in the art to apply and/or modify the base semiconductor part does not include a bottom surface of the hole as discloses by Goldstein in (see Annotation Figure 1 and column 5, lines 8 – 20). Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was to apply and/or modify the base semiconductor part does not include a bottom surface of the hole as suggested to the device of Nakamura changing the vertical distance allows for tailoring of the cavity length while changing the width allows for adjustment of the extent of the optical mode to overlap with the reflector. Notwithstanding, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claims 55, 56 and 68 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (JPH1146038, applicant submitted in the IDS, filed on December 13, 2023) in view of Hayafuji et al. (US 5,701,321).
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Regarding claims 55, 56 and 68, Nakamura discloses the claimed invention except for at least a part of the second light reflector is in contact with an inner surface of the main substrate and the second light reflector are located on a bottom surface of the hole and an inner surface of the main substrate continuously and the second light reflector is in contact with the lower surface of the main substrate. Hayafuji discloses a reflective layer (see Figure 1, character 16) in contact with the inner surfaces of the aperture (see Figure 1, character 15) and extending continuously across at least a portion of the aperture (see Figure 1, character 15) and the reflective layer (see Figure 16, character 16) is optically in contact with the lower surface of the substrate (see Figure 1, character 1). However, it is well known in the art to apply and/or modify the reflective layer in contact with the inner surfaces of the aperture and extending continuously across at least a portion of the aperture and the reflective layer is optically in contact with the lower surface of the substrate as discloses by Hayafuji in (see Figure 1). Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was to apply and/or modify the reflective layer in contact with the inner surfaces of the aperture and extending continuously across at least a portion of the aperture and the reflective layer is optically in contact with the lower surface of the substrate as suggested to the device of Nakamura, changing the vertical distance allows for tailoring of the cavity length while changing the width allows for adjustment of the extent of the optical mode to overlap with the reflector. Notwithstanding, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claim 59 and 70 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (JPH1146038, applicant submitted in the IDS, filed on December 13, 2023).
Regarding claim 59, Nakamura discloses the claimed invention except for the first electrode and the second electrode are aligned in a <1-100> direction or a <11-20> direction of the base semiconductor part. It would have been obvious to a person having ordinary skill in the art at the time the invention was to apply and/or modify the first electrode and the second electrode are aligned in a <1-100> direction or a <11-20> direction of the base semiconductor part to the device of Nakamura, to provide the desired angular beam divergence, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
In addition, the selection of electrodes aligned direction, it’s obvious because it is a matter of determining optimum process conditions by routine experimentation with a limited number of species of result effective variables. These claims are prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges or a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill or art) and In re Aller, 105 USPQ 233 (CCPA 1995) (selection of optimum ranges within prior art general conditions is obvious).
Note that the specification contains no disclosure of either the critical nature of the claimed [the first electrode and the second electrode are aligned in a <1-100> direction or a <11-20> direction of the base semiconductor part] or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen [the first electrode and the second electrode are aligned in a <1-100> direction or a <11-20> direction of the base semiconductor part] or upon another variable recited in a claim, the Applicant must show that the chosen [the first electrode and the second electrode are aligned in a <1-100> direction or a <11-20> direction of the base semiconductor part] are critical. In re Woodruf, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 70, Nakamura discloses the claimed invention except for a reflectance of the second light reflector is smaller than a reflectance of the first light reflector. It would have been obvious to a person having ordinary skill in the art at the time the invention was to apply and/or modify the a reflectance of the second light reflector is smaller than a reflectance of the first light reflector Nakamura to allowing light to pass through, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
In addition, the selection of reflectance of first and second reflectors, it’s obvious because it is a matter of determining optimum process conditions by routine experimentation with a limited number of species of result effective variables. These claims are prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges or a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill or art) and In re Aller, 105 USPQ 233 (CCPA 1995) (selection of optimum ranges within prior art general conditions is obvious).
Note that the specification contains no disclosure of either the critical nature of the claimed [a reflectance of the second light reflector is smaller than a reflectance of the first light reflector] or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen [a reflectance of the second light reflector is smaller than a reflectance of the first light reflector] or upon another variable recited in a claim, the Applicant must show that the chosen [a reflectance of the second light reflector is smaller than a reflectance of the first light reflector] are critical. In re Woodruf, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claims 60, 61, 63, 64 and 73 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (JPH1146038, applicant submitted in the IDS, filed on December 13, 2023) in view of Okagawa et al. (JPH11163402, applicant submitted in the IDS, filed on December 13, 2023).
Regarding claim 60, Nakamura disclose the base semiconductor part (see Annotation Figure 1, character 2) comprises a first portion (see Annotation Figure 1, character 2b), and a second portion (see Annotation Figure 1, character 2a) overlapping the second light reflector (see Annotation Figure 1, character 11) in a thickness direction.
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Nakamura discloses the claimed invention except for a threading dislocation density of one fifth or less of that of the first portion. Okagawa teaches a mask layer (see Figure 3, character M) and dislocation line control layer (see Figure 3, character S1). However, it is well known in the art to apply and/or modify the mask layer inside of the dislocation line control layer as discloses by Okagawa in (see Figure 1, Abstract and paragraph [0034]). Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was to apply and/or modify the mask layer inside of the dislocation line control layer as suggested to the device of Nakamura, to reduce dislocation.
It would have been obvious to a person having ordinary skill in the art at the time the invention was to apply and/or modify the a threading dislocation density of one fifth or less of that of the first portion the device of Nakamura to provide a minimum dislocation, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
In addition, the selection of threading dislocation density, it’s obvious because it is a matter of determining optimum process conditions by routine experimentation with a limited number of species of result effective variables. These claims are prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges or a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill or art) and In re Aller, 105 USPQ 233 (CCPA 1995) (selection of optimum ranges within prior art general conditions is obvious).
Note that the specification contains no disclosure of either the critical nature of the claimed [a threading dislocation density of one fifth or less of that of the first portion] or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen [a threading dislocation density of one fifth or less of that of the first portion] or upon another variable recited in a claim, the Applicant must show that the chosen [a threading dislocation density of one fifth or less of that of the first portion] are critical. In re Woodruf, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 61, Nakamura and Okagawa, Nakamura disclose the second portion (see Annotation Figure 1, character 2b) overlaps the first light reflector (see Annotation Figure 1, character 10) and the second light reflector (see Annotation Figure 1, character 11) in plan view.
Regarding claim 63, Nakamura and Okagawa, Nakamura disclose a first electrode (see Annotation Figures 1 and 2, character 9) located above the compound semiconductor part (see Annotation Figure 1, character 201) and overlapping the first light reflector (see Annotation Figures 1 and 2, character 12) in plan view; and
a second electrode (see Annotation Figures 1 and 2, character 10) located above the base semiconductor part (see Annotation Figure 1, character 2),
wherein the first electrode (see Annotation Figures 1 and 2, character 9) and the second electrode (see Annotation Figures 1 and 2, character 10) overlap the first portion (see Annotation Figures 1 and 2, character 2a) in plan view.
Regarding claim 64, Nakamura and Okagawa discloses the claimed invention except for a threading dislocation density in the second portion is 5×106/cm2 or less. It would have been obvious to a person having ordinary skill in the art at the time the invention was to apply and/or modify the a threading dislocation density in the second portion is 5×106/cm2 or less, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
In addition, the selection of threading dislocation density, it’s obvious because it is a matter of determining optimum process conditions by routine experimentation with a limited number of species of result effective variables. These claims are prima facie obvious without showing that the claimed ranges achieve unexpected results relative to the prior art range. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges or a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill or art) and In re Aller, 105 USPQ 233 (CCPA 1995) (selection of optimum ranges within prior art general conditions is obvious).
Note that the specification contains no disclosure of either the critical nature of the claimed [a threading dislocation density in the second portion is 5×106/cm2 or less] or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen [a threading dislocation density in the second portion is 5×106/cm2 or less] or upon another variable recited in a claim, the Applicant must show that the chosen [a threading dislocation density in the second portion is 5×106/cm2 or less] are critical. In re Woodruf, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Regarding claim 73, Nakamura disclose method for manufacturing a semiconductor device, comprising:
forming a base semiconductor part (see Annotation Figure 1, character 2, Abstract and paragraphs [0013 and 0020] and the reference called “n-type nitride semiconductor layer or n-contact layer”);
forming a compound semiconductor part (see Annotation Figure 1, character 201) above the base semiconductor part (see Annotation Figure 1, character 2);
forming a first light reflector (see Annotation Figure 1, character 12, Abstract, paragraphs [0013 and 0016], the reference called “second-reflecting mirror” or second reflector”) above the compound semiconductor part (see Annotation Figure 1, character 201);
forming a hole (see Annotation Figure 1, character 100, Abstract and paragraphs [0013 – 0015]) penetrating the main substrate in the thickness direction and overlapping the first light reflector in plan view; and
forming a second light reflector (see Annotation Figure 1, character 11, Abstract, paragraphs [0013 and 0016], the reference called “first-reflecting mirror” or first reflector”) in the hole (see Annotation Figure 1, character 100).
Nakamura discloses the claimed invention except for forming a base semiconductor part on a template substrate by an ELO method, the template substrate comprising a main substrate and a mask pattern. Okagawa teaches a mask layer (see Figure 3, character M), dislocation line control layer (see Figure 3, character S1) and substrate (see Figure 3, character 1). However, it is well known in the art to apply and/or modify the mask layer inside of the dislocation line control layer and they are located above the laser as discloses by Okagawa in (see Figure 1, Abstract and paragraphs [0022, 0025, 0034]. Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was to apply and/or modify the mask layer inside of the dislocation line control layer and they are located above the laser as suggested to the device of Nakamura, could be used to control the upward propagation direction of the dislocation lines in the layer, the mask layer can serves as a protective layer against the diffusion of impurities from the upper layer side to the lower layer than the mask layer and also could use to reduce dislocation.
Claims 62 and 69 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al. (JPH1146038, applicant submitted in the IDS, filed on December 13, 2023) in view of Okagawa et al. (JPH11163402, applicant submitted in the IDS, filed on December 13, 2023), further in view of Kuramoto et al. (JP2021-48427, applicant submitted in the IDS, filed on December 13, 2023).
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Regarding claim 62, Nakamura and Okagawa discloses the claimed invention except for an insulating film which is in contact with the upper surface of the compound semiconductor part, wherein the insulating film comprises an aperture portion overlapping the first light reflector, the second portion, and the second light reflector in plan view. Kuramoto teaches an insulating film (see Figure 1, character 14), wherein the insulating film (see Figure 1, character 14) comprises an aperture portion (see Figure 1, character 14A). However, it is well known in the art to apply and/or modify the an insulating film, wherein the insulating film comprises an aperture portion as discloses by Kuramoto in (see Figures 1 and 2 and paragraphs [0012 and 00106]). Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was to apply and/or modify the an insulating film, wherein the insulating film comprises an aperture portion as suggested to the device of Nakamura and Okagawa, insulating film could be used to provide insulation and prevent electricity from passing through, and the opening in the insulator could be used to allow electricity to pass to the gain medium.
Regarding claim 69, Nakamura and Okagawa, Nakamura disclose a first electrode (see Annotation Figures 1 and 2, character 9) located above the compound semiconductor part (see Annotation Figures 1 and 2, character 201).
Nakamura and Okagawa discloses the claimed invention except for the first electrode is in contact with the upper surface of the insulating film, and the first electrode is in contact with the compound semiconductor part in the aperture portion. Kuramoto teaches an insulating film (see Figure 1, character 14), wherein the insulating film (see Figure 1, character 14) comprises an aperture portion (see Figure 1, character 14A) and a translucent electrode (see Figure 1, character 15). However, it is well known in the art to apply and/or modify the an insulating film, wherein the insulating film comprises an aperture portion and a translucent electrode as discloses by Kuramoto in (see Figures 1 and 2 and paragraphs [0012 and 00106]). Therefore, it would have been obvious to a person having ordinary skill in the art at the time the invention was to apply and/or modify the an insulating film, wherein the insulating film comprises an aperture portion and a translucent electrode as suggested to the device of Nakamura and Okagawa, the insulating film could be used to provide insulation and prevent the passage of current; the aperture in the insulator could be used to allow the passage of current to the gain medium, and the electrode would serve as an electrical contact that allows current to flow through the semiconductor layers. The electrode is electrically in contact with the insulator.
Allowable Subject Matter
Claim 72 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claims 66, 71 and 72 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 66 recites a semiconductor device structure including the specific structure limitation of the compound semiconductor part comprises an aperture portion overlapping the first light reflector, the second portion, and the second light reflector in plan view, and a high-resistance portion surrounding the aperture portion and having a current resistance higher than that of the aperture portion, which is neither anticipated or neither disclosed nor suggested in any piece of available prior art, which is neither anticipated nor obvious over the prior art of record.
Claim 71 recites a semiconductor device structure including the specific structure limitation of a mask pattern located above the main substrate and comprising a mask portion and an opening portion; and a first partition wall portion having light reflectivity and overlapping the opening portion of the mask pattern in plan view, which is neither anticipated or neither disclosed nor suggested in any piece of available prior art, which is neither anticipated nor obvious over the prior art of record.
Claim 72 recites a semiconductor device structure including the specific structure limitation of a mask pattern located above the main substrate and comprising a mask portion and an opening portion; and a second partition wall portion having light reflectivity and overlapping the center of the mask portion in plan view, which is neither anticipated or neither disclosed nor suggested in any piece of available prior art, which is neither anticipated nor obvious over the prior art of record.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claims 74 and 75 are allowed.
The following is an examiner’s statement of reasons for allowance: Claim 74 recites a semiconductor device structure including the specific structure limitation of a seed portion; a mask pattern located above the seed portion and comprising a mask portion and an opening portion; and a second light reflector located below the seed portion, overlapping the first light reflector, and below the first light reflector, which is neither anticipated or neither disclosed nor suggested in any piece of available prior art, which is neither anticipated nor obvious over the prior art of record.
Claim 75 recites a method for manufacturing a semiconductor device including the specific steps limitation of forming a base semiconductor part on a template substrate by an ELO method, the template substrate comprising a main substrate and a mask pattern; removing the main substrate; and forming a second light reflector on an opposite side to a side on which the first light reflector is located with reference to the mask pattern, which is neither anticipated or neither disclosed nor suggested in any piece of available prior art, which is neither anticipated nor obvious over the prior art of record.
The prior art failed to teach or suggest a seed portion; a mask pattern located above the seed portion and comprising a mask portion and an opening portion; and a second light reflector located below the seed portion, overlapping the first light reflector, and below the first light reflector (claim 74) and/or forming a base semiconductor part on a template substrate by an ELO method, the template substrate comprising a main substrate and a mask pattern; removing the main substrate; and forming a second light reflector on an opposite side to a side on which the first light reflector is located with reference to the mask pattern (claim 75).
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Delma R. Forde whose telephone number is (571)272-1940. The examiner can normally be reached M - TH 7:00 AM - 4:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MinSun O Harvey can be reached at 571-272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Delma R Forde/Examiner, Art Unit 2828
/TOD T VAN ROY/Primary Examiner, Art Unit 2828
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