DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12-13-23 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 5, and 7 are rejected under 35 U.S.C. 102(a)(1) as being fully anticipated by Yamaji et al. (US20190107739).
Re claim 1, Yamaji et al. teaches for example in fig. 5-7 and 11, an optical modulation module (abstract) having a first main surface and a second main surface facing the first main surface (fig. 5, 11) and connected to a wiring substrate (32) by a connection substrate (33) on a side of the first main surface (fig. 5, 11), the optical modulation module comprising: a first-type semiconductor layer (31i) into which an impurity of a first polarity is injected (para. 0078); a second-type semiconductor layer (31c) into which an impurity having a second polarity different from the first polarity is injected (para. 0078); a first wiring layer electrically connected to the first-type semiconductor layer (para. 0050-0053, 0057, 0077-0078) and electrically connected to a terminal of the connection substrate on the first main surface (para. 0050-0053, 0057, 0077-0078); and a second wiring layer electrically connected to the second-type semiconductor layer (para. 0050-0053, 0057, 0077-0078) and in contact with the terminal on the first main surface (para. 0050-0053, 0057, 0077-0078).
Re claim 2, Yamaji et al. further teaches for example in fig. 5-7 and 11, a connection substrate (33) disposed on a side of the first main surface of the optical modulation module (fig. 5, 11); and a connection substrate having a terminal that electrically connects the optical modulation module and the connection substrate (para. 0050-0053, 0057).
Re claim 5, Yamaji et al. further teaches for example in fig. 5-7 and 11, on the first main surface, the first wiring layer serves as a ground electrode of the optical modulation module (para. 0050-0053), and the second wiring layer serves as an input electrode for inputting a signal from the wiring substrate via the connection substrate (para. 0050-0053).
Re claim 7, Yamaji et al. further teaches for example in fig. 5-7 and 11, the connection substrate is a high frequency substrate, and is a coplanar waveguide or a grounded waveguide (para. 0050-0053) including a plate-like substrate body (fig. 5) and a signal line formed on a surface of the substrate body (para. 0050-0053).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Yamaji et al. (US20190107739).
Re claim 8, supra claim 2. Furthermore, Yamaji et al. further teaches for example in fig. 5-7 and 11, a modulation electrode (abstract) that is at least one of a modulation laser (para. 0047).
But, Yamaji et al. fails to explicitly teach at least one of an electro-absorption type optical modulator, a Mach-Zehnder interference type optical modulator or a direct modulation laser and has a length of 150 m or less.
However, Yamaji et al. teaches a semiconductor laser diode (LD) with a semiconductor optical modulator. Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to vary the semiconductor laser diode, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering obvious design choices involves only routine skill in the art.
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify the teachings of Yamaji et al. in order to provide a modulation signal through a transmission line with short as possible to suppress degradation in signal quality at high frequencies, as taught by Yamaji et al. (para. 0005).
Allowable Subject Matter
Claims 3, 4, and 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art taken alone or in combination fails to anticipate or fairly suggest the limitations of the claims, in such a manner that a rejection would be proper. The prior art fails to teach a combination of all the claimed features as presented in dependent claims 3, 4, and 6.
Specifically regarding claim 3, Yamaji et al. (US20190107739) teaches the state of the art of an optical modulation module.
But, Yamaji et al. fails to explicitly teach a combination of all the claimed features including a signal is transmitted in one transmission direction, and the first wiring layer and the second wiring layer are arranged in a direction intersecting with the transmission direction on the first main surface, as claimed.
Specifically regarding claim 4, Yamaji et al. (US20190107739) teaches the state of the art of an optical modulation module.
But, Yamaji et al. fails to explicitly teach a combination of all the claimed features including a plurality of at least one of the first wiring layer and the second wiring layer is disposed on the first main surface, and the first wiring layer and the second wiring layer are adjacent to each other and alternately disposed on the first main surface, as claimed.
Specifically regarding claim 6, Yamaji et al. (US20190107739) teaches the state of the art of an optical modulation module.
But, Yamaji et al. fails to explicitly teach a combination of all the claimed features including on the first main surface, the first wiring layer is arranged with the second wiring layer put therebetween in a direction of the first main surface, as claimed.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH P MARTINEZ whose telephone number is (571)272-2335. The examiner can normally be reached Monday-Thursday 9am to 7pm PACIFIC.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Bumsuk Won can be reached at (571) 272-2713. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Joseph P Martinez/ Primary Examiner, Art Unit 2872 3-13-26