DETAILED ACTION
This Action is in response to Applicant’s amendment filed on March 11, 2026. Claims 7-12 are still pending in the present application. This Action is made NON-FINAL.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: TERMINAL, WIRELESS COMMUNICATION SYSTEM, AND COMMUNICATION METHOD FOR DETERMINING A CONTROL CHANNEL MONITORING OCCASION BASED ON SUBCARRIER SPACING.
The disclosure is objected to because of the following informality: On page 2 line 25, the acronym SSB needs to be spelled out. Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification
when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely
perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office Action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the
generic placeholder is not preceded by a structural modifier.
Such claim limitations are:
reception unit configured to receive … in claim 7; and
control unit configured to determine … in claim 7.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof which for:
reception unit, the specification disclose structure in the form of communication
device 1004 which could be a network controller or network card and include a switch, duplexer, and synthesizer (see figure 13 and paragraph 0104); and
control unit, the specification disclose structure in the form of processor 1001 (see
figure 13 and paragraph 0100).
If Applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C.
112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness
rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 7, 8, 11, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Nam et al. (US 2019/0098590 A1) in view of Intel Corporation (Discussion on initial aspects for extending NR up to 71 GHz), hereinafter “Intel”.
Consider claims 7 and 11, Nam et al. disclose a method and a terminal (user equipment
(UE) – abstract, figure 3, and paragraph 0005) comprising: a reception unit (RF transceiver 310 – figure 3) configured to receive information via a broadcast channel based on detection of a block including a synchronization signal and the broadcast channel (UE includes a transceiver configured to receive a synchronization signal/physical broadcasting channel (SS/PBCH) block of an index i from a base station (BS), wherein SS/PBCH block comprises a PBCH carrying master information block (MIB) – abstract, figure 18 step 1810, and paragraphs 0005 and 0201. The PBCH/MIB carries information for configuring Type0-PDCCH monitoring for system information – paragraphs 0102, 0107, 0148, and 0159); and a control unit (processor 340 – figure 3) configured to determine a monitoring occasion (PDCCH monitoring occasion / slot index n0) for monitoring a search space for receiving a control channel (Type0-PDCCH CSS / RMSI monitoring configuration), based on the information (determining a PDCCH monitoring occasion based on MIB/pdcch-ConfigSIB1 information – abstract “determine a slot index n0 as a sum of an offset value and [i∗M]… the index indicated in the MIB… configures PDCCH monitoring occasions… and cause the transceiver to decode a PDCCH in the slot index n0”, paragraph 0005 – processor determines n0 based on “a first value O determined according to an index indicated in the MIB, pdcch-ConfigSIB1, wherein the index configures physical downlink control channel (PDCCH) monitoring occasions” and paragraphs 0202 and 0203 - the UE determines a slot index n0, as a sum of an offset value and [i∗M]… the first value O can be determined according to an index indicated in the MIB, pdcch-ConfigSIB1, in which the index configures physical downlink control channel (PDCCH) monitoring occasions and the UE… performs PDCCH monitoring and decodes a PDCCH in the slot index n0), wherein
the control unit (processor 340 – figure 3) determines the monitoring occasion in a time domain (Nam et al. disclose Type0-PDCCH monitoring occasion timing relative to SS/PBCH blocks and teaches TDM/FDM multiplexing patterns for SS/PBCH and CORESET/RMSI transmission – see paragraph 0150 -whether the system utilizes the Frequency Division Multiplex (FDM) or Time Division Multiplex (TDM) may be indicated by means of ORMSI being 0 (FDM) or the number of slots corresponding to non-zero value (TDM) in the RMSI numerology, paragraph 0152 - If TDM is used, indication of slot and OFDM symbol locations for the CORESET burst set can be designed in a more flexible manner, paragraphs 0161-0165 describe one-to-one correspondence of SSB and CORESET timing and slots mapped with CORESET burst sets, figures 11 and 12 show slots mapped with CORESET burst sets offset from SSB timing. Thus, Nam et al. teach offsetting CORESET/PDCCH monitoring occasions from SSB transmissions in time), based on a parameter that has a different value depending on a subcarrier spacing in a second frequency band that is higher than a first frequency band (Nam et al. expressly teach determining the PDCCH monitoring occasion based on a parameter O and subcarrier spacing configuration μ – see paragraph 0005 - offset value is determined based on “a first value O determined according to an index indicated in the MIB, pdcch-ConfigSIB1” and “a second value μ indicated in the MIB, wherein the second value μ represents a subcarrier spacing configuration”, paragraph 0202 - The offset value is determined based on a first value O and a second value μ… the second value μ represents a subcarrier spacing configuration”, claim 4: when μ=0, offset value is one of 0, 2, 5, 7; when μ=1, offset value is one of 0, 4, 10, 14; when μ=2, offset value is one of 0, 10, 20, 30; and when μ=3, offset value is one of 0, 20, 40, 60. Nam et al. also distinguish different frequency ranges and different O values - claim 2: for a first frequency range, first value O is one of 0, 2, 5, and 7; and
for a second frequency range, first value O is one of 0, 2.5, 5, and 7.5.
However, Nam et al. does not expressly recite the words “does not overlap” with the block in a time domain and explicitly a second frequency band that is higher that a first frequency band.
In the same field of endeavor, Intel expressly teaches non-overlapping SSB and Type0-PDCCH CSS symbol placement in the higher-frequency context as Intel discloses for NR extension up to 71 GHz (page 2 - Proposal 1: “Support 480 kHz and 960 kHz SCS for SSB and initial BWP” and “Support Type0-PDCCH configuration indication in MIB of SSB for all supported SSB SCS.”, page 3 - Proposal 2: “Consider 480 kHz and 960 kHz SCS based SSB positions in a slot with SSB symbols 2, 3, 4, 5 and 9, 10, 11, 12 in a slot.” Proposal 3: “Type0-PDCCH CSS may utilize symbols {0,1} and {7,8} that correspond to SSB in the first half and second half of the slot.” Because Intel places Type0-PDCCH CSS in symbols {0,1} and {7,8}, while SSBs are placed in symbols {2,3,4,5} and {9,10,11,12}, Intel teaches a PDCCH monitoring occasion/search space arrangement that does not overlap the SSB block in the time domain). Intel also supplies the higher-frequency context required by the claim as Intel is directed to “extending NR up to 71 GHz”, discusses “NR operating in the 60 GHz band”, Proposal 1: “Support 480 kHz and 960 kHz SCS for SSB and initial BWP”, and Proposal 3: “Consider only same SCS for SSB and CORESET#0 (configured by MIB) for 480 and 960 kHz SCS.”
Thus, Nam et al. teach the O/μ-based subcarrier-spacing-dependent monitoring occasion parameter, and Intel teach applying such initial-access/Type0-PDCCH configurations in a higher second frequency band, namely 52.6–71 GHz / 60 GHz operation using 480 kHz and 960 kHz SCS.
Therefore, it would have been obvious to a person having ordinary skill in the art before
the effective filing date of the application to modify Nam et al.’s MIB/pdcch-ConfigSIB1-based Type0-PDCCH monitoring occasion determination for use in Intel’s high-frequency NR extension to 52.6–71 GHz using 480 kHz and 960 kHz SCS as Nam et al. provide the established mechanism for determining Type0-PDCCH monitoring occasions from MIB information using O, M, i, and μ. Intel identifies the need to support initial access at 52.6–71 GHz and expressly proposes supporting 480 kHz and 960 kHz SCS for SSB and initial BWP, with Type0-PDCCH configuration indicated in MIB. Intel further teach placing Type0-PDCCH CSS symbols so that they do not overlap the SSB symbols. A person having ordinary skill in the art would have been motivated to combine these teachings to preserve Nam et al.’s known MIB-based initial access procedure while adapting the PDCCH monitoring occasion timing to the larger subcarrier spacings and shorter slot durations of Intel’s high-frequency FR2-2 operation. The modification would predictably avoid collisions between SSB transmission and Type0-PDCCH monitoring while enabling reliable initial access in the higher-frequency band. This is a predictable use of prior-art elements according to their established functions and is supported by KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007), and MPEP § 2143.
Consider claim 8, and as applied to claim 7 above, Nam et al. do not specifically disclose that the second frequency band is a frequency band that is equal to or greater than 52.6 GHz and the subcarrier spacing is 480 kHz or 960 kHz.
In the same field of endeavor, Intel discloses NR operation in a higher frequency band extending up to 71 GHz (see title - Initial access aspects for extending NR up to 71 GHz) and operation in the 60 GHz band and the 52.6 GHz to 71 GHz range (see sections 1 and 2.1) and the subcarrier spacing is 480 kHz or 960 kHz (see page 2 Proposal 1 - Support 480 kHz and 960 kHz SCS for SSB and initial BWP and page 3 Proposal 3 - Consider only same SCS for SSB and
CORESET#0 (configured by MIB) for 480 and 960 kHz SCS).
Therefore, it would have been obvious to a person having ordinary skill in the art before
the effective filing date of the application to combine Nam et al.’s MIB-based Type0-PDCCH monitoring occasion determination with Intel’s 52.6–71 GHz high-frequency initial-access configuration. Nam et al. supply the known Type0-PDCCH monitoring framework and Intel identifies the need to support 480 kHz and 960 kHz SCS for initial access in 52.6–71 GHz operation. The motivation is to extend Nam et al.’s known monitoring occasion determination to newly deployed NR high-frequency bands while preserving initial access functionality.
Consider claim 12, Nam et al. disclose a wireless communication system (wireless network 100 - figure 1) comprising: a terminal (user equipment – abstract, figure 3, and paragraph 0005) ; and a base station (101-103 – figures 1 and 2 and paragraph 0006), wherein the base station
transmits a block including a synchronization signal and a broadcast channel, and transmits information via the broadcast channel (BS transmitting an SS/PBCH block including PBCH carrying MIB – paragraph 0006 - a base station (BS) for transmitting control information… transceiver configured to transmit the SS/PBCH block of the index i, and a PDCCH in the slot index n0 to a user equipment (UE), the SS/PBCH block comprises a PBCH carrying MIB, see also figure 18 and paragraphs 0201-0203), and the terminal
receives the information via the broadcast channel based on detection of the block (UE includes a transceiver configured to receive a synchronization signal/physical broadcasting channel (SS/PBCH) block of an index i from a base station (BS), wherein SS/PBCH block comprises a PBCH carrying master information block (MIB) – abstract, figure 18 step 1810, and paragraphs 0005 and 0201. The PBCH/MIB carries information for configuring Type0-PDCCH monitoring for system information – paragraphs 0102, 0107, 0148, and 0159); and
determines a monitoring occasion for monitoring a search space for receiving a control channel based on the information (determining a PDCCH monitoring occasion based on MIB/pdcch-ConfigSIB1 information – abstract “determine a slot index n0 as a sum of an offset value and [i∗M]… the index indicated in the MIB… configures PDCCH monitoring occasions… and cause the transceiver to decode a PDCCH in the slot index n0”, paragraph 0005 – processor determines n0 based on “a first value O determined according to an index indicated in the MIB, pdcch-ConfigSIB1, wherein the index configures physical downlink control channel (PDCCH) monitoring occasions” and paragraphs 0202 and 0203 - the UE determines a slot index n0, as a sum of an offset value and [i∗M]… the first value O can be determined according to an index indicated in the MIB, pdcch-ConfigSIB1, in which the index configures physical downlink control channel (PDCCH) monitoring occasions and the UE… performs PDCCH monitoring and decodes a PDCCH in the slot index n0), and the monitoring occasion is determined in a manner in which the monitoring occasion in a time domain (Nam et al. disclose Type0-PDCCH monitoring occasion timing relative to SS/PBCH blocks and teaches TDM/FDM multiplexing patterns for SS/PBCH and CORESET/RMSI transmission – see paragraph 0150 -whether the system utilizes the Frequency Division Multiplex (FDM) or Time Division Multiplex (TDM) may be indicated by means of ORMSI being 0 (FDM) or the number of slots corresponding to non-zero value (TDM) in the RMSI numerology, paragraph 0152 - If TDM is used, indication of slot and OFDM symbol locations for the CORESET burst set can be designed in a more flexible manner, paragraphs 0161-0165 describe one-to-one correspondence of SSB and CORESET timing and slots mapped with CORESET burst sets, figures 11 and 12 show slots mapped with CORESET burst sets offset from SSB timing. Thus, Nam et al. teach offsetting CORESET/PDCCH monitoring occasions from SSB transmissions in time), based on a parameter that has a different value depending on a subcarrier spacing in a second frequency band that is higher than a first frequency band (Nam et al. expressly teach determining the PDCCH monitoring occasion based on a parameter O and subcarrier spacing configuration μ – see paragraph 0005 - offset value is determined based on “a first value O determined according to an index indicated in the MIB, pdcch-ConfigSIB1” and “a second value μ indicated in the MIB, wherein the second value μ represents a subcarrier spacing configuration”, paragraph 0202 - The offset value is determined based on a first value O and a second value μ… the second value μ represents a subcarrier spacing configuration”, claim 4: when μ=0, offset value is one of 0, 2, 5, 7; when μ=1, offset value is one of 0, 4, 10, 14; when μ=2, offset value is one of 0, 10, 20, 30; and when μ=3, offset value is one of 0, 20, 40, 60. Nam et al. also distinguish different frequency ranges and different O values - claim 2: for a first frequency range, first value O is one of 0, 2, 5, and 7; and
for a second frequency range, first value O is one of 0, 2.5, 5, and 7.5.
However, Nam et al. does not expressly recite the words “does not overlap” with the block in a time domain and explicitly a second frequency band that is higher that a first frequency band.
In the same field of endeavor, Intel expressly teaches non-overlapping SSB and Type0-PDCCH CSS symbol placement in the higher-frequency context as Intel discloses for NR extension up to 71 GHz (page 2 - Proposal 1: “Support 480 kHz and 960 kHz SCS for SSB and initial BWP” and “Support Type0-PDCCH configuration indication in MIB of SSB for all supported SSB SCS.”, page 3 - Proposal 2: “Consider 480 kHz and 960 kHz SCS based SSB positions in a slot with SSB symbols 2, 3, 4, 5 and 9, 10, 11, 12 in a slot.” Proposal 3: “Type0-PDCCH CSS may utilize symbols {0,1} and {7,8} that correspond to SSB in the first half and second half of the slot.” Because Intel places Type0-PDCCH CSS in symbols {0,1} and {7,8}, while SSBs are placed in symbols {2,3,4,5} and {9,10,11,12}, Intel teaches a PDCCH monitoring occasion/search space arrangement that does not overlap the SSB block in the time domain). Intel also supplies the higher-frequency context required by the claim as Intel is directed to “extending NR up to 71 GHz”, discusses “NR operating in the 60 GHz band”, Proposal 1: “Support 480 kHz and 960 kHz SCS for SSB and initial BWP”, and Proposal 3: “Consider only same SCS for SSB and CORESET#0 (configured by MIB) for 480 and 960 kHz SCS.”
Thus, Nam et al. teach the O/μ-based subcarrier-spacing-dependent monitoring occasion parameter, and Intel teach applying such initial-access/Type0-PDCCH configurations in a higher second frequency band, namely 52.6–71 GHz / 60 GHz operation using 480 kHz and 960 kHz SCS.
Therefore, it would have been obvious to a person having ordinary skill in the art before
the effective filing date of the application to modify Nam et al.’s MIB/pdcch-ConfigSIB1-based
Type0-PDCCH monitoring occasion determination for use in Intel’s high-frequency NR extension to 52.6–71 GHz using 480 kHz and 960 kHz SCS as Nam et al. provide the established mechanism for determining Type0-PDCCH monitoring occasions from MIB information using O, M, i, and μ. Intel identifies the need to support initial access at 52.6–71 GHz and expressly proposes supporting 480 kHz and 960 kHz SCS for SSB and initial BWP, with Type0-PDCCH configuration indicated in MIB. Intel further teach placing Type0-PDCCH CSS symbols so that they do not overlap the SSB symbols. A person having ordinary skill in the art would have been motivated to combine these teachings to preserve Nam et al.’s known MIB-based initial access procedure while adapting the PDCCH monitoring occasion timing to the larger subcarrier spacings and shorter slot durations of Intel’s high-frequency FR2-2 operation. The modification would predictably avoid collisions between SSB transmission and Type0-PDCCH monitoring while enabling reliable initial access in the higher-frequency band. This is a predictable use of prior-art elements according to their established functions and is supported by KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007), and MPEP § 2143.
Claims 9 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Nam et al. (US 2019/0098590 A1) in view of Intel Corporation (Discussion on initial aspects for extending NR up to 71 GHz), hereinafter “Intel”, as applied to claim 7 above, and further in view of Si (US 2022/0263619 A1) (which has proper supporting disclosure available in at least provisional application 63/150,337).
Consider claims 9 and 10, and as applied to claim 7 above, Nam et al., as modified by Intel, fail to specifically disclose n0 that is a slot of the monitoring occasion is calculated based on a formula
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and the parameter is a parameter O in the formula (claim 9), wherein a value of the parameter O is 1.25 in a case where the subcarrier spacing is 480 kHz (claim 10).
In the same field of endeavor, Si discloses the same Type0-PDCCH CSS monitoring occasion framework. In particular, Si describes determining slot index n0 for Type0-PDCCH monitoring occasions using parameters including O and M as Si states, for example, a UE determines an index of slot n0 based on an expression of the form:
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O and M are provided by tables for PDCCH monitoring occasions.
O is a time domain offset used to determine slots including monitoring occasions for Type0-PDCCH (claim 9 - See paragraphs 0082-0086, 0095-0125, and Tables 12–16 of Si)
wherein a value of the parameter O is 1.25 in a case where the subcarrier spacing is 480 kHz (claim 10 – See paragraph 0091 Table 1).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to use Si’s explicit Type0-PDCCH monitoring formula with Nam et al.’s, as modified by Intel, Type0-PDCCH MIB/pdcch-ConfigSIB1 monitoring occasion framework. Nam et al. already teach that n0 is determined using O, M, i, and μ, and Si discloses the same Type0-PDCCH formula in the context of enhancement for higher frequency range. A person of ordinary skill in the art would have had a reason to use Si’s explicit formula to implement Nam et al.’s, as modified by Intel, monitoring occasion determination because Si provides a straightforward, standard-compatible expression for computing the same slot index n0 in the same NR Type0-PDCCH context. The combination merely applies a known formula for calculating the monitoring slot to Nam et al.’s, as modified by Intel, known monitoring occasion determination, yielding predictable results.
Response to Arguments
Applicant’s arguments filed on March 11, 2026 with respect to the rejection of claims 7, 11, and 12 under 35 USC 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of Nam et al. (US 2019/0098590 A1) in view of Intel Corporation (Discussion on initial aspects for extending NR up to 71 GHz).
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure.
Harada et al. (U.S. Patent Application Publication # 2021/0385800 A1) disclose a use terminal and radio communication method.
Harada et al. (U.S. Patent Application Publication # 2023/0050703 A1) disclose a terminal and base station.
Any inquiry concerning this communication or earlier communications from the Supervisory Patent Examiner (SPE) should be directed to Rafael Pérez-Gutiérrez whose telephone number is (571)272-7915. The examiner can normally be reached Monday-Thursday from 6:15 am to 4:15 pm EST.
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Rafael Pérez-Gutiérrez
R.P.G./rpg
/Rafael Pérez-Gutiérrez/Supervisory Patent Examiner, Art Unit 2642
August 6, 2026
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