DETAILED ACTION Claims 1-20 are presented for examination. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim (s) 1-6, 14, and 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Williams et al. (US PG Pub No. 2016/0048440 A1 ) in view of Gollub et al. (US PG Pub No. 2009/0300434 A1). Regarding claim 1, Williams teaches a method, implemented at a computer system that includes one or more processors associated with performance monitoring hardware configured to generate telemetry data related to performance of the one or more processors ([0004]) , for multiplexing access the performance monitoring hardware in different modes, the computer system having a hypervisor configured to manage a plurality of virtual machines including a management partition and one or more guest partitions ([0026]; [0040]) , each of which corresponds to one of the plurality of virtual machines, the method comprising: providing a first mode at the one or more guest partitions, the first mode enabling each of the one or more guest partitions to access the performance monitoring hardware for monitoring one or more virtual processors of a corresponding partition ( [0047], wherein hypervisor program is executed at second privilege level ; [0045], wherein performance monitoring circuits monitor performance of the processor ) ; and providing a second mode at the management guest partition , the second mode enabling the management guest partition to access the performance monitoring hardware for monitoring one or more virtual processors of another at least one of the one or more guest partitions ( [0047], wherein one or more guest operating systems are executed at a first privilege level ) , wherein: the first mode has a first priority ([0026]) , and the second mode has a second priority that is lower than the first priority ([0009], wherein the second privilege level is higher than the first privilege level) , such that when the first mode at a particular guest partition is enabled ([0026]) , the second mode associated with the particular guest partition at the management partition is automatically disabled ([002 6-2 7], wherein a disable control flag is set for the second privilege level which causes performance monitoring circuits configured by the first privilege level to continue operating when in the second privilege level ) . Williams does not teach the use of a management partition managed by the hypervisor. Gollub teaches the use of a hypervisor management partition that provides an operating system executing in a virtualized partition provided by the hypervisor ([0025]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to include the use of a management partition. One would be motivate by the desire to include a management partition having special privileges such being able to create new guest operating systems and being able to access the hardware directly as taught by Gollub . Regarding claim 2 , Williams teaches wherein the performance monitoring hardware includes one or more registers, and state of the performance monitoring hardware includes values stored in the one or more registers ([0044]) . Regarding claim 3 , Williams teaches wherein the one or more registers include at least one of (1) one or more CPU counter registers, or (2) one or more CPU configuration registers ([0053]) . Regarding claim 4 , Williams teaches wherein the one or more registers include one or more model-specific registers (MSRs). Regarding claim 5 , Williams teaches wherein the telemetry data includes at least one of (1) processor pipeline slot utilization, (2) stalls due to last level cache (LLC) misses, (3) shortage in hardware resources, (4) shortage in software dependencies, (5) thermal and power capping throttling events, (6) processor microcode revision, or (7) whether hyper-threading is on or off ([0004]) . Regarding claim 6 , Williams teaches further comprising providing a third mode at the management partition, the third mode enabling performance monitoring for processors of the computer system, wherein the third mode has a third priority that is lower than the second priority, such that when the first mode is enabled, the second mode and the third mode are automatically disabled, and when the second mode is enabled, the third mode is automatically disabled ([0043]) . Regarding claims 14, and 16-20, they are the system and storage device claims of claims 1-6 above. Therefore, they are rejected for the same reasons as claims 1-6 above. Allowable Subject Matter Claims 7-13 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. 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