DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/13/2023 and 03/28/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1-9 objected to because of the following informalities:
Claim 1 recites “the circuit” at multiple locations, it should recite “the time-continuous neural network electronic circuit”.
Claim 1 recites limitations “a first forward compartment configured for receiving and processing, in a first forward computing unit which first forward computing unit is comprised by the circuit …. based on an associated first set of forward weights stored in a first forward memory unit which first forward memory unit is comprised by the circuit”
“ii) a first feedback compartment configured for receiving and processing, in a first feedback computing unit which first feedback computing unit is comprised by the circuit …. based on the feedback signal and based on an associated first set of feedback weights stored in a first feedback memory unit which first feedback memory unit is comprised by the circuit”
“(iii) a first central compartment connected to said first forward and first feedback compartments and configured for receiving and processing, in a first central computing unit which first central computing unit is comprised by the circuit…”
“(iv) a second forward compartment configured for receiving and processing, in a second forward computing unit which second forward computing unit is comprised by the circuit… based on the second signal and based on an associated second set of forward weights stored in a second forward memory unit which second forward memory unit is comprised by the circuit”
“(v) a second feedback compartment configured for receiving and processing, in a second feedback computing unit which second feedback computing unit is comprised by the circuit…based on an associated second set of feedback weights stored in a second feedback memory unit which second feedback memory unit is comprised by the circuit”
“(vi) a second central compartment connected to said second forward and second feedback compartments and configured for receiving and processing, in a second central computing unit which second central computing unit is comprised by the circuit”
These above limitations are not clear, please rephrase for these limitations for clarity.
Claims 2-9 recites “A circuit according to claim…”, they should recite “The time-continuous neural network electronic circuit according to claim….”
Appropriate corrections are required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 at multiple locations recites “a second signal” such as “b) a second signal of the at least one second signal received from a hidden layer…”, “generate a second signal based on the third and fourth signals…”, and “a second signal of the at least one second signal from a neuron in the at least one hidden layer…” It is not clear if these “a second signal” are a same signal or different signals. Dependent claims 2-9 are also rejected because they inherit the deficiencies of the independent claim.
Appropriate corrections are required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-9 are rejected under 35 U.S.C. 103 as being unpatentable over Hasani (Interpretable Recurrent Neural Networks in Continuous-time Control Environments), in view of Binas et al (WO Published Patent Application No. 2017144372).
In regard to claim 1, Hasani teaches A time-continuous neural network electronic circuit implemented on analog hardware with device mismatch, comprising, an input layer; (Hasani, abstract, “This dissertation presents methods to address interpretation, stability and the overlooked properties of a class of intelligent algorithms, namely recurrent neural networks (RNNs), in continuous-time environments.” And pg. 13, Fig. 2.1,
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at least one hidden layer, wherein a first hidden layer of the at least one hidden layer is operatively connected to the input layer; (Hasani, pg. 13, Fig. 2.1,
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an output layer, wherein the output layer is operatively connected to a hidden layer of the at least one hidden layer; (Hasani, pg. 13, Fig. 2.1,
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a first control unit operably connected to the at least one hidden layer and the output layer; and (Hasani, pg. 14, 2.6, paragraph 1, ” RNN variants have achieved state-of-the-art performance in a large variety of applications, ranging from speech recognition [Robinson et al., 1996, Graves et al., 2013, Graves and Jaitly, 2014, Sak et al., 2014], autonomous robot control [OpenAI, 2018, Lechner et al., 2019), to natural language processing (NLP) [Mikolov et al., 201 1, Sutskever et al., 2011, Liu et al., 2014, Sutskever et al., 2014).”)
wherein the at least one hidden layer comprises a plurality of neurons for processing at least one first signal which the first hidden layer is configured to receive from the input layer; and (Hasani, Fig. 8.2,
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wherein the output layer comprises at least one output neuron for processing at least one second signal which the output layer is configured to receive from the at least one hidden layer; (Hasani, Fig. 8.2,
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, examiner would lie to point out that X and Y are the input that then are put through the hidden layer which then outputs Y1. Y1 is a signal that is then processed.)
wherein the first control unit is connected to the output layer and configured to receive a network output signal from the output layer, based on the seventh signals of the second central compartment of the output neuron, and wherein said first control unit is further individually connected to the first feedback compartment of each respective neuron in the hidden layer and to the second feedback compartment of the output neuron in the output layer and is configured to generate the feedback signal based on a comparison between said network output signal and a stored target signal. (Hasani, Fig. 8.2,
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, Examiner would like to point out that the output signal is Y1. This could be fed back multiple times until hitting the target signal, meaning that it is interpreted that this is the seventh signal. Also, the input is put through a hidden layer and fed back through until reaching said target signal.)
However, Hasani does not explicitly teach wherein, each respective neuron in the at least one hidden layer comprises,
a first forward compartment configured for receiving and processing, in a first forward computing unit which first forward computing unit is comprised by the circuit, a) the first signal received from the input layer in case of a neuron in the first hidden layer or b) a second signal of the at least one second signal received from a hidden layer of the at least one hidden layer in case of a neuron in a hidden layer different from the first hidden layer, and for generating a third signal based on the first signal or based on the second signal and based on an associated first set of forward weights stored in a first forward memory unit which first forward memory unit is comprised by the circuit,
(ii) a first feedback compartment configured for receiving and processing, in a first feedback computing unit which first feedback computing unit is comprised by the circuit, a feedback signal received from the first control unit, and for generating a fourth signal based on the feedback signal and based on an associated first set of feedback weights stored in a first feedback memory unit which first feedback memory unit is comprised by the circuit,
(iii) a first central compartment connected to said first forward and first feedback compartments and configured for receiving and processing, in a first central computing unit which first central computing unit is comprised by the circuit, the third signal from the first forward compartment and the fourth signal from the first feedback compartment, and configured to generate a second signal based on the third and fourth signals and each output neuron in the output layer comprises,
(iv) a second forward compartment configured for receiving and processing, in a second forward computing unit which second forward computing unit is comprised by the circuit, a second signal of the at least one second signal from a neuron in the at least one hidden layer, and for generating a fifth signal based on the second signal and based on an associated second set of forward weights stored in a second forward memory unit which second forward memory unit is comprised by the circuit,
(v) a second feedback compartment configured for receiving and processing, in a second feedback computing unit which second feedback computing unit is comprised by the circuit, the feedback signal, and for generating a sixth signal based on the feedback signal and based on an associated second set of feedback weights stored in a second feedback memory unit which second feedback memory unit is comprised by the circuit,
(vi) a second central compartment connected to said second forward and second feedback compartments and configured for receiving and processing, in a second central computing unit which second central computing unit is comprised by the circuit, the fifth signal from the second forward compartment and the sixth signal from the second feedback compartment, and configured to generate a seventh signal based on the fifth and sixth signals; and
Binas teaches wherein, each respective neuron in the at least one hidden layer comprises,
a first forward compartment configured for receiving and processing, in a first forward computing unit which first forward computing unit is comprised by the circuit, a) the first signal received from the input layer in case of a neuron in the first hidden layer or b) a second signal of the at least one second signal received from a hidden layer of the at least one hidden layer in case of a neuron in a hidden layer different from the first hidden layer, and for generating a third signal based on the first signal or based on the second signal and based on an associated first set of forward weights stored in a first forward memory unit which first forward memory unit is comprised by the circuit, (Binas, pg. 4, paragraph 3, “Typically, neural networks are configured for a particular task through a training process, optimising their input-output relation to approximate a given training dataset. The back-propagation algorithm is a two-stepped, supervised training method, consisting of a forward pass, in which the input stimulus is passed successively through all layers, and a backward pass, in which the output error of the network is computed and successively passed backwards through the layers. Thereby, as a consequence of the chain rule, the error gradients used to update the network parameters (weights) can be computed layer-wise and must not be computed for the whole network at once, dramatically simplifying the training process. In order for this to work, the transfer function f needs to be differentiable (in practice, piece wise differentiability is sufficient, as is the case for the often used rectified linear transfer function). Traditionally, neural networks have been implemented in digital general-purpose hardware using central processing units (CPUs) and graphics processing units (GPUs), using the same transfer function f for all somas.”)
(ii) a first feedback compartment configured for receiving and processing, in a first feedback computing unit which first feedback computing unit is comprised by the circuit, a feedback signal received from the first control unit, and for generating a fourth signal based on the feedback signal and based on an associated first set of feedback weights stored in a first feedback memory unit which first feedback memory unit is comprised by the circuit, (Binas, pg. 4, paragraph 3, “Typically, neural networks are configured for a particular task through a training process, optimising their input-output relation to approximate a given training dataset. The back-propagation algorithm is a two-stepped, supervised training method, consisting of a forward pass, in which the input stimulus is passed successively through all layers, and a backward pass, in which the output error of the network is computed and successively passed backwards through the layers. Thereby, as a consequence of the chain rule, the error gradients used to update the network parameters (weights) can be computed layer-wise and must not be computed for the whole network at once, dramatically simplifying the training process. In order for this to work, the transfer function f needs to be differentiable (in practice, piece wise differentiability is sufficient, as is the case for the often used rectified linear transfer function). Traditionally, neural networks have been implemented in digital general-purpose hardware using central processing units (CPUs) and graphics processing units (GPUs), using the same transfer function f for all somas.”)
(iii) a first central compartment connected to said first forward and first feedback compartments and configured for receiving and processing, in a first central computing unit which first central computing unit is comprised by the circuit, the third signal from the first forward compartment and the fourth signal from the first feedback compartment, and configured to generate a second signal based on the third and fourth signals and each output neuron in the output layer comprises, (Binas, pg. 4, paragraph 3, “Typically, neural networks are configured for a particular task through a training process, optimising their input-output relation to approximate a given training dataset. The back-propagation algorithm is a two-stepped, supervised training method, consisting of a forward pass [said first forward], in which the input stimulus is passed successively through all layers, and a backward pass [first feedback], in which the output error of the network is computed and successively passed backwards through the layers. Thereby, as a consequence of the chain rule, the error gradients used to update the network parameters (weights) can be computed layer-wise and must not be computed for the whole network at once, dramatically simplifying the training process. In order for this to work, the transfer function f needs to be differentiable (in practice, piece wise differentiability is sufficient, as is the case for the oftenused rectified linear transfer function). Traditionally, neural networks have been implemented in digital general-purpose hardware using central processing units [a first central compartment connected] (CPUs) and graphics processing units (GPUs), using the same transfer function f for all somas.”)
(iv) a second forward compartment configured for receiving and processing, in a second forward computing unit which second forward computing unit is comprised by the circuit, a second signal of the at least one second signal from a neuron in the at least one hidden layer, and for generating a fifth signal based on the second signal and based on an associated second set of forward weights stored in a second forward memory unit which second forward memory unit is comprised by the circuit, (Binas, pg. 4, paragraph 3, “Typically, neural networks are configured for a particular task through a training process, optimising their input-output relation to approximate a given training dataset. The back-propagation algorithm is a two-stepped, supervised training method, consisting of a forward pass, in which the input stimulus is passed successively through all layers, and a backward pass, in which the output error of the network is computed and successively passed backwards through the layers [in a second forward computing unit which second forward computing unit is comprised by the circuit]. Thereby, as a consequence of the chain rule, the error gradients used to update the network parameters (weights) can be computed layer-wise and must not be computed for the whole network at once, dramatically simplifying the training process. In order for this to work, the transfer function f needs to be differentiable (in practice, piece wise differentiability is sufficient, as is the case for the often used rectified linear transfer function). Traditionally, neural networks have been implemented in digital general-purpose hardware using central processing units (CPUs) and graphics processing units (GPUs), using the same transfer function f for all somas.” And pg. 6, paragraph 1, “The term current-mode refers to circuits that use both currents and voltages (like every electronic circuit) but where signals are represented as currents [a second signal], and voltages play only an incidental role. A part of the neural network 1 is schematically illustrated in Figure 4 showing two consecutive layers of somas 3 connected by a matrix of the synapses 5. A network is thus constructed by 10 connecting layers of soma circuits through matrices of programmable synapse circuits. Using the circuits shown in Figures 2 and 3, the output of a soma circuit 3 is communicated or encoded as a voltage (thick line in Figure 4) and passed to a column of synapse circuits 5, implementing multiplications by scalars.”)
(v) a second feedback compartment configured for receiving and processing, in a second feedback computing unit which second feedback computing unit is comprised by the circuit, the feedback signal, and for generating a sixth signal based on the feedback signal and based on an associated second set of feedback weights stored in a second feedback memory unit which second feedback memory unit is comprised by the circuit, (Binas, pg. 4, paragraph 3, “Typically, neural networks are configured for a particular task through a training process, optimising their input-output relation to approximate a given training dataset. The back-propagation algorithm is a two-stepped, supervised training method, consisting of a forward pass, in which the input stimulus is passed successively through all layers, and a backward pass, in which the output error of the network is computed and successively passed backwards through the layers [a second feedback compartment configured for receiving and processing, in a second feedback computing unit which second feedback computing unit is comprised by the circuit]. Thereby, as a consequence of the chain rule, the error gradients used to update the network parameters (weights) can be computed layer-wise and must not be computed for the whole network at once, dramatically simplifying the training process. In order for this to work, the transfer function f needs to be differentiable (in practice, piece wise differentiability is sufficient, as is the case for the often used rectified linear transfer function). Traditionally, neural networks have been implemented in digital general-purpose hardware using central processing units (CPUs) and graphics processing units (GPUs), using the same transfer function f for all somas.”)
(vi) a second central compartment connected to said second forward and second feedback compartments and configured for receiving and processing, in a second central computing unit which second central computing unit is comprised by the circuit, the fifth signal from the second forward compartment and the sixth signal from the second feedback compartment, and configured to generate a seventh signal based on the fifth and sixth signals; and (Binas, pg. 4, paragraph 3, “Typically, neural networks are configured for a particular task through a training process, optimising their input-output relation to approximate a given training dataset. The back-propagation algorithm is a two-stepped, supervised training method, consisting of a forward pass, in which the input stimulus is passed successively through all layers, and a backward pass, in which the output error of the network is computed and successively passed backwards through the layers. Thereby, as a consequence of the chain rule, the error gradients used to update the network parameters (weights) can be computed layer-wise and must not be computed for the whole network at once, dramatically simplifying the training process. In order for this to work, the transfer function f needs to be differentiable (in practice, piece wise differentiability is sufficient, as is the case for the often used rectified linear transfer function). Traditionally, neural networks have been implemented in digital general-purpose hardware using central processing units (CPUs) [a second central compartment connected to said second forward and second feedback compartments and configured for receiving and processing] and graphics processing units (GPUs), using the same transfer function f for all somas.”)
Hasani and Binas are related to the same field of endeavor (i.e. analog circuits). In view of the teachings of Binas, it would have been obvious for a person with ordinary skill in the art to apply the teachings of Binas to Hasani before the effective filing date of the claimed invention in order to use less power than the most efficient digital electronic neural networks. (Binas, pg. 2, paragraph 7, “The proposed analogue electronic neural network, when programmed properly, may achieve state-of-the-art performance while dissipating significantly less power than most efficient digital electronic neural networks.”)
In regard to claim 2, Hasani and Binas teaches the circuit of claim 1.
Binas further teaches wherein the first forward computing unit is configured to update the first set of forward weights based on the first, the second and the third signal, and wherein the second forward computing unit is configured to update the second set of forward weights based on the second, the fifth and the seventh signal. (Binas, pg. 6, paragraph 1, “The proposed method and the proposed analogue deep neural network 1 are next explained in more detail with reference to an example feed-forward network [first forward computing] implementation based on the soma and synapse circuits shown in Figures 2 and 3 respectively. In other words, a multilayer neural network 1 is created from current- 5 mode analogue circuits of Figures 2 and 3. The term current-mode refers to circuits that use both currents and voltages (like every electronic circuit) but where signals are represented as currents, and voltages play only an incidental role. A part of the neural network 1 is schematically illustrated in Figure 4 showing two consecutive layers of somas 3 connected by a matrix of the synapses 5. A network is thus constructed by 10 connecting layers of soma circuits through matrices of programmable synapse circuits. Using the circuits shown in Figures 2 and 3, the output of a soma circuit 3 is communicated or encoded as a voltage (thick line in Figure 4) and passed to a column of synapse circuits 5, implementing multiplications by scalars.”) and pg. 7, paragraph 2, “The summed current is then passed as input to the soma 3 of the next layer, which implements the non-linearity [the second forward computing unit]. The binary weight and sign of the synapse 5 is set by configuration bits w±, wi (the example circuit depicted presents a signed 3-bit synapse), whereby the actual values of the different possible weights are determined by the size of the transistors used. The soma circuit 3 performs the rectification and, depending on the input current, a non-linear compression of the input current.”)
Hasani and Binas are combinable for the same rationale as set forth above with respect to claim 1.
In regard to claim 3, Hasani and Binas teaches the circuit of claim 1.
Binas further teaches wherein the first feedback computing unit is configured to update the first set of feedback weights based on an approximation of an inverse of a function of the first set of forward weights and based on the feedback signal, and wherein the second feedback computing unit is configured to update the second set of feedback weights based on an approximation of an inverse of a function of the second set of forward weights and based on the feedback signal. (Binas, pg. 4, paragraph 3, “Typically, neural networks are configured for a particular task through a training process, optimising their input-output relation to approximate a given training dataset. The back-propagation algorithm is a two-stepped, supervised training method, consisting of a forward pass, in which the input stimulus is passed successively through all layers, and a backward pass, in which the output error of the network is computed and successively passed backwards through the layers. Thereby, as a consequence of the chain rule, the error gradients used to update the network parameters (weights) [first set of forward weights and based on the feedback signal,] can be computed layer-wise and must not be computed for the whole network at once, dramatically simplifying the training process. In order for this to work, the transfer function f needs to be differentiable (in practice, piece wise differentiability is sufficient, as is the case for the often used rectified linear transfer function). Traditionally, neural networks have been implemented in digital general-purpose hardware using central processing units (CPUs) and graphics processing units (GPUs), using the same transfer function f for all somas.” And pg. 6, paragraph 1, “The proposed method and the proposed analogue deep neural network 1 are next explained in more detail with reference to an example feed-forward network [first forward computing] implementation based on the soma and synapse circuits shown in Figures 2 and 3 respectively. In other words, a multilayer neural network 1 is created from current- 5 mode analogue circuits of Figures 2 and 3. The term current-mode refers to circuits that use both currents and voltages (like every electronic circuit) but where signals are represented as currents, and voltages play only an incidental role. A part of the neural network 1 is schematically illustrated in Figure 4 showing two consecutive layers of somas 3 connected by a matrix of the synapses 5. A network is thus constructed by 10 connecting layers of soma circuits through matrices of programmable synapse circuits. Using the circuits shown in Figures 2 and 3, the output of a soma circuit 3 is communicated or encoded as a voltage (thick line in Figure 4) and passed to a column of synapse circuits 5, implementing multiplications by scalars.”) and pg. 7, paragraph 2, “The summed current is then passed as input to the soma 3 of the next layer, which implements the non-linearity [the second forward computing unit]. The binary weight and sign of the synapse 5 is set by configuration bits w±, wi (the example circuit depicted presents a signed 3-bit synapse), whereby the actual values of the different possible weights are determined by the size of the transistors used. The soma circuit 3 performs the rectification and, depending on the input current, a non-linear compression of the input current.”)
Hasani and Binas are combinable for the same rationale as set forth above with respect to claim 1.
In regard to claim 4, Hasani and Binas teach the circuit of claim 1.
Hasani further teaches wherein the first control unit is embodied as a proportional and/or integrative and/or derivative controller. (Hasani, pg. 117, paragraph 2, “Here we propose an alternative machine-learning approach for automatically deriving neural network (NN) abstractions of integrated circuits [wherein the first control unit], up to a prescribed tolerance of the behavioral features”)
Hasani and Binas are combinable for the same rationale as set forth above with respect to claim 1.
In regard to claim 5, Hasani and Binas teach the circuit of claim 4.
Hasani further teaches wherein the first control unit is embodied as a neural network proportional and/or integrative and/or derivative controller. (Hasani, pg. 117, paragraph 2, “Here we propose an alternative machine-learning approach for automatically deriving neural network (NN) abstractions of integrated circuits [wherein the first control unit], up to a prescribed tolerance of the behavioral features”)
Hasani and Binas are combinable for the same rationale as set forth above with respect to claim 1.
In regard to claim 6, Hasani and Binas teach the circuit of claim 1.
Hasani further teaches further comprising a second control unit individually connected to each respective neuron in the at least one hidden layer and to each output neuron in the output layer, the second control unit being configured to generate and send a control signal to the at least one neuron in the at least one hidden layer and to the at least one output neuron in the output layer so as to modify activation parameters of the neural network. (Hasani, pg. 13, Fig. 8.2,
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, examiner would like to point out that in the table below the Fig. table 8.2 discusses the CPU being used.)
Hasani and Binas are combinable for the same rationale as set forth above with respect to claim 1.
In regard to claim 7, Hasani and Binas teach the circuit of claim 6.
Hasani further teaches wherein the control signal can be generated based on the second signal generated by the first central computing unit of the at least one neuron in the at least one hidden layer and/or based on the seventh signal generated by the second central computing unit of the at least one output neuron. (Hasani, Fi.g 8.2,
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Hasani and Binas are combinable for the same rationale as set forth above with respect to claim 1.
In regard to claim 8, Hasani and Binas teach the circuit of claim 6.
Hasani further teaches wherein said second control unit is embodied as a proportional and/or integrative and/or derivative controller. (Hasani, pg. 117, paragraph 2, “Here we propose an alternative machine-learning approach for automatically deriving neural network (NN) abstractions of integrated [integrative] circuits, up to a prescribed tolerance of the behavioral features”)
Hasani and Binas are combinable for the same rationale as set forth above with respect to claim 1.
In regard to claim 9, Hasani and Binas teach the circuit of claim 1.
Hasani further teaches comprising 'n' hidden layers, wherein 'n' is greater than two, and wherein the 'n' hidden layers are connected consecutively, and wherein the first hidden layer is operably connected to the input layer, and the 'nth' hidden layer is operably connected to the output layer. (Hasani, Fig. 2.1,
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Hasani and Binas are combinable for the same rationale as set forth above with respect to claim 1.
Conclusion
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/S.K.V./Examiner, Art Unit 2146 /USMAAN SAEED/Supervisory Patent Examiner, Art Unit 2146
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