Prosecution Insights
Last updated: April 19, 2026
Application No. 18/570,075

POWER CONVERSION DEVICE

Final Rejection §103
Filed
Dec 14, 2023
Examiner
NOVAK, PETER MICHAEL
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Mitsubishi Electric Corporation
OA Round
2 (Final)
88%
Grant Probability
Favorable
3-4
OA Rounds
2y 3m
To Grant
97%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
592 granted / 672 resolved
+20.1% vs TC avg
Moderate +9% lift
Without
With
+8.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
37 currently pending
Career history
709
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
51.7%
+11.7% vs TC avg
§102
20.7%
-19.3% vs TC avg
§112
20.2%
-19.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 672 resolved cases

Office Action

§103
DETAILED ACTION The instant action is in response to application 14 December 2023. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification. Response to Arguments The 112(b) rejection has been withdrawn. Applicants remarks on the merits have been considered but are moot for not considering the present references. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. (The claims have been condensed.) The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-10, 12, 19 (as best understood) are rejected under 35 U.S.C. 103 as being unpatentable over Tomoaki (JP 2014033553A) in view of Tao (US 20180062557 ) and Thurber (US 6169444). As to claim 1, Tomoaki discloses A power conversion device comprising: a rectification circuit which is connected to an AC power supply and rectifies input voltage from the AC power supply; a leg circuit connected to the rectification circuit and having an upper leg which includes a plurality of semiconductor elements (D1, D2) connected in series and a lower legwhich includes a plurality of semiconductor elements connected in series (S1, S2), the upper leg and the lower leg being connected in series, at least the plurality of semiconductor elements in the lower leg being switching elements (IGBTs are shown); a plurality of balance resistors connected in parallel to the semiconductor elements of the leg circuit (R1-R4): at least one charge/discharge capacitor connected between a connection point of the semiconductor elements in the upper leg and a connection point of the semiconductor elements in the lower leg (CF); a smoothing capacitor (CA) connected to an output of the leg circuit; Tomoaki does not teach and an inrush preventing circuit provided between the AC power supply and the leg circuit, and including a current limiting resistor, wherein: when charging speed of the charge/discharge capacitor is represented as a factor Kf and charging speed of the smoothing capacitor is represented as a factor K0, a factor Km, which is defined by Kf'/KO, is set to be smaller than 100 to suppress overvoltage applied on the semiconductor elements when the AC; power supply is turned on. Tao teaches an inrush preventing circuit (72, RY1) provided between the AC power supply (50) and the leg circuit (80), and including a current limiting resistor (72). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use the inrush resistor to prevent large currents from damaging the system. Thurber teaches wherein when charging speed of the charge/discharge capacitor is represented as a factor Kf and charging speed of the smoothing capacitor is represented as a factor K0, a factor Km, which is defined by Kf/K0, is set to be smaller than 100 to suppress overvoltage applied on the semiconductor elements when the AC power supply is turned on (Col. 3, lines 8-15 “the ratio for values between the flying capacitor and the output capacitor is typically about 1:20.”). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use a larger output capacitor to decrease the effects of voltage transients. As to claim 2, Tomoaki in view of Tao and Thurber explicitly teaches a diode rectifier (Tao, Fig. 1) and the plurality of balance resistors (Tomaki, Fig. 1) are connected in parallel to the respective semiconductor elements of the leg circuit. They do not explicitly teach teaches wherein the AC power supply is a single-phase AC power supply, the rectification circuit is a diode rectification circuit with only one arm. However, from three-phase to single phase is old and well known and therefore not patentable (see action mailed 22 Oct 2025). As to claim 3, Tomoaki in view of Tao and Thurber explicitly teaches, the rectification circuit is a bridge rectification circuit, and the plurality of balance resistors are connected in parallel to the respective semiconductor elements of the leg circuit. They do not explicitly teach wherein the AC power supply is a single-phase AC power supply. However, from three-phase to single phase is old and well known and therefore not patentable (see action mailed 22 Oct 2025). As to claim 4 Tomoaki in view of Tao and Thurber teaches wherein: the AC power supply is a single-phase AC power supply, the rectification circuit is a diode rectification circuit with only one arm, and the plurality of balance resistors includes:one common balance resistor connected in parallel to a series circuit of the semiconductor element at a lowermost position in the upper leg and the semiconductor element at an uppermost position in the lower leg, and individual balance resistors connected in parallel to each semiconductor element of the upper leg and each semiconductor element of the lower leg other than the semiconductor elements to which the common balance resistor is connected (this appears to be taught by R1-R4 in parallel with the semiconductor elements, with a common resistor being defined as two resistors in series). As to claim 5, Tomoaki in view of Tao and Thurber teaches teaches wherein the AC power supply is a single-phase AC power supply, the rectification circuit is a bridge rectification circuit, and the plurality of balance resistors includes one common balance resistor connected in parallel to the semiconductor element at a lowermost position in the upper leg and the semiconductor element at an uppermost position in the lower leg, and individual balance resistors connected in parallel to each semiconductor element of the upper leg and each semiconductor element of the lower leg other than the semiconductor elements to which the common balance resistor is connected ((this appears to be taught by R1-R4 in parallel with the semiconductor elements, with a common resistor being defined as two resistors in series).). As to claim 6, Tomoaki in view of Tao and Thurber teaches wherein the AC power supply is a three-phase AC power supply, the rectification circuit is a bridge rectification circuit, and the plurality of balance resistors are connected in parallel to the respective semiconductor elements of the leg circuit (see Fig 1 of Tomoaki). As to claim 7, Tomoaki in view of Tao and Thurber teaches wherein the AC power supply is a three-phase AC power supply ,the rectification circuit is a bridge rectification circuit, and the plurality of balance resistors includes one common balance resistor connected in parallel to the semiconductor element at a lowermost position in the upper leg and the semiconductor element at an uppermost position in the lower leg, and individual balance resistors connected in parallel to each semiconductor element of the upper leg and each semiconductor element of the lower leg other than the semiconductor elements to which the common balance resistor is connected (see image above, and explanation of claim 4). As to claims 8, 19 Tomoaki in view of Tao and Thurber teaches wherein the factor Km is set to be a constant not greater than twenty (see above). As to claim 9, Tomoaki in view of Tao and Thurber does not explicitly teach wherein the factor KM ise set to be a constant not greater than ten. However, routine optimization and experimentation (MPEP 2144.05) would cause one of ordinary skill to consider varying magnitudes of capacitors which would read on the claim language, especially if two capacitors of the same magnitude were put in parallel to further smooth the output. As such, this appears to be obvious. As to claim 10, Tomoaki in view of Tao and Thurber teaches wherein the AC power supply is a single-phase AC power supply, the rectification circuit is a diode rectification circuit in which two diodes are connected in series, one end of the single-phase AC power supply is connected to a connection point of the two diodes, and another end of the single-phase AC power supply is connected to a connection point of the upper leg and the lower leg of the leg circuit (this would be taught by going from 3 phase to 1 phase and is obvious as explained above). As to claim 12, Tomoaki in view of Tao and Thurber teaches wherein the factor Km is set to be a constant so that the overvoltage, applied on the semiconductor elements when the power supply is turned on, does not exceed a withstanding voltage of the semiconductor elements (Tao teaches shorting the overvoltage, and Thurber teaches Kin at a ratio 20). Allowable Subject Matter Claims 11,13-18, 20 allowed. The following is a statement of reasons for the indication of allowable subject matter: As to claims 11, the prior art fails to disclose: “wherein the factor Kf is obtained by a product of an average value of resistance values of the balance resistors and a capacitance value of the charge/discharge capacitor, and the factor KO is obtained by a product of a resistance value of the current limiting resistor and a capacitance value of the smoothing capacitor.” in combination with the additionally claimed features, as are claimed by the Applicant. Please note: while objected or allowed claims have been indicated, only the presented claims have been examined for compliance with form and 35 USC 112 consideration. As a reminder, claims that are dependent upon objected claims still require examination for form and 35 USC 112 issues even if they overcome 35 USC 102 and 103 rejections. Similarly, amendments incorporating allowable subject matter into independent claims requires reconsideration for dependent claim form and any possible 35 USC 112 issues that arise through amendments even if the 35 USC 102 and 103 rejections are overcome. As such, applicant is advised that while examiner can enter previously allowed claims or previously objected claims rewritten into independent form after final rejection, any other claims may not be entered. Conclusion Examiner has cited particular column, paragraph, and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M NOVAK whose telephone number is (571)270-1375. The examiner can normally be reached on 9AM-5PM,Monday through Thursday, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu Tran can be reached on 571-270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see https://ppair-my.uspto.gov/pair/PrivatePair. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /PETER M NOVAK/ Primary Examiner, Art Unit 2839
Read full office action

Prosecution Timeline

Dec 14, 2023
Application Filed
Oct 19, 2025
Non-Final Rejection — §103
Jan 14, 2026
Response Filed
Feb 08, 2026
Final Rejection — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
88%
Grant Probability
97%
With Interview (+8.6%)
2y 3m
Median Time to Grant
Moderate
PTA Risk
Based on 672 resolved cases by this examiner. Grant probability derived from career allow rate.

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