Prosecution Insights
Last updated: April 18, 2026
Application No. 18/571,690

INTEGRATED CIRCUITS INCLUDING FIRST AND SECOND POWER SUPPLY NODES FOR WRITING AND READING MEMORY CELLS

Non-Final OA §103
Filed
Dec 18, 2023
Examiner
VALENCIA, ALEJANDRO
Art Unit
2853
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Hewlett-Packard Development Company, L.P.
OA Round
4 (Non-Final)
42%
Grant Probability
Moderate
4-5
OA Rounds
2y 11m
To Grant
48%
With Interview

Examiner Intelligence

Grants 42% of resolved cases
42%
Career Allow Rate
567 granted / 1335 resolved
-25.5% vs TC avg
Moderate +6% lift
Without
With
+5.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 11m
Avg Prosecution
151 currently pending
Career history
1486
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
53.6%
+13.6% vs TC avg
§102
24.4%
-15.6% vs TC avg
§112
20.8%
-19.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1335 resolved cases

Office Action

§103
DETAILED ACTION Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-7, 10 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Linn et al. (2021/0162738) in view of Edelin et al. (2007/0236519). Regarding claim 1, Linn teaches the print cartridge circuitry (fig. 1B) component comprising an integrated circuit for association with a plurality of fluid actuation devices and comprising input signal contacts to receive input signals from a host printer, the integrated circuit comprising: a plurality of memory cells (fig. 1, items 102); a memory cell power node (fig. 4A, item 323) electrically coupled to the plurality of memory cells (see fig. 4A); a first power supply node (fig. 4A, item 350) to supply power to the plurality of memory cells to write data to the plurality of memory cells ([0038]); and a second power supply node (fig. 4A, item 344) to supply power to the plurality of memory cells to read data from the plurality of memory cells ([0034]-[0035]); a first voltage regulator (fig. 4A, item 308) to generate a memory-write voltage on the memory cell power node based on a first voltage received from the first power supply node to write data to the plurality of memory cells ([0045]); and a second voltage regulator (fig. 4A, item 306) to generate a memory-read voltage on the memory cell power node based on a second voltage received from the second power supply node to read data from the plurality of memory cells ([0043]), , and wherein the plurality of memory cells are readable with the first power supply node disabled ([0043]). Linn does not teach wherein the memory-write voltage is greater than the memory-read voltage. Edelin teaches this (Edelin, [0026]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the voltage scheme disclosed by Edelin to the circuit structure of Linn because doing so would amount to combining prior art elements according to known methods to yield predictable results. Regarding claim 2, Linn in view of Edelin teaches the print cartridge circuitry component of claim 1, wherein the second power supply node is to supply less than 7V and the first power supply node is to supply more than 9V (Edelin, [0026]). Regarding claim 3, Linn in view of Edelin teaches the print cartridge circuitry component of claim 1, wherein the plurality of memory cells are readable with the first power supply node disabled (Linn, see fig. 4A, [0043]). Regarding claim 4, Linn in view of Edelin teaches the print cartridge circuitry component of claim 1, the integrated circuit further comprising: a plurality of fluid actuation devices, wherein the first power supply node is to supply power to the plurality of fluid actuation devices (Linn, fig. 1B, items 126). Regarding claim 5, Linn in view of Edelin teaches the print cartridge circuitry component of claim 1, the integrated circuit further comprising: a logic circuit (fig. 4A, item 302), wherein the second power supply node is to supply power to the logic circuit (Linn, se fig. 4A). Regarding claim 6, Linn in view of Edelin teaches the print cartridge circuitry component of claim 5, wherein the logic circuit is to control reading and writing of data to the plurality of memory cells and firing of the plurality of fluid actuation devices (Linn, see fig. 1B). Regarding claim 7, Linn in view of Edelin teaches the print cartridge circuitry component of claim 1, wherein the first power supply node is to supply a first voltage and a first maximum current, wherein the second power supply node is to supply a second voltage and a second maximum current, and wherein the first voltage is greater than the second voltage, and the first maximum current is greater than the second maximum current (Edelin, [0026], Note that “maximum current” has not been defined in any way so as to limit the claim. Because voltage is proportional to current, and the first voltage is higher than the second voltage, as detailed in claim 1, the prior art teaches a first maximum current that is higher than a second maximum current). Regarding claim 10, Linn in view of Edelin teaches the print cartridge comprising an ink reservoir and an ink ejection die comprising the integrated circuit of claim 1 ([0048]). Regarding claim 23, Linn in view of Edelin teaches two different nodes supplying the claimed voltages (Linn, see fig. 4A). Claim(s) 8 is rejected under 35 U.S.C. 103 as being unpatentable over Linn in view of Edelin as applied to claim 7 above, and further in view of Schapendonk et al. (10,705,125). Regarding claim 8, Linn in view of Edelin teaches the print cartridge circuitry component of claim 7. Linn in view of Edelin does not teach a voltage isolation component between the first voltage regulator and the memory cell power node Schapendonk teaches an isolation component (Schapendonk, see fig. 7, Note that if voltage regulator 30 is taken to be analogous to the claimed first voltage regulator, voltage regulator 34 is taken to be analogous to the claimed second voltage regulator, and the input to functional circuit 116 is taken to be analogous to the claimed memory cell power node, switch SW1 serves as an isolation component between the first voltage regulator and the memory cell power node). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to add an isolation component of the type disclosed by Schapendonk to the device of Linn in view of Edelein because doing so would allow for isolation of the read and write voltages. Claim(s) 11 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Linn in view of Edelin as applied to claim 1 above, and further in view of Martin et al. (2017/0297328). Regarding claim 11, Edelin teaches the print cartridge circuitry component of claim 1 comprising: an off-die package comprising: the integrated circuit wherein the memory cells are off-die; and contacts connected to the first and second power supply nodes and a memory read/write data contact to transmit corresponding printer signals when installed, to supply power to, read, and write to the plurality of off-die memory cells, wherein the contacts are positioned to intercept signals from the host printer that would otherwise reach on-die memory cells of the fluid ejection die, such that the plurality of off-die memory cells receive power and data signals in place of the on-die memory cells, wherein the contacts are configured to align to corresponding signal contacts of the print cartridge when the off-die package is attached to the print cartridge, and wherein the contacts are configured to directly or indirectly connect to host printer contacts (Linn, [0025]-[0046]). While Linn in view of Edelin teaches all of the understood limitations of claim 11, Martin is now incorporated to disclose that circuits can be “off-die” (Martin, [0060], First, note that it is believed that the combination of Martin with Linn in view of Edelin teaches all claimed limitations. Note that the language of the claim is still broad and could mean any number of things. That is, whether the electronics of a cartridge are on the cartridge itself or removed from the cartridge, the components can physically be placed in contact with host computer hardware). It would have been obvious to one of ordinary skill in the art at the time of invention to apply all of the on-die components disclosed by Edelin in view of Lin to an off-die circuitry, as disclosed by Martin, because doing so would allow for repurposing of used circuitry. Regarding claim 12, Linn in view of Edelin and Martin teaches the print cartridge of claim 11, wherein the print cartridge is a used, refurbished, and/or refilled print cartridge (see claim 11 rejection. Note that “used, refurbished, and/or refilled” has no concrete meaning). Response to Arguments Applicant’s arguments with respect to claim(s) 1 have been considered but are moot in light of the new ground(s) of rejection. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEJANDRO VALENCIA whose telephone number is (571)270-5473. The examiner can normally be reached M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, RICARDO MAGALLANES can be reached at 571-202-5960. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALEJANDRO VALENCIA/Primary Examiner, Art Unit 2853
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Prosecution Timeline

Dec 18, 2023
Application Filed
Jul 15, 2025
Non-Final Rejection — §103
Oct 09, 2025
Response Filed
Oct 20, 2025
Final Rejection — §103
Nov 17, 2025
Response after Non-Final Action
Nov 28, 2025
Request for Continued Examination
Dec 03, 2025
Response after Non-Final Action
Mar 23, 2026
Non-Final Rejection — §103
Mar 31, 2026
Response Filed
Apr 07, 2026
Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12600127
INKJET ASSEMBLY, INKJET PRINTING APPARATUS AND INKJET PRINTING METHOD FOR USE IN PREPARATION OF DISPLAY COMPONENT
2y 5m to grant Granted Apr 14, 2026
Patent 12583238
PAPER SUPPLY CONTROL DEVICE
2y 5m to grant Granted Mar 24, 2026
Patent 12576644
RECORDING DEVICE AND METHOD OF CONTROLLING RECORDING DEVICE
2y 5m to grant Granted Mar 17, 2026
Patent 12570101
RECORDING DEVICE
2y 5m to grant Granted Mar 10, 2026
Patent 12558904
DROP-ON-DEMAND INK DELIVERY SYSTEMS AND METHODS WITH TANKLESS RECIRCULATION FOR CARD PROCESSING SYSTEMS
2y 5m to grant Granted Feb 24, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

4-5
Expected OA Rounds
42%
Grant Probability
48%
With Interview (+5.9%)
2y 11m
Median Time to Grant
High
PTA Risk
Based on 1335 resolved cases by this examiner. Grant probability derived from career allow rate.

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