DETAILED ACTION
Remarks
Applicant presents a communication dated 1 July 2026 responsive to the 1 April 2026 non-final Office action (the “Previous Action”).
With the communication, claims 1, 10, 12, 18 and 20-22 are amended and claim 9 is cancelled.
Claims 1-8, 10-14 and 18-22 are pending. Claims 1 and 18 are the independent claims.
Any unpersuasive arguments are addressed in the “Response to Arguments” section below.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular columns, paragraphs, figures and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
Applicant argues with respect to the § 112(d) of claim 20 that the claim has amended to address the rejection. (Remarks, p. 1 par. 4)
Examiner respectfully disagrees and points out that all limitations of the claim are still contingent and therefore do not further limit the parent claim of claim 20 under the broadest reasonable interpretation in light of the specification. See M.P.E.P. § 2111.04(II).
Applicant argues with respect to the § 101 rejection of claim 1 that it is not practical for the human mind with aid of pen and paper to generate the transition table and test cases claimed because a specification of a hardware device “contains thousands of hardware instructions, potentially giving rise to more than ten thousand entries” and “the scale and complexity” of this processing “plac[es] it firmly beyond the realm of mental processes. (Remarks, p. 7 par. 3).
Examiner respectfully points out that the claim only requires “a plurality” of instructions and therefore encompasses as few as two instructions, not necessarily thousands.
Applicant argues with respect to the § 101 rejection of claim 1 that the claim is directed to “specific technical solution” of generating a reduced set of test cases by identifying equivalent entries and eliminating equivalents, not “the abstract idea of testing or selecting.” (Remarks, p. 7 par. 4).
Examiner respectfully disagrees and submits that the claim was never rejected as being solely directed to testing or selecting. As set forth herein and in the Previous Action, generating a reduced set of test cases by identifying equivalent entries and eliminating equivalents, at least as claimed, is performable by the human mind with aid of pen and paper.
Applicant argues with respect to the § 101 rejection of claim 1 that the claimed transition table “constitutes a specific technical data structure and processing mechanism that improves the efficiency of hypervisor verification.” (Remarks, p. 7 last par. – p. 8 par. 1).
Examiner respectfully disagrees and submits that a human mind with aid of pen and paper is capable of creating a table. Furthermore, nothing in the specification suggests that mere use of a table results improves the efficiency of the computer or any other technology. Applicant’s arguments cannot take the place of evidence in the record. See M.P.E.P. § 716.01(c)(II).
Applicant argues with respect to the § 101 rejection of claim 1 that the apparatus of claim 1 provides an “80% reduction in the number of test cases required…while maintaining equivalent coverage” per page 4 of the specification. (Remarks, p. 8 par. 3).
Examiner respectfully points out in response that p. 4 of the specification only refers to “the proposed concept”, not necessarily the portions of the disclosed concept recited in claim 1. The specification is silent as what components or steps purportedly provide the benefits argued. Note too that an improvement in the abstract idea itself is not an improvement in technology. See M.P.E.P. § 2106.05(a)(II). And as set forth in the rejections, omitting equivalent entries of a table in the generation of test cases is part of the abstract idea itself.
Applicant argues with respect to the § 101 rejection of claim 1 that claim 1 is eligible “since the specific combination of the elements of claim 1 is not well-understood, routine, conventional activity in the field.” (Remarks, p. 8 par. 5).
Examiner respectfully disagrees and submits that additional elements can perhaps render a claim eligible if they are not well-understood, routine, conventional (see M.P.E.P. § 2106.05(d)), but the only additional elements of claim 1 are “user interface circuitry” and “processing circuitry.” Those elements do not render the claim eligible for the reasons set forth below. Note too that the “’novelty’ of any element or steps in a process, or even the process itself, is of no relevance in determining whether the subject matter of a claim falls within the § 101 categories of possible patentable subject matter.” Intellectual Ventures I v. Symantec Corp., 838 F.3d 1307, 1315, 120 USPQ2d 1353, 1358 (Fed. Cir. 2016) (quoting Diamond v. Diehr, 450 U.S. at 188–89, 209 USPQ at 9). See also M.P.E.P. § 2106.05(I).
Applicant argues with respect to the § 103 rejections of claim 1 that the bank machine of Apfelbaum is not a hardware device as claimed because the hardware device of claim 1 is “a CPU, GPU, etc.” and the bank machine of Apfelbaum is not associated operated in a hypervisor environment. (Remarks, p. 10 par. 1). Applicant adds that Apfelbaum does not teach entries determined bases on hardware instructions defined in the specification of the hardware device. (Remarks, p. 10 par. 2).
Examiner respectfully disagrees that the claim requires any of the devices argues and submits that the claim only requires a hardware device. And Apfelbaum is not cited as teaching a hardware device in a hypervisor or determining the entries based on hardware instructions defined in a specification of a hardware device. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant argues with respect to the § 103 rejection of claim 1 that Giomi does not teach determining entries based on hardware instructions defined in a specification of a hardware device because, according to Applicant, the entries of Giomi arise from the program structure, not from instructions defined by a device specification. (Remarks, p. 10 par. 4).
Examiner respectfully disagrees and submits that since the program structure specifies aspects of a hardware device, it is or includes a device specification as claimed.
Applicant argues with respect to the § 103 rejection of claim that “there is no teaching for combining Giomi with Apfelbaum” because one of ordinary skill would not consult a circuit synthesis tool when designing a hypervisor test case generation system. (Remarks, p. 11 last par. – p. 12 par. 1).
Examiner respectfully disagrees and submits that one of ordinary skill would have been motivated for the reasons set forth in the Previous Action and that Giomi is analogous art to the claimed invention because both the claimed invention and Giomi generate state machine descriptions of devices. There is also no requirement that an express written motivation appear in the prior art references. See M.P.E.P. § 2145(X)(A).
Applicant argues with respect to the § 103 rejection of claim 1 that Davis does not teach verification of hardware instructions of a hardware device in a hypervisor because claim 1 is “directed to verifying that the hypervisor correctly implements the handling of hardware instructions” such as “whether hypervisor correctly forwards, modifies, or handles the instruction” as required by the device specification and because Davis does not check compliance with any device specification. (Remarks, p. 11 par. 5).
Examiner respectfully disagrees and submits that the claim plainly refers to no verificaton of whether or not a hypervisor forwards, modifies or handles any instruction as argued. Limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Davis is not cited as teaching compliance with any specification either. Again, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references.
Applicant argues that one of ordinary skill would not have been motivated to combine Davis and Apfelbaum because Davis fails to teach verifying whether the hypervisor correctly implements the handling of hardware instructions. (Remarks, p. 11 last par. )
Examiner respectfully disagrees that Davis must teach verifying whether the hypervisor correctly implements the handling of hardware instructions in order to be combined with Apfelbaum. Verifying whether the hypervisor correctly implements the handling of hardware instructions is not required by the claim and is not asserted to be taught by Davis. One of ordinary skill would have been motivated for the reasons set below and in the Previous Action.
Applicant’s arguments with respect to the withdrawn rejections or objections are moot.
Applicant’s arguments with respect to the remaining claims by virtue of their similarity with claim 1, dependence from claim 1 or dependence from a similar claim are unpersuasive for the same reasons.
Allowable Subject Matter
Claim 13 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 101 set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim 20 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 101 and 112 set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 USC § 112
The Previous Action’s § 112 rejections are withdrawn in view of Applicant’s claim amendments unless reproduced herein below.
The following is a quotation of 35 U.S.C. 112(d):
(d) REFERENCE IN DEPENDENT FORMS.—Subject to subsection (e), a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
The following is a quotation of pre-AIA 35 U.S.C. 112, fourth paragraph:
Subject to the following paragraph [i.e., the fifth paragraph of pre-AIA 35 U.S.C. 112], a claim in dependent form shall contain a reference to a claim previously set forth and then specify a further limitation of the subject matter claimed. A claim in dependent form shall be construed to incorporate by reference all the limitations of the claim to which it refers.
Claim 20 is rejected under 35 U.S.C. 112(d) or pre-AIA 35 U.S.C. 112, 4th paragraph, as being of improper dependent form for failing to further limit the subject matter of the claim upon which it depends, or for failing to include all the limitations of the claim upon which it depends. Applicant may cancel the claim(s), amend the claim(s) to place the claim(s) in proper dependent form, rewrite the claim(s) in independent form, or present a sufficient showing that the dependent claim(s) complies with the statutory requirements.
As to claim 20, all of the limitations of this claim are contingent limitations, meaning they are not required under the broadest reasonable interpretation. See. M.P.E.P. § 2111.04(II). Since the claim requires no additional limitations, it does not further limit the claim on which it depends.
Claim Rejections - 35 USC § 101
The Previous Action’s § 101 rejection of claim 21 as being directed to a non-statutory signal is withdrawn in view of Applicant’s amendments of that claim.
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-8, 10-14 and 18-22 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception without significantly more.
As to claim 1, the claim recites:
An apparatus for generating test cases for a verification of hardware instructions of a hardware device in a hypervisor, the apparatus comprising interface circuitry and processing circuitry configured to:
generate a transition table based on a specification of the hardware device, the transition table comprising a plurality of entries, determined based on a plurality of hardware instructions defined in the specification of the hardware device, with each entry representing a change of a state of the hardware device in response to an event, wherein each entry of the transition table comprises a condition portion defining one or more conditions and a behavior portion defining the change of the state of the hardware device;
determine entries of the transition table that are equivalent, wherein two entries are determined to be equivalent if the condition portion and behavior portion of a first entry are equivalent to the condition portion and the behavior portion of a second entry;
generate a plurality of test cases based on the entries of the transition table, wherein at least one entry of the transition table is omitted in the generation of the test cases due to being equivalent to another entry of the transition table.
Although an apparatus is claimed (Step 1), under the broadest reasonable interpretation in light of the specification the above underlined elements recite a mental process because they describe a process performable by the human mind with aid of pen and paper. Note that the human mind with aid of pen and paper is capable of generating the claimed table and that per page 11 lines 20-25, generating test cases may merely comprise selecting certain instructions. The claim therefore recites an abstract idea. (Step 2A Prong 1).
None of the additional elements integrate the judicial exception into a practical application. (Step 2A Prong 2). Reference to an “apparatus comprising interface circuitry and processing circuitry” configured to only amounts to mere instructions to implement the abstract idea on a computer. See M.P.E.P. § 2106.05(f).
Looking at the claim limitations as an ordered combination yields the same conclusion as that reached when looking at the elements individually. Their collective function is merely to implement the abstract idea using a generic computer.
The claim does not include additional elements that amount to significantly more than the judicial exception for substantially the same reasons discussed above with respect to a practical application. (Step 2B).
As to claims 2-8 and 10-14, the features of these claims do not integrate the abstract idea into a practical application or amount to significantly more because they only further describe mental process, i.e., the abstract idea itself.
As to claim 18, the claim recites an abstract idea without significantly more for the substantially the same reasons as claim 1.
As to claims 19-22, the features of these claims do not integrate the abstract idea into a practical application or amount to significantly more because they only further describe mental process, i.e., the abstract idea itself.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 10-12, 18-19 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Apfelbaum et al. (US 6,694,290) (art of record – hereinafter Apfelbaum) in view of Davis (US 2021/0026758) (art of record – hereinafter Davis), Wang et al., “Behavior Model Construction for Client Side of Modern Web Applications” (art of record – hereinafter Wang) and Giomi (US 5,774,370) (art of record – hereinafter Giomi).
As to claim 1, Apfelbaum discloses an apparatus for generating test cases for a hardware device, the apparatus comprising interface circuitry and processing circuitry configured (e.g., Apfelbaum, col. 10 ll. 29-37: the techniques are implemented in computer programs executing on programmable computers that each include a processor [processing circuitry], a storage medium readable by the processor [i.e., via interface circuitry], at least one input device and at least one output device; col. 1 ll. 20-25; the software 100 detects 104 paths through the model states and transitions and generates 106 testing programs corresponding to each of the detected paths; col. 1 ll. 29-31]: as shown, model 108 includes states and transitions representing a bank machine system [hardware device]) to:
generate a transition table based on a specification of the hardware device, the transition table comprising a plurality of entries, with each entry representing a change of a state of the hardware device (e.g., Apfelbaum, col. 8 ll. 7-10: the table includes columns for specifying a source state and a destination state for each transition row. This enables an entire model to be displayed as one or more tables of rows. The equivalence of the model and the table enables a user to easily “flip” between the different model representations; col. 8 l. 65 – col. 9 l. 1: the rows in the table can be hand entered by a user. Alternatively, a user can import the data from an external source; col. 1 ll. 29-31: as shown, model 108 includes states and transitions representing a bank machine system [hardware device]) in response to an event; (e.g., Apfelbaum, Fig. 1 and associated text, col. 1 ll. 29-25: as shown model 108 includes states 110-116 and transitions 118-14 representing a bank machine system that dispenses case to customers entering an authorized PIN [and see figure, the machine enters a WITHDRAWAL state in response to receiving an OKPIN and an EXIT state when not receiving an OKPIN (!OKPIN)]) wherein each entry of the transition table comprises a condition portion defining one or more conditions and a behavior portion defining the change of the state of the hardware device; (e.g. Apfelbaum, col. 8 ll. 1-10, each row can further include predicate 254 and/or constraint expressions [condition portion] in another embodiment, the table also includes columns for specifying a source state and a destination state [behavior portion] for each transition row)
entries of the transition table (see immediately above)
one entry of the transition table and another entry of the transition table (see immediately above)
generate a plurality of test cases based on the entries of the transition table, (e.g., Apfelbaum, col. 8 ll. 7-10: the table includes columns for specifying a source state and a destination state for each transition row. This enables an entire model to be displayed as one or more tables of rows; col. 1 ll. 20-25; the software 100 detects 104 paths through the model states and transitions and generates 106 testing programs corresponding to each of the detected paths).
Apfelbaum does not explicitly disclose: verification of hardware instructions of a hardware device in a hypervisor; entries determined based on a plurality of hardware instructions defined in the specification of the hardware device, to determine entries of the transition table that are equivalent, wherein two entries are determined to be equivalent if the condition portion and the behavior portion of a first entry are equivalent to the condition portion and the behavior portion of a second entry; and wherein at least one entry of the transition table is omitted in the generation of the test cases due to being equivalent to another entry of the transition table.
However, in an analogous art, Davis discloses:
verification of hardware instructions of a hardware device in a hypervisor (e.g., Davis, par. [0025]: the hypervisor 110 can emulate a plurality of components for use by the virtual machine. For example, hypervisor 110 can include device emulation code that establishes and configured virtual devices such as super video graphics array (“SVGA”) 144, network interface controller (“NIC”) 146, and input-output memory management unit (“IOMMU”) 152. Virtual devices 140-152 listed above are only examples; par. [0021]: an example system for fuzz testing virtual devices).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the verification of Apfelbaum to include verification of hardware instructions of a hardware device in a hypervisor, as taught by Davis, as Davis would provide the advantage of a means of testing those types of hardware devices. (See Davis, abstract).
Further, in an analogous art, Wang discloses
to determine entries that are equivalent, (e.g., Wang, p. 120 left col. par. 2: to identify identical transitions in transition list T [each transition in the list being an entry, note too that even per p. 9 ll. 15-20 of the specification, any data structure is a table]) wherein two entries are determined to be equivalent if the condition portion and the behavior portion of a first entry are equivalent to the condition portion and the behavior portion of a second entry; (e.g., Wang, p. 118 Table 1, p. 120 left col. pars. 2-4: a transition [entry] t is made of up of src(t), trgt(t) [behavior portion] and associated event()[cond]/act, which is labled in terms of lbl(t) [condition portion]. To identify identical tansitions in Transition list T, we define identical transitions as follows: Transition t1 is identical to t2 iff src(t1) and src(t1), trgt(t1) and trgt (t2) and lbl(t1) and lbl(t2) are identical; p. 116 left col. Sec. 3.1 par. 2: src(t) and trgt(t) represent the source and target state of transition t; cond(t) describes the triggered conditions) and
wherein at least one entry is omitted in the generation of the test cases due to being equivalent to another entry (e.g., Wang, p. 113 left col. pars 2-3: Alimadadi proposes a graph-based behavior mode. Test cases generated from these models tend to be infeasible. Therefore, this paper defines a novel Client-side Behavior Model (CBM); p. 130 right col. Sec. 6.1 par. 1: the model-based testing approach is an effective way to derive test cases based on the models constructed; p. 120 right col. par. 2: identical [equivalent] transitions are removed from the transition list [i.e., an entry in that list is removed]. As a result, a transition set T’’ is obtained; p. 121 left col. par. 3: after processing all transitions involved in noise information, the final transition set T1 is formed. The original CBM has been built from the state set and transition set T1 [so the entry is omitted in the generation of the test cases because it has been removed from the set of transitions used to build the model, and the test cases are generated from that model]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the table entries representing transitions taught by Apfelbaum to include omitting at least one entry in the generation of the test cases due to being equivalent to another entry, wherein two entries are determined to be equivalent if the condition portion and the behavior portion of a first entry are equivalent to the condition portion and the behavior portion of a second entry, as taught by Wang, as Wang would provide the advantage of a means of optimizing the transition table. (See Wang, p. 125, right col. par. 2).
Further still, in an analogous art, Giomi discloses:
entries determined based on a plurality of hardware instructions defined in the specification of the hardware device; (e.g., Giomi, col. 1 ll. 24-25: descriptions of the circuit’s behavior using hardware description languages (HDL); col. 6 ll. 38-40: parsing the HDL description [hardware instructions] to create CFGs for each process of the HDL description; col. 6 ll. 49-51: for each of the identified CFGs, the invention extracts an FSM state transition table (STT); Fig. 20(a) and associated text, col. 11 ll. 24-25: FIG. 20(a) illustrates a process [see figure, it comprises VHDL instructions]; Fig. 20(e) and associated text, col. 12 ll. 16-17: FIG. 20(e) illustrates a simplified STT for the process of FIG. 20(a)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the table of Apfelbaum such that it is generated based on a plurality of hardware instructions defined in the specification of the hardware device, wherein the entries in the transition table are based on the plurality of hardware instructions, as taught by Giomi, as Giomi would provide the advantage of a means of extracting behavior of the tested device from a hardware description language specification of the device. (See Giomi, col. 2 ll. 25-35).
As to claim 3, Apfelbaum/Davis/Wang/Giomi discloses the apparatus according to claim 1 (see rejection of claim 1 above), Apfelbaum further discloses:
wherein each entry of the transition table defines one or more conditions to be met for affecting the state change and the corresponding change of the state of the hardware device (e.g., Apfelbaum, Fig. 12 and associated text, col. 8 ll. 1-3: each row can further include predicate 254 and/or constraint expressions 256 [see figure, a predicate expression such as TEST == 1 being a condition to be met]; col. 8 ll. 7-8: the table also includes columns specifying a source state and a destination state for each transition row (not shown); col. 8 ll. 26-30: assume the TEST model variable is set to “1” in FIG. 12. Under this assumption, PINS 001, 002, 003 and 004 represent eligible transitions because these transitions satisfy their associated predicate).
As to claim 10, Apfelbaum/Davis/Wang/Giomi discloses the apparatus according to claim 1 (see rejection of claim 1 above), but Apfelbaum/Davis/Wang does not explicitly disclose wherein each hardware instruction is related to one or more entries in the transition table.
However, in analogous art, Giomi discloses:
wherein each hardware instruction is related to one or more entries in the transition table (e.g., Giomi, col. 1 ll. 24-25: descriptions of the circuit’s behavior using hardware description languages (HDL); col. 6 ll. 38-40: parsing the HDL description [hardware instructions] to create CFGs for each process of the HDL description; col. 6 ll. 49-51: for each of the identified CFGs, the invention extracts an FSM state transition table (STT); Fig. 20(a) and associated text, col. 11 ll. 24-25: FIG. 20(a) illustrates a process [see figure, it comprises VHDL instructions]; Fig. 20(e) and associated text, col. 12 ll. 16-17: FIG. 20(e) illustrates a simplified STT for the process of FIG. 20(a)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the entries in a transition table taught by Apfelbaum such that each hardware instruction is related to one or more entries in the transition table, as taught by Giomi, as Giomi would provide the advantage of a means of extracting device behavior described in a hardware description language to the table. (See Giomi, col. 2 ll. 25-35).
As to claim 11, Apfelbaum/Davis/Wang/Giomi discloses the apparatus according to claim 1 (see rejection of claim 1 above), Apfelbaum further discloses entries of the transition table and the processing circuitry performs the method (see rejection of claim 1 above) but does not explicitly disclose wherein the processing circuitry is configured to determine classes of equivalent entries of the transition table, and to pick one entry of each class of equivalent entries for the plurality of test cases.
However, in an analogous art, Wang discloses:
to determine classes of equivalent entries, and to pick one entry of each class of equivalent entries for the plurality of test cases (e.g., Wang, p. 124 right col. par. 3: for each pair of transitions in transition set T1, if two transitions are determined to be equivalent [such a pair being an equivalence class], then one is removed from T1 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method performed by processing circuitry using entries of a transition table taught by Apfelbaum such that the method includes determining classes of equivalent entries, and to pick one entry of each class of equivalent entries for the plurality of test cases, as taught by Wang, as Wang would provide the advantage of a means of optimizing the transition table. (See Wang, p. 125, right col. par. 2).
As to claim 12, Apfelbaum/Davis/Wang/Giomi discloses the apparatus according to claim 11 (see rejection of claim 11 above), Apfelbaum does not explicitly disclose wherein the picked entry from each class is picked randomly.
However, in an analogous art, Wang discloses:
wherein the picked entry from each class is picked randomly (e.g., Wang, p. 123 right col. Sec. 4.2.2, equivalent transitions are identified by comparing each component of transitions and merged by reserving one [one entry from each class, see rejection of claim 1 above] randomly).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method performed by processing circuitry using entries of a transition table taught by Apfelbaum such that the method includes picking one entry randomly, as taught by Wang, as Wang would provide the advantage of a means of optimizing the transition table. (See Wang, p. 125, right col. par. 2).
As to claim 18, it is a method claim having limitations substantially the same as those of claim 1. Accordingly, it is rejected for substantially the same reasons.
As to claim 19, it is a method claim having limitations substantially the same as those of claim 11. Accordingly, it is rejected for substantially the same reasons.
As to claim 21, Apfelbaum/Davis/Wang/Giomi discloses the method of claim 18 (see rejection of claim 18 above), Apfelbaum further discloses:
a non-transitory machine-readable storage medium including program code, when executed, to cause a machine to perform the method (e.g., Apfelbaum, col. 10 ll. 45-53: each computer program is stored on a storage medium or device “(e.g., CD-ROM, embedded ROM, hard disk or magnetic diskette)” operating the compute when the medium is read by the computer to perform the procedures described in this document).
As to claim 22, it is a method claim having limitations substantially the same as those of claim 12. Accordingly, it is rejected for substantially the same reasons.
Claim 2 is rejection under 35 U.S.C. 103 as being unpatentable over Apfelbaum (US 6,694,290) in view of Davis (US 2021/0026758) in view of Wang (“Behavior Model Construction for Client Side of Modern Web Applications”) in view of Giomi (US 5,774,370) in further view of Bade et al. (US 2002/0059054) (art of record – hereinafter Bade).
As to claim 2, Apfelbaum/Davis/Wang/Giomi discloses the apparatus according to claim 1 (see rejection of claim 1 above) but does not explicitly disclose wherein the event comprises one of an execution of a pre-defined instruction, an occurrence of an exception and an occurrence of an external interrupt.
However, in an analogous art, Bade discloses:
wherein the event comprises one of an execution of a pre-defined instruction, an occurrence of an exception and an occurrence of an external interrupt (e.g., Bade, par. [0131]: the behavior as a process is described as a FSM. In a state, the Process takes the first signal from the queue. In the example, the interrupt controller waits for an interrupt signal, sent by one of the two peripheral devices; par. [0132]: from each state, a state transition to another state can only be made upon receiving signal generated by the environment or by another FSM).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the events of Apfelbaum/Davis/Wang/Giomi, such that an event comprises an occurrence of an external interrupt, as taught by Bade, as Bade would provide the advantage of a means of representing behavior of a device processing interrupts, such as an interrupt controller. (See Bade, par. [0131]).
Claims 4-8 are rejected under 35 U.S.C. 103 as beidevideng unpatentable over Apfelbaum (US 6,694,290) in view of Davis (US 2021/0026758) in view of Wang (“Behavior Model Construction for Client Side of Modern Web Applications”) in view of Giomi (US 5,774,370) in further view of Nishide et al. (US 2008/0288902) (art of record – hereinafter Nishide).
As to claim 4, Apfelbaum/Davis/Wang/Giomi discloses the apparatus according to claim 3 (see rejection of claim 3 above) but does not explicitly disclose wherein the one or more conditions are based on one or more variables, with each variable representing one of a register or memory cell, a bit field in a register or memory cell, a relation between two register or memory cells or between bit fields of two registers or memory cells, and a logical combination of two or more relations.
However, in an analogous art, Nishide discloses:
wherein the one or more conditions are based on one or more variables, with each variable representing one of a register or memory cell, a bit field in a register or memory cell, a relation between two register or memory cells or between bit fields of two registers or memory cells, and a logical combination of two or more relations (e.g., Nishide, Fig. 6 and associated text, par. [0074]: a corresponding signal “(for example, count)” is a value of a register used in the device under test [and see the code in the figure, the next state is WAIT_TRANS “if (count>=2’b11)”, i.e., on the condition that count has a particular value] ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the conditions of Apfelbaum to include conditions based on one or more variables comprising a register, as taught by Nishide, as Nishide would provide the advantage of a means of describing conditional behavior of a device under test that uses registers. (See Nishide, par. [0074]).
As to claim 5, Apfelbaum/Davis/Wang/Giomi/Nishide discloses the apparatus according to claim 4 (see rejection of claim 4 above) but does not explicitly disclose wherein a value of a variable is one of a hexadecimal value, an indicator representing a relation between two bit fields, registers or memory cells, and a binary value.
However, in an analogous art, Nishide discloses:
wherein a value of a variable is one of a hexadecimal value, an indicator representing a relation between two bit fields, registers or memory cells, and a binary value (e.g., Nishide, Fig. 6 and associated text, par. [0074]: a corresponding signal “(for example, count)” is a value of a register used in the device under test [and see the code in the figure, the next state is WAIT_TRANS “if (count>=2’b11)”, i.e., when the count variable has a value of “2’b11”, which, in Verilog, is a binary value as indicated by the letter b]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the conditions of Apfelbaum to include conditions based on one or more variables comprising a register, as taught by Nishide, as Nishide would provide the advantage of a means of describing behavior of a device that transitions states based on binary values. (See Nishide, par. [0079]).
As to claim 6, Apfelbaum/Davis/Wang/Giomi/Nishide discloses the apparatus according to claim 4 (see rejection of claim 4 above), Apfelbaum further discloses:
wherein a relation is one of equal, greater than or smaller than (e.g., Apfelbaum, Fig. 2 and associated text [see figure the predicate for one row of the transition table is “TEST==1”, i.e., TEST being equal to 1]).
As to claim 7, Apfelbaum/Davis/Wang/Giomi/Nishide discloses the apparatus according to claim 4 (see rejection of claim 4 above) Apfelbaum further discloses entries of the transition table and corresponding change of the state of the hardware (see rejection of claim 1 above) but Apfelbaum does not explicitly disclose wherein two entries of the transition table are determined to be equivalent if the one or more conditions and the corresponding change of the state of the hardware are equivalent.
However, in an analogous art, Wang discloses:
wherein two entries are determined to be equivalent if the one or more conditions and the corresponding change of the state are equivalent (e.g., Wang. p. 115 left col. Sec. 3.1 par. 2: a transition t is denoted by a t-tuple <src,event,cond,act,trgt>, where src(t) and trgt(t) represent the source and target state of transition t, cond(t) describes the triggered conditions; p. 120 pars. 2-4: a transition is made of src(t), trgt(t), and associated event ()[cond]/act, which is labeled in terms of lbl(t). We define identical transitions as follows: transition t1 is identical to t2 iff src(t1) and src(t2), trgt(t1) and trgt(t2), and lbl(t1) and lbl(t2) are identical. Here, lbl(t1) and lbl(t2) being identical means that every member of them is the same; p. 120 right col. par. 1: two transitions are judged to be different if as long as one component of them is different).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the table entries representing transitions of a hardware device taught by Apfelbaum to include determining entries as equivalent if the one or more conditions and the corresponding change of state of are equivalent, as taught by Wang, as Wang would provide the advantages of a means of identifying equivalent transitions and a means optimizing the transition table. (See Wang, p. 120 left col. pars. 2-4 and p. 125, right col. par. 2).
As to claim 8, Apfelbaum/Davis/Wang/Giomi/Nishide discloses the apparatus according to claim 4 (see rejection of claim 4 above), but Apfelbaum does not explicitly disclose wherein a condition defines either a value of a variable or that the variable is irrelevant for the entry, wherein two entries are determined to be equivalent if a first of the two entries comprises a condition that defines that a given variable is irrelevant and if a second of the two entries either comprises the condition that defines that the given variable is irrelevant or the second entry lacks a condition that is based on the given variable.
However, in an analogous art, Wang discloses:
wherein a condition defines either a value of a variable or that the variable is irrelevant for the entry, wherein two entries are determined to be equivalent if a first of the two entries comprises a condition that defines that a given variable is irrelevant and if a second of the two entries either comprises the condition that defines that the given variable is irrelevant or the second entry lacks a condition that is based on the given variable (e.g., Wang. p. 115 left col. Sec. 3.1 par. 2: a transition t is denoted by a t-tuple <src,event,cond,act,trgt>, where src(t) and trgt(t) represent the source and target state of transition t, cond(t) describes the triggered conditions; p. 118 Table 1, p. 120 right col. par. 1: two transitions are judged to be different if as long as one component of them is different [And see Table, the conditions include values of variables such as username.value or password.value. Any variables not part of the condition shown are thus defined by the condition as irrelevant, meaning two entries must each not include the same variables from their conditions, i.e., define those variables as irrelevant, to be equivalent]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the table entries of Apfelbaum such that a condition defines either a value of a variable or that the variable is irrelevant for the entry, and two entries are determined to be equivalent if a first of the two entries comprises a condition that defines that a given variable is irrelevant and if a second of the two entries either comprises the condition that defines that the given variable is irrelevant or the second entry lacks a condition that is based on the given variable, as taught by Wang, as Wang would provide the advantage of a means of optimizing the transition table. (See Wang, p. 125, right col. par. 2).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Apfelbaum (US 6,694,290) in view of Davis (US 2021/0026758) in view of Wang (“Behavior Model Construction for Client Side of Modern Web Applications”) in view of Giomi (US 5,774,370) in further view of Liao et al. (US 2018/0144134) (art of record – hereinafter Liao).
As to claim 14, Apfelbaum/Davis/Wang/Giomi discloses the apparatus according to claim 1, (see rejection of claim 1 above) wherein the hardware device is a central processing unit and the hardware instructions are central processing unit instructions.
However, in an analogous art, Liao discloses:
wherein the hardware device is a central processing unit and the hardware instructions are central processing unit instructions (e.g., Liao, Fig. 2 and associated text, par. [0029]: virtual components of the virtual machine management device VMM. The virtual components includes: virtual processor VCPU; par. [0031]: these virtual components are implemented by software simulation technology. The software can implement the interfaces and the functions similar to the underlying hardware. For example, the software can simulate multiple virtual processors VCPU).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the hardware device and hardware instructions of Apfelbaum/Davis such that the hardware device is a central processing unit and the hardware instructions are central processing unit instructions, as taught by Liao, as Liao would provide the advantage of a means for a hypervisor to simulate a CPU. (See Liao, par. [0029]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/TODD AGUILERA/Primary Examiner, Art Unit 2192
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