DETAILED ACTION
This non-final rejection is responsive to communication filed December 20, 2023. Claims 1-7 are currently amended. Claim 9 has been added. Claims 1-9 are pending in this application.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/20/23 and 4/29/25 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The abstract of the disclosure is objected to because it exceeds 150 words. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gelashvili (US 2021/0201124 A1).
With respect to claims 1, 8 and 9, Gelashvili teaches a convolutional neural network inference processing device that performs processing in a convolutional neural network (paragraph 75) including a plurality of convolution layers and a residual layer that adds intermediate data related to the plurality of convolution layers (paragraph 135), as an addition target to a processing result by the plurality of convolution layers for each tile that is data obtained by dividing input data into a predetermined size (paragraphs 28 and 135), the convolutional neural network inference processing device comprising:
a memory (paragraphs 79-80): and
at least one processor coupled to the memory (paragraph 76), the at least one processor being configured to:
store the intermediate data (paragraphs 32, 38-40, 62, and 68);
store inconsistency data that is data at a portion at which there is inconsistency between the processing result and the intermediate data (paragraphs 35, 57, 69, 103, and 110);
store past layer data that is an addition target in a residual layer generated using inconsistency data related to the tile for which processing has been performed in the past and the intermediate data (paragraphs 88 and 135); and
perform processing by the plurality of convolution layers and processing by the residual layer that adds the past layer data to the processing result (paragraphs 135 and 145-146).
The examiner would like to note that all neural network related data has to be stored in some fashion for the neural network to function. The storing limitations are broadly claimed such that any convolutional neural network inference processing device is capable of storing claimed data. Further, the data does not appear to be used to affect functionality. Nonetheless, the examiner has applied art related to the types of stored data.
With respect to claim 2, Gelashvili teaches the convolutional neural network inference processing device according to claim 1, wherein the at least one processor is further configured to store, in the memory, data of a portion in contact with an adjacent tile in the intermediate data as margin data, combine the margin data stored in the memory with the intermediate data, and perform processing by a convolution layer related to the plurality of convolution layers (Gelashvili, paragraphs 32, 38-40, 62, and 68).
With respect to claim 3, Gelashvili teaches the convolutional neural network inference processing device according to claim 2, wherein the at least one processor performs processing by the convolution layer by expanding a dimension of the intermediate data by combining the margin data with the intermediate data (Gelashvili, paragraphs 51, 59, and 103).
With respect to claim 4, Gelashvili teaches the convolutional neural network inference processing device according to claim 2, wherein: at least one processor and a memory corresponding to each of the plurality of convolution layers and a residual layer, are allocated to each of the plurality of convolution layers and the residual layer, and the at least one processor performs processing by each of the convolution layer and the residual layer using predetermined intermediate data stored in the memory and margin data stored in the memory (Gelashvili, paragraphs 76, 78, 88, and 135).
With respect to claim 5, Gelashvili teaches the convolutional neural network inference processing device according to claim 4, wherein the at least one processor is further connected to an external memory, and can select the external memory or the memory as an output destination of the processing result (Gelashvili, paragraphs 68, 72, 124-125, and 147).
With respect to claim 6, Gelashvili teaches the convolutional neural network inference processing device according to claim 1, wherein the memory combines inconsistency data related to an adjacent tile for which processing has been performed in the past and the intermediate data, and stores the combined data as the past layer data (Gelashvili, paragraphs 32, 38-40, 62, 68, 88 and 135).
With respect to claim 7, Gelashvili teaches the convolutional neural network inference processing device according to claim 1, wherein: the neural network includes, as an integration layer, a layer that performs a series of processing in the plurality of convolution layers, which are continuous, and in the residual layer, and the at least one processor performs processing, in an integration layer to which the residual layer belongs, of adding the past layer data generated using the intermediate data related to the integration layer to the processing result related to the integration layer (Gelashvili, paragraphs 36, 74-75, 135 and 145-146).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALICIA M WILLOUGHBY whose telephone number is (571)272-5599. The examiner can normally be reached 9-5:30, EST, M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ajay Bhatia can be reached at 571-272-3906. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALICIA M WILLOUGHBY/ Primary Examiner, Art Unit 2156
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