DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The finality of the office action mailed 02/05/2026 is withdrawn.
Response to Arguments
Applicant’s arguments, see Remarks, filed 01/14/2026, with respect to the rejection(s) of claim(s) 1-12 under Yoshizaki et al. have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yoshizaki et al., in view of Chuang et al. (US 11,469,369 B2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshizaki et al. (US 7,493,098 B2), in view of Chuang et al. (US 11,469,369 B2).
Regarding Claim 1, Yoshizaki et al. teaches in Figure 7 a drive circuit comprising:
a load resistor (RL);
a variable resistance element configured to have at least a first terminal and a second terminal (Q11, RE); and
a constant current source configured to determine a magnitude of a current flowing through the load resistor based on an input voltage and a resistance value of the variable resistance element (Q21),
wherein a voltage across the load resistor is output as an output voltage (Vout);
but does not explicitly teach
the variable resistance element configured to be capable of changing a resistance value based on a magnetoresistance effect.
Chuang et al. teaches in Figure 1B the variable resistance element (104) configured to be capable of changing a resistance value based on a magnetoresistance effect (Col. 4, lines 34-54: wherein the resistive state of 104 is based on a magnetoresistance ratio).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the magnetoresistance value teachings of Chuang et al. with the variable resistance element of Yoshizaki et al. for the purpose of increasing “the MR ratio of the MTJ memory element 104 while reducing the set voltage, and reducing power consumption of the MTJ memory element 104.” Chuang et al.: Col. 4, lines 51-54.
Regarding Claim 2, Yoshizaki et al. and Chuang et al., as a whole, teach all the limitations of the present invention, wherein Yoshizaki et al. further teaches the drive circuit, wherein the resistance value of the load resistor is able to be selected (based on input into Q11).
Regarding Claim 3, Yoshizaki et al. and Chuang et al., as a whole, teach all the limitations of the present invention, wherein Yoshizaki et al. further teaches the drive circuit, wherein the variable resistance element has a third terminal in addition to the first terminal and the second terminal (where Q11 has a third terminal in addition to the first terminal connected to Q21 and a second terminal connected to ground).
Regarding Claim 4, Yoshizaki et al. and Chuang et al., as a whole, teach all the limitations of the present invention, wherein Yoshizaki et al. further teaches the drive circuit, wherein the variable resistance element is a magnetic domain wall motion type (Q11, RE).
Regarding Claim 5, Yoshizaki et al. and Chuang et al., as a whole, teach all the limitations of the present invention, wherein Yoshizaki et al. further teaches the drive circuit wherein the resistance value of the variable resistance element changes in a case in which a voltage is applied between the second terminal and the third terminal (based on Vin signal), and
wherein the drive circuit further includes a resistance control circuit applying a voltage between the second terminal and the third terminal (circuit which generates Vin).
Regarding Claim 6, Yoshizaki et al. and Chuang et al., as a whole, teach all the limitations of the present invention, wherein Yoshizaki et al. further teaches the drive circuit, wherein a switching element is connected between at least one of the second terminal and the third terminal and the resistance control circuit (Q11).
Regarding Claim 7, Yoshizaki et al. and Chuang et al., as a whole, teach all the limitations of the present invention, wherein Yoshizaki et al. further teaches the drive circuit wherein one of two terminals included in the load resistor is connected to a constant voltage source (where RL connects to Q21), and
wherein the constant current source is a bipolar transistor including a base terminal to which the input voltage is applied, a collector terminal connected to the other of the two terminals included in the load resistor, and an emitter terminal connected to the first terminal of the variable resistance element (where Q21 is connected to an input voltage, RL, and Q11,RE, respectively).
Regarding Claim 8, Yoshizaki et al. and Chuang et al., as a whole, teach all the limitations of the present invention, wherein Yoshizaki et al. further teaches the drive circuit, wherein the variable resistance element and the bipolar transistor are stacked as an integrated circuit (where Q21, and Q11,RE are stacked).
Regarding Claim 9, Yoshizaki et al. and Chuang et al., as a whole, teach all the limitations of the present invention, wherein Yoshizaki et al. teaches an array circuit comprising:
a plurality of the drive circuits according to claim 1 (see claim 1),
wherein the plurality of the drive circuits share the load resistor and are connected in parallel (see Claim 6, where there are two drive circuits connected in parallel).
Regarding Claim 10, Yoshizaki et al. and Chuang et al., as a whole, teach all the limitations of the present invention, wherein Yoshizaki et al. further teaches the array circuit
wherein the load resistor shared in the plurality of the drive circuits and the constant current source of each of the plurality of the drive circuits are connected to each other through a current mirror (RL, which are connected to the same upper node and to each Q21 and Q24), and
wherein a ground electric potential of the input voltage and a ground electric potential of the output voltage are configured to be common (where nodes of the input voltage and the ground electric potential of the output voltage are to ground).
Regarding Claim 11, Yoshizaki et al. and Chuang et al., as a whole, teach all the limitations of the present invention, wherein Yoshizaki et al. further teaches the array circuit
wherein a current flow-in/out circuit that is able to perform at least one of causing a current to flow in the load resistor and causing a current to flow out from the load resistor is connected (using Vout).
Regarding Claim 12, Yoshizaki et al. and Chuang et al., as a whole, teach all the limitations of the present invention, wherein Yoshizaki et al. further teaches a neuromorphic device comprising the array circuit according to claim 9 (see rejection of Claim 9).
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Diana J Cheng whose telephone number is (571)270-1197. The examiner can normally be reached Monday - Friday 9 am - 5:30 pm ET.
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/DIANA J. CHENG/Primary Examiner, Art Unit 2849