Prosecution Insights
Last updated: May 29, 2026
Application No. 18/573,057

Display Panel and Display Apparatus

Non-Final OA §103
Filed
Dec 21, 2023
Priority
Apr 29, 2022 — CN 202210468937.6 +1 more
Examiner
SITTA, GRANT
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
BOE TECHNOLOGY GROUP CO., LTD.
OA Round
1 (Non-Final)
72%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 72% — above average
72%
Career Allowance Rate
674 granted / 934 resolved
+4.2% vs TC avg
Moderate +14% lift
Without
With
+13.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 0m
Avg Prosecution
23 currently pending
Career history
966
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
89.2%
+49.2% vs TC avg
§102
7.5%
-32.5% vs TC avg
§112
1.1%
-38.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 934 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-3 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over WO2021016946 Examiner is using Liu et al 20240194141 as an English translation in view of Chen et al 2023/0317000 hereinafter, Chen. In regards to claim 1, Liu teaches a display panel, comprising: a substrate (fig. 2 (100/10)); and PNG media_image1.png 536 534 media_image1.png Greyscale a plurality of first pixel units located on a side of the substrate and arranged in a plurality of rows and a plurality of columns; (fig. 5a (rows and columns of subpixels) PNG media_image2.png 472 678 media_image2.png Greyscale wherein a first pixel unit includes a plurality of sub-pixels (fig. 5a RGBs), a sub-pixel includes a pixel driving circuit and a light-emitting device; (fig. 3c 121 T1 driving transistor for 120b)) PNG media_image3.png 772 576 media_image3.png Greyscale the light-emitting device is located on a side of the pixel driving circuit away from the substrate and is electrically connected to the pixel driving circuit; (fig. 6b R, G, V top side) and fig. 2 (120)) PNG media_image4.png 480 516 media_image4.png Greyscale the pixel driving circuit includes a first reset transistor; (fig. 3a (129 at least T6 and T7)) PNG media_image5.png 778 598 media_image5.png Greyscale the plurality of sub-pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel;(fig. 3a-3c 121a, 121b, etc for each R, G, and B)) [0086] For example, as shown in FIGS. 3B and 3C, a pixel circuit 121a of the first sub-pixel G1 further includes a first parasitic circuit 125a, and a pixel circuit 121b of the second sub-pixel G2 further includes a second parasitic circuit 125b. For example, the first parasitic circuit 125a is electrically connected to a control terminal of a drive circuit 122a of the pixel circuit 121a of the first sub-pixel G1 and a first light-emitting voltage application electrode of a light-emitting element 120a of the first sub-pixel G1, and is configured to control a voltage of the control terminal of the drive circuit 122a of the pixel circuit 121a of the first sub-pixel G1 based on a voltage of the first light-emitting voltage application electrode of the light-emitting element 120a of the first sub-pixel G1. The second parasitic circuit 125b is electrically connected to a control terminal of a drive circuit of a pixel circuit 121b of the second sub-pixel G2 and a first light-emitting voltage application electrode of a light-emitting element 120b of the second sub-pixel G2, and is configured to control a voltage of the control terminal of the drive circuit 122b of the pixel circuit 121b of the second sub-pixel G2 based on a voltage of the first light-emitting voltage application electrode of the light-emitting element 120b of the second sub-pixel G2. an area of a light-emitting device of the first sub-pixel is greater than an area of a light-emitting device of the second sub-pixel and greater than an area of a light-emitting device of the third sub-pixel; and [218] (fig. 6a DE4 for B is larger than G1 and R)[248-252] PNG media_image6.png 596 626 media_image6.png Greyscale PNG media_image7.png 564 806 media_image7.png Greyscale Liu fails to teach an orthographic projection of at least one of a first reset transistor of the second sub-pixel or a first reset transistor of the third sub-pixel on the substrate is located within an orthographic projection of the light-emitting device of the first sub-pixel on the substrate. Examiner notes Liu teaches: [0136] For example, as shown in FIG. 6C, an orthographic projection of the first light-emitting voltage application electrode 1201a of the light-emitting element of the first sub-pixel G1 on the base substrate 10 at least partially overlaps with an orthographic projection of a control terminal 1221a of the drive circuit of the pixel circuit of the first sub-pixel G1 on the base substrate 10, and an orthographic projection of the first light-emitting voltage application electrode 1201b of the light-emitting element of the second sub-pixel G2 on the base substrate 10 at least partially overlaps with an orthographic projection of a control terminal 1221b of the drive circuit of the pixel circuit of the second sub-pixel G2 on the base substrate 10. Examiner notes Liu fails to teach the cited portions because the reset transistor is not shared amongst the sub-pixels which examiner understand to be the inventive concept. However, Chen teaches an orthographic projection of at least one of a first reset transistor of the second sub-pixel or a first reset transistor of the third sub-pixel on the substrate is located within an orthographic projection of the light-emitting device of the first sub-pixel on the substrate.[0067] (fig. 7a (744))(fig. 8a 540 and 716)). Examiner notes 780a sub-pixel with an orthographic projection over 744. PNG media_image8.png 344 358 media_image8.png Greyscale Embodiments relate to a display device with subpixels that share switch transistors that selectively connect sources of driving transistors to a high voltage source. Further, part of reset transistors or part of a select transistor may be shared across multiple subpixels. The reset transistor selectively connects an anode of an organic light emitting diode (OLED) to a low voltage source. The select transistor selectively passes through pixel data from a data line when a gate signal is received via a gate line. Driver transistors and capacitors of the subpixels are independent and not shared. In this way, the dimensions of the subpixels may be reduced and enable increase in the density of the pixels.(abstract) It would have been obvious to one of ordinary skill in the art to modify the teachings of Liu to further include an orthographic projection of at least one of a first reset transistor of the second sub-pixel or a first reset transistor of the third sub-pixel on the substrate is located within an orthographic projection of the light-emitting device of the first sub-pixel on the substrate as taught by Chen in order to further miniaturize display devices [002-003] In regards to claim 2, Liu in view of Chen teaches the display panel according to claim 1, wherein orthographic projections of the first reset transistor of the first sub-pixel, the first reset transistor of the second sub-pixel and the first reset transistor of the third sub-pixel on the substrate are all located within the orthographic projection of the light-emitting device of the first sub-pixel on the substrate (fig. 7a 742 and 744 shared amongst 4 sub-pixels Chen) in view of fig. 6c 1291b/1292b) Liu. In regards to claim 3, Liu in view of Chen teaches display panel according to claim 1, wherein at least two of the first reset transistor of the first sub-pixel, the first reset transistor of the second sub-pixel, and the first reset transistor of the third sub-pixel are a same transistor (fig. 7a same transistor 742 and 744 shared amongst 4 sub-pixels Chen). In regards to claim 17, Liu in view of Chen teaches (Currently Amended) the display panel according to claim Lany one of claims 16, wherein the light-emitting device includes an anode, a light-emitting layer and a cathode, the anode is electrically connected to the pixel driving circuit,(fig. 5b Ae Liu) the light-emitting layer is located on a side of the anode away from the substrate (fig. 6c Ae facing up away from substrate) Liu, and the cathode is located on a side of the anode away from the substrate (fig. 6c Ce) Liu; and the orthographic projection of the at least one of the first reset transistor of the second sub-pixel (fig. 7a same transistor 742 and 744 shared amongst 4 sub-pixels Chen) and/or the first reset transistor of the third sub-pixel on the substrate is located within an orthographic projection of an anode of the first sub-pixel on the substrate (fig. 7c 780C Chen in view of (1201)anode Rstld [139] Liu. In regards to claim 18, Liu in view of Chen teaches display panel according to claim 1, wherein the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, and the third sub-pixel is a blue sub-pixel (fig. 6a R, G1/G2 and B) Liu.. In regards to claim 19, Liu in view of Chen teaches display panel according to claim 1, comprising: a first display region and a second display region, the first display region being provided with the first pixel units; wherein the second display region is provided with a plurality of second pixel units, the plurality of second pixel units are arranged in a plurality of rows and a plurality of columns;(fig. 5a (11 for first row and second row) Liu a second pixel unit includes a plurality of sub-pixels, and density of sub-pixels in the first display region is equal to density of sub-pixels in the second display region; an area of a light-emitting device of a sub-pixel in the first display region is 0.4 to 0.6 times an area of a light-emitting device of a sub-pixel of a same color in the second display region.(fig. 1 403/404 is half, or .5, of 401 and 402) Liu. In regards to claim 20, Liu in view of Chen teaches display apparatus, comprising: the display panel according to claim 1 (fig. 1 (400) and fig. 2 (display)) Liu. Allowable Subject Matter Claims 4-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to GRANT SITTA whose telephone number is (571)270-1542. The examiner can normally be reached M-F 7:30-4:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Patrick Edouard can be reached at 571-272-6084. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /GRANT SITTA/Primary Examiner, Art Unit 2622
Read full office action

Prosecution Timeline

Dec 21, 2023
Application Filed
May 12, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
72%
Grant Probability
86%
With Interview (+13.6%)
3y 0m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 934 resolved cases by this examiner. Grant probability derived from career allowance rate.

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