Prosecution Insights
Last updated: April 19, 2026
Application No. 18/573,198

INFORMATION PROCESSING DEVICE AND METHOD

Non-Final OA §103§112
Filed
Dec 21, 2023
Examiner
WU, MING HAN
Art Unit
2618
Tech Center
2600 — Communications
Assignee
Sony Group Corporation
OA Round
1 (Non-Final)
76%
Grant Probability
Favorable
1-2
OA Rounds
2y 8m
To Grant
99%
With Interview

Examiner Intelligence

Grants 76% — above average
76%
Career Allow Rate
282 granted / 370 resolved
+14.2% vs TC avg
Strong +23% interview lift
Without
With
+23.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
35 currently pending
Career history
405
Total Applications
across all art units

Statute-Specific Performance

§101
7.8%
-32.2% vs TC avg
§103
68.3%
+28.3% vs TC avg
§102
2.1%
-37.9% vs TC avg
§112
12.6%
-27.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 370 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Response to Arguments Election without traverse: the applicant accepts the examiner’s restriction requirement. Claim Interpretation The following is a quotation of 35 U.S.C. 112(f): (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph: An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph: (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function. Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: a vertex connection information generation unit that deletes, an encoding unit that encodes, control unit that controls in the claim 1. Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. Dependent claims to the claim 1 are also interpreted under 35 U.S.C. 112 (f) interpretation due to the dependency to the claim 1 and similar reason above. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claims 1 recites the limitation "a vertex connection information generation unit…” The claim limitation invoking 35 USC 112(f) fails to disclose sufficient corresponding structure for performing the claimed function. To satisfy 112(f), the specification must disclose corresponding structure, which can be either (i) specific physical structure , or (ii) an algorithm implemented by a computer. Although the specification (i.e. page 110) describes the function of the “vertex connection information generation unit,” it does not disclose a corresponding algorithm that defines how the function is performed. Accordingly, the claim in indefinite under 35 USC 112(b). Dependent claims not mentioned specifically above inherit the deficiencies from the claims stated above on which they depend. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordiL624nary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1 – 16 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al. (Patent: US 9,749,609 B2 ) in view of Koo et al. (Publication: US 2020/0221130 A1). Regarding claim 1, Ahn discloses an information processing device comprising (column 9 lines 3 to 10 - computer-readable media including program instructions to implement various operations embodied by a computer. Program instructions include both machine code, such as produced by a compiler, and files containing higher level code stored in memory and executed by the processor inside the computer to perform the following: Computer contain a least one processor.): an information generation unit that deletes at least some of internal vertices which are vertices of a mesh representing an object having a three- dimensional structure and positioned other than a boundary of a patch of a geometry ( FIG. 3, Column 4 lines 59 to 65 - an apparatus for encoding a 3D mesh removes a front vertex 302 connected to both end vertices of a start gate 301 from among vertices configuring the start gate 301. Also, the apparatus for encoding the 3D mesh encodes connectivity information between a front vertex 302 prior to being removed and neighboring vertices following the front vertex 302 being removed. As shown in removed vertex 302, vertex 302 is an internal vertice, not on the boundry, and “positioned other than a boundary of a patch of a geometry”. See the following Figure 3 . Column 8 lines 9 to 15 - The vertex remover 605 removes a front vertex, “an information generation unit”. The vertex remover 605 generates a triangle by connecting a plurality of neighboring vertices connected to the front vertex. PNG media_image1.png 336 668 media_image1.png Greyscale ) and generates information indicating the vertices of the mesh and a connection between the vertices ( Column 4 lines 55 to 60 - FIG. 3 is a diagram illustrating a 3D mesh simplified by removing a front vertex and generating a triangle, updated information, “generate a information” . Column 2 lines 5 to 11 - The removing of the front vertex may include generating a triangle using the both end vertices configuring the gate and the front vertex, generating tag information associated with neighboring vertices of the front vertex, and updating valence information of the neighboring vertices of the front vertex, “generates information indicating…”. PNG media_image2.png 339 668 media_image2.png Greyscale ). Ahn does not however Koo discloses an encoding unit that encodes the vertex connection information ([0197] - the encoder “encoding unit” allocates, encodes, indexes for connection to (2.sup.n−1) vertexes for a 0-th vertex (in this case, as shown in Table 3, when None is allocated as index 0, the vertex may be expressed as a total of n bits) and allocates indexes for connection to (2.sup.n-1−1) vertexes for other vertexes, “vertex connection information”). a vertex connection information generation unit performs method ([0024] - the layer deriving unit “a vertex connection information generation unit” may divide vertexes of the plurality of rotation layers into sub groups, and the edge information may include connection information between the sub groups and connection information between vertexes in the sub group.); generates vertex connection information ([0211] - the encoder splits “generates” the first sub group into second sub groups including a plurality of vertexes. A connections between the second sub groups, vertices, may be determined.) Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Ahn with an encoding unit that encodes the vertex connection information; a vertex connection information generation unit performs method; generates vertex connection information as taught by Koo. The motivation for doing is to process content more efficiently. Regarding claim 2, Ahn in view of Koo disclose all the limitation of claim 1. Ahn discloses includes a boundary vertex list which is a list of boundary vertices which are vertices positioned at the boundary of the patch (column 4 lines 35 to 40 - configuring a patch, the tag information indicates whether a number of neighboring vertices connected to the boundary vertices is decreased, increased, or remains the same.). Regarding claim 3, Ahn in view of Koo disclose all the limitation of claim 2. Ahn discloses wherein the boundary vertex list includes an inclusive list in which a region surrounded by the boundary vertices forming the list and a connection between the boundary vertices is included in the patch (column 4 lines 60 to 66 - encodes information between a front vertex 302 prior to being removed and neighboring vertices following the front vertex 302 being removed, Fig. 3, thus As shown in the Fig. 3, the information indicated a list with neighboring vertices and connection between the vertices. PNG media_image3.png 268 434 media_image3.png Greyscale ). Regarding claim 4, Ahn in view of Koo disclose all the limitation of claim 3. Ahn discloses wherein the boundary vertex list includes an exclusive list in which the region surrounded by the boundary vertices forming the list and the connection between the boundary vertices is not included in the patch ( Column 5 lines 23 to 35 - the apparatus for encoding the 3D mesh updates valence information on the neighboring vertices of the front vertex removed when the triangle is generated. Column 4 lines 60 to 66 - configuring a patch, for encoding the 3D mesh encodes connectivity information between a front vertex 302 prior to being removed and neighboring vertices following the front vertex 302 being removed.). Regarding claim 5, Ahn in view of Koo disclose all the limitation of claim 2. Ahn discloses wherein the boundary vertex list includes identification information on the boundary vertices and position information on the boundary vertices in a geometry image on which the patch is arranged ( column 4 lines 35 to 40 - configuring a patch, the tag information indicates whether a number of neighboring vertices connected to the boundary vertices is decreased, increased, or remains the same.). Koo discloses information on the image which is a two-dimensional plane on which the patch is arranged ([0122] - In order to apply a non-separable transform, two-dimensional (or two-dimensional array) data blocks may be arranged in the form of a one-dimensional array. For example, blocks of a 4×4 size may be arranged in row-first lexicographic order, as shown in FIG. 4. Furthermore, the blocks may be arranged in column order within each row. Although not shown in FIG. 4, the blocks may be arranged in column-first order. However, the present disclosure is not limited thereto. The encoder/decoder may arrange two-dimensional blocks in the form of a one-dimensional array using various methods in addition to the lexicographic order.) Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify Ahn in view Koo with an encoding unit that encodes the vertex connection information; a vertex connection information generation unit performs method; generates vertex connection information as taught by Koo. The motivation for doing is to process content more efficiently. Regarding claim 6, Ahn in view of Koo disclose all the limitation of claim 2. Ahn discloses indicates the connection between the boundary vertices in an arrangement order of the boundary vertices ( In a subsequent step, Column 8 lines 9 to 15 - The vertex remover 605 removes a front vertex of the plurality of gates based on the determined priority, generates a triangle, and simplifies a 3D mesh. For example, the vertex remover 605 removes the front vertex in a sequential order from a higher priority. column 5 lines 50 to 55 - determining a priority of a gate configuring a 3D mesh based on valence information on boundary vertices, tag information on vertices configuring a patch, and a null patch; simplifying a 3D mesh by removing a vertex based on the priority of the gate.). Regarding claim 7, Ahn in view of Koo disclose all the limitation of claim 2. Ahn discloses wherein the vertex connection information further includes an internal vertex list which is a list of the internal vertices ( Column 2 lines 13 to 16 - The simplifying “removed the internal vertex” of the 3D mesh may include determining whether a patch associated with the gate and the front vertex is a null patch, and determining a priority of the gate associated with the patch determined to be the null patch to be lower than a priority of the gate associated with the patch “include internal vertex list which is a list of the internal vertices” determined not to be the null patch. Column 6 lines 31 to 35 - when the patch is determined to be the null-patch, a compression rate may be reduced because the front vertex is not removed, “not the internal vertex”.). Regarding claim 8, Ahn in view of Koo disclose all the limitation of claim 2. Ahn discloses includes pair information indicating a correspondence of the boundary vertices between the patches (referring to FIG. 4, Column 4 lines 40 to 45 - when a number of vertices connected to a boundary vertex subsequent to the generation of the triangle is increased or remains the same in comparison to a number of vertices connected to a boundary vertex prior to the generation of the triangle, the apparatus for encoding the 3D mesh generates tag information on a plus type 402. Conversely, when the number of vertices connected to the boundary vertex subsequent to the generation of the triangle is reduced in comparison to the number of vertices connected to the boundary vertex prior to the generation of the triangle, the apparatus for encoding the 3D mesh generates tag information on a minus type 401. The apparatus for encoding the 3D mesh updates the valence information to the number of vertices connected to the boundary vertex subsequent to the generation of the triangle. Column 6 lines 26 to 30 - when connectivity information on neighboring vertices adjacent to the front vertex of the gate is abnormal, the apparatus for encoding the 3D mesh determines the patch associated with the gate to be the null-patch. As such, Column 6 lines 31 to 35 - when the patch is determined to be the null-patch, a compression rate may be reduced because the front vertex is not removed, “between the patches ”. PNG media_image4.png 286 434 media_image4.png Greyscale ). Regarding claim 9, Ahn in view of Koo disclose all the limitation of claim 1. Ahn discloses generates a parameter to be used when the vertices and the connection are reconstructed (Column 8 lines 23 to 30 - the vertex remover 605 generates tag information on the plurality of neighboring vertices connected to the front vertex when the triangle is generated. In this example, the tag information includes a plus type or a minus type indicating whether a number of the plurality of neighboring vertices connected to a boundary vertex is decreased, increased, or remains the same. In addition, the vertex remover 605 updates the valence information on the plurality of neighboring vertices when the triangle is generated.). Regarding claim 10, Ahn in view of Koo disclose all the limitation of claim 9. Ahn discloses as the parameter, flag information indicating whether or not at least some of the internal vertices of the mesh have been deleted ( Column 8 lines 23 to 30 - the vertex remover 605 generates tag information on the plurality of neighboring vertices connected to the front vertex when the triangle is generated. In this example, the tag information includes a plus type or a minus type indicating whether a number of the plurality of neighboring vertices connected to a boundary vertex is decreased, increased, or remains the same. In addition, the vertex remover 605 updates the valence information on the plurality of neighboring vertices when the triangle is generated. Column 2 lines 13 to 16 - The simplifying “removed the internal vertex” of the 3D mesh may include determining whether a patch associated with the gate and the front vertex is a null patch, and determining a priority of the gate associated with the patch determined to be the null patch to be lower than a priority of the gate associated with the patch “some of the internal vertice” determined not to be the null patch. column 5 lines 50 to 55 - determining a priority of a gate configuring a 3D mesh based on valence information on boundary vertices, tag information on vertices configuring a patch, and a null patch; simplifying a 3D mesh by removing a vertex based on the priority of the gate;). Regarding claim 11, Ahn in view of Koo disclose all the limitation of claim 9. Ahn discloses generates, as the parameter, information regarding a density of the vertices upon reconstruction ( Column 8 lines 23 to 30 - the vertex remover 605 generates tag information on the plurality of neighboring vertices connected to the front vertex when the triangle is generated. In this example, the tag information includes a plus type or a minus type indicating whether a number of the plurality of neighboring vertices connected to a boundary vertex is decreased, increased, or remains the same. In addition, the vertex remover 605 updates the valence information on the plurality of neighboring vertices when the triangle is generated. As shown in Fig. 3, the density of the density of the mesh decrease. PNG media_image5.png 266 470 media_image5.png Greyscale ). Regarding claim 12, Ahn in view of Koo disclose all the limitation of claim 9. Ahn discloses as the parameter, flag information indicating whether to correct positions of the vertices to be reconstructed (Column 8 lines 23 to 30 - the vertex remover 605 generates tag information on the plurality of neighboring vertices connected to the front vertex when the triangle is generated. In this example, the tag information includes a plus type or a minus type indicating whether a number of the plurality of neighboring vertices connected to a boundary vertex is decreased, increased, or remains the same. In addition, the vertex remover 605 updates the valence information on the plurality of neighboring vertices when the triangle is generated. Column 2 lines 12 to 20 - The simplifying “removed the internal vertex, reconstructed” of the 3D mesh may include determining whether a patch associated with the gate and the front vertex is a null patch, and determining a priority of the gate associated with the patch determined to be the null patch to be lower than a priority of the gate associated with the patch “some of the internal vertice” determined not to be the null patch.). Regarding claim 13, Ahn in view of Koo disclose all the limitation of claim 9. Ahn discloses generates, as the parameter, information regarding a feature of a geometry targeted for correction of the vertices to be reconstructed (Column 8 lines 23 to 30 - the vertex remover 605 generates tag information on the plurality of neighboring vertices connected to the front vertex when the triangle is generated. In this example, the tag information includes a plus type or a minus type indicating whether a number of the plurality of neighboring vertices connected to a boundary vertex is decreased, increased, or remains the same. In addition, the vertex remover 605 updates the valence information on the plurality of neighboring vertices when the triangle is generated. Column 6 lines 33 to 40 - The simplifying “removed the internal vertex, target for correction, reconstructed” of the 3D mesh may include determining whether a patch associated with the gate and the front vertex is a null patch, and determining a priority of the gate associated with the patch determined to be the null patch to be lower than a priority of the gate associated with the patch “some of the internal vertice” determined not to be the null patch.). Regarding claim 14, Ahn in view of Koo disclose all the limitation of claim 9. Ahn discloses generates, as the parameter, information regarding a target search range of correction of the vertices to be reconstructed (Column 8 lines 23 to 30 - the vertex remover 605 generates tag information on the plurality of neighboring vertices connected to the front vertex when the triangle is generated. In this example, the tag information includes a plus type or a minus type indicating whether a number of the plurality of neighboring vertices connected to a boundary vertex is decreased, increased, or remains the same. In addition, the vertex remover 605 updates the valence information on the plurality of neighboring vertices when the triangle is generated. Column 6 lines 33 to 40 - The simplifying “removed the internal vertex, target for correction, reconstructed” of the 3D mesh may include determining whether a patch associated with the gate and the front vertex is a null patch, and determining a priority of the gate associated with the patch determined to be the null patch to be lower than a priority of the gate associated with the patch “some of the internal vertice” determined not to be the null patch.). Regarding claim 15, Ahn in view of Koo disclose all the limitation of claim 1. Ahn discloses determines whether to delete the internal vertices of the mesh, and in a case of determining to delete the internal vertices, ( Column 2 lines 13 to 16 - The simplifying “removed the internal vertex” of the 3D mesh may include determining whether a patch associated with the gate and the front vertex is a null patch, and determining a priority of the gate associated with the patch determined to be the null patch to be lower than a priority of the gate associated with the patch “include internal vertex list which is a list of the internal vertices” determined not to be the null patch. Column 6 lines 31 to 35 - when the patch is determined to be the null-patch, a compression rate may be reduced because the front vertex is not removed, “not the internal vertex”.) deletes at least some of the internal vertices of the mesh and generates the vertex connection information ( Column 6 lines 31 to 35 - when the patch is determined to be the null-patch, a compression rate may be reduced because the front vertex is not removed, “not the internal vertex”. with the triangle being generated, Column 5 lines 23 to 35 - the apparatus for encoding the 3D mesh updates valence information on the neighboring vertices of the front vertex removed when the triangle is generated. ). Regarding claim 16, see rejection on claim 1. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ming Wu whose telephone number is (571)270-0724. The examiner can normally be reached on Monday - Friday: 9:30am - 6:00pm EST . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Devona Faulk can be reached on 571-272-7515. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MING WU/ Primary Examiner, Art Unit 2618
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Prosecution Timeline

Dec 21, 2023
Application Filed
Mar 18, 2026
Non-Final Rejection — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
76%
Grant Probability
99%
With Interview (+23.3%)
2y 8m
Median Time to Grant
Low
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