Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
Claim 4 recites the limitation "the third shunt capacitive element" and “"the fourth shunt capacitive element". There is insufficient antecedent basis for this limitation in the claim. Note, “third and fourth shunt capacitive elements" are claimed in claim 2.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, and 5-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Srinidhi Embar et al. (20210391829), hereafter called SRINIDHI, in view of KRVAVAC (20090085667)
Regarding claim 1, SRINIDHI (Fig. 1) discloses a Doherty amplifier (100) comprising: an output terminal (190) connectable or connected to a load (106); a main/carrier transistor (136) having a first output capacitance (139); a peak transistor (156) having a second output capacitance (159), wherein the main transistor (139) and the peak transistor (156) each comprise a Gallium Nitride based high electron mobility transistor, see para. [0070]; a first shunt network (144) arranged in between an output of the main transistor (139) and ground, the first shunt network comprising a series connection of a first shunt inductor and a first shunt DC decoupling capacitor; a first series inductor (143) arranged in between the output of the main transistor (139) and a combining node (170), wherein the combining node (170) is electrically connected to the output terminal (190) either directly or indirectly via an impedance matching network (175, 176), and wherein the Doherty power amplifier is configured to combine signals amplified by the main transistor (139) and the peak transistor (156) at the combining node (170); a first shunt capacitive element (146) arranged in between the combining node (170) and ground; wherein an inductance of the first shunt network is configured such that the first shunt network resonates with a part of the first output capacitance (139) at a given frequency within an operational frequency band of the Doherty power amplifier, wherein a remaining part of the first output capacitance (139) forms, together with the first series inductor (143) and at least a part of the first shunt capacitive element (146), an impedance inverter at said given frequency; wherein the impedance inverter is a first lumped equivalent of a transmission line having an electrical length of substantially 90 degrees at said given frequency; the Doherty power amplifier further comprising: a second shunt network (163) arranged in between an output of the peak transistor (156) and ground, the second shunt network comprising a series connection of a second shunt inductor and a second shunt DC decoupling capacitor; a second series inductor (162) arranged in between the output of the peak transistor (156) and an intermediate node (164);
SRINIDHI, in view of KRVAVAC are analogous art because they are from the same field of endeavor, namely Doherty amplifier. Accordingly, it would have been obvious in view of the reference, taken as a whole, to have modified the circuit of SRINIDHI to have included a phase delay unit, as taught by KRVAVAC. Such a modification would have imparted the advantageous benefit of provided a high impedance to the output, see paras. [0015]-[0018] as taught by KRVAVAC, to SRINIDHI reference, thereby suggesting the obviousness of such a modification.
Regarding claim 3, wherein capacitor (*175) and inductor (176) can be configured as an impedance matching network, wherein the impedance matching network is configured to lower the impedance seen at the combining node (170) looking towards load (106).
Regarding claim 5, SRINIDHI (Fig. 1) discloses a first low-pass input impedance matching network (134) connected to an input of the main transistor (136) and a second low-pass input impedance matching network (154) connected to an input of the peak transistor (156).
Regarding claim 6, SRINIDHI (Fig. 1), wherein the first and second low-pass input impedance matching networks (134 and 154) each comprise one or more matching stages, each matching stage comprising a shunt inductor and a series inductor, see Fig. 2, matching networks (234 and 254).
Regarding claim 7, SRINIDHI (Fig. 1), further comprising: an input terminal (102); and a splitter (120) configured for splitting an RF signal received at the input terminal (102) into a first component to be fed to the main transistor (136) and a second component to be fed to the peak transistor (156).
Regarding claim 8, wherein the Doherty amplifier (100) is integrated in a PCB, see para. [0054] and [0059].
Regarding claims 8-19, the additional features of the subject-matter of claims 8 to 19 refer to the implementation details of how the components are physically implemented. These additional features are considered straightforward implementation details that the one of ordinary skilled in the art would choose in accordance with the circumstances, without having to invoke inventive skills.
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, prior art(s) does not disclose the phase delay unit comprises: a third series inductor arranged in between the intermediate node (N2) and the combining node (N1); a third shunt capacitive element (C7) arranged in between the combining node (N1) and ground; and a fourth shunt capacitive element (C8) arranged in between the intermediate node (N2) and ground.
Conclusion
The prior arts made of record and not relied upon is considered pertinent to applicant's disclosure.
Blednov (8,354,882) discloses similar structure as claimed. However, it lacks shunt capacitive elements (C5 and C6) as required by the claim.
Jang et al. (9,899,976) and Root (8,593,219) also lack shunt capacitive elements (C5 and C6) as required by the claim.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767. The examiner can normally be reached from 8:30 AM – 5:00 PM EST.
Examiner interviews are available via telephone and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, JESSICA HAN can be reached on (571) 272-2078. The fax phone numbers for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application lnformation Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/KHANH V NGUYEN/ Primary Examiner, Art Unit 2843
Prosecution Insights