DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The new title is acceptable and clearly indicates the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-6, 8-12 and 16-22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. US 2022/0165788 in view of Tian et al. CN 111863797.
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Lee et al. US 2022/0165788
Regarding claim 1, Lee et al. in Fig. 1H disclose a semiconductor light emitting device, comprising:
a light emitting structure (e.g. nanorod LED) [0066] having a first region and a second region along the major axis direction (annotated above);
an insulating layer 106 [0068] surrounding a side surface of the first region; and
a first electrode 112 [0099] surrounding a side surface of the second region and extending to cover an upper surface of the second region as a single continuous electrode structure,
wherein a thickness of the insulating layer 106 is the same as a thickness of the first electrode 112,
wherein the light emitting structure comprises:
a first conductivity type semiconductor layer 103 [0067];
an active layer 102 [0067] on the first conductivity type semiconductor layer 103; and
a second conductivity type semiconductor layer 101 [0067] on the active layer 102.
Lee et al. do not expressly disclose wherein the insulating layer comprises:
a first insulating layer surrounding a side surface of the first conductivity type semiconductor layer; and
a second insulating layer surrounding a side surface of the active layer.
Tian et al. in Fig. 1 and [0040]-[0086] teach a first insulating layer 302 surrounding a side surface of a first conductivity type semiconductor layer; and a second insulating layer 301 surrounding a side surface of a active layer. Tian et al. further teach that the insulating layers are formed to prevent the metal in subsequent process steps from adhering to the wall of the light emitting structure to generate short circuit.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Tian et al. in the device of Lee et al. to improve the device performance.
Regarding claim 3, Lee et al. in view of Tian et al. teach the semiconductor light emitting device of claim 1. Lee et al. in Fig. 1H (annotated above) teach wherein the first region comprises the first conductivity type semiconductor layer 103 and the active layer 102, and the second region comprises a first portion of the second conductivity type semiconductor layer 101.
Regarding claim 4, Lee et al. in view of Tian et al. teach the semiconductor light emitting device of claim 3. Lee et al. in Fig. 1H (annotated above) teach wherein the first region comprises a second portion part 110 of the second conductivity type semiconductor layer 101, the second portion being different from the first portion [0098].
Regarding claim 5, Lee et al. in view of Tian et al. teach the semiconductor light emitting device of claim 3. Lee et al. in Fig. 1H (annotated above) teach wherein the diameter of the first region is the same as the diameter of the second region.
Regarding claim 6, Lee et al. in view of Tian et al. teach the semiconductor light emitting device of claim 3. Lee et al. in Fig. 1H (annotated above) teach wherein the side surface of the first region and the side surface of the second region coincide along the major axis direction.
Regarding claim 8, Lee et al. in view of Tian et al. teach the semiconductor light emitting device of claim 1. Tian et al. do not expressly teach wherein a thickness of the first insulating layer is greater than a thickness of the second insulating layer.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Regarding claim 9, Lee et al. in view of Tian et al. teach the semiconductor light emitting device of claim 1. Tian et al. in Fig. 1 teach wherein the outer surface of the first insulating layer has a concave round shape.
Regarding claim 10, Lee et al. in view of Tian et al. teach the semiconductor light emitting device of claim 1. Tian et al. in Fig. 1 teach wherein a thickness of the first insulating layer is the thickest in a lower side of the first region.
Regarding claim 11, Lee et al. in view of Tian et al. teach the semiconductor light emitting device of claim 1. Lee et al. in Fig. 1H (annotated above) teach wherein the first electrode is not in contact with the active layer.
Regarding claim 12, Lee et al. in view of Tian et al. teach the semiconductor light emitting device of claim 1. Tian et al. in Fig. 1 teach wherein the first electrode and the insulating layer overlap each other along the major axis direction.
Regarding claim 16, Lee et al. in view of Tian et al. teach the semiconductor light emitting device of claim 1. Lee et al. in Fig. 1H (annotated above) teach the thickness of the first electrode 112 and a thickness of a second electrode 108 [0081] are different.
Regarding claim 17, Lee et al. in view of Tian et al. teach the semiconductor light emitting device of claim 16. Lee et al. do not expressly teach wherein the thickness of the first electrode on the side surface of the second region is greater than the thickness of the first electrode on the upper surface of the second region.
However, Lee et al. teach that the thickness of the conductor layers are controlled by the deposition time of the conductor. Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Regarding claim 18, Lee et al. in view of Tian et al. teach the semiconductor light emitting device of claim 1. Lee et al. in Fig. 1H (annotated above) teach the LED of claim 1 comprising: a second electrode 108 [0081] on a lower surface of the first region.
Regarding claim 19, Lee et al. in view of Tian et al. teach the semiconductor light emitting device of claim 1. Lee et al. in Fig. 1H (annotated above) wherein the light emitting structure has a cylindrical shape (e.g. nanorod).
Regarding claim 20, Lee et al. in Figs. 1H and 6 disclose a semiconductor light emitting device, comprising:
a substrate 610 [0184];
first and second assembling wirings on the substrate 610 [0184];
a plurality of semiconductor light emitting devices 613 [0184] disposed on the first and second assembling wirings to generate different color lights;
a first wiring electrode 611 [0184] on one side of each of the plurality of semiconductor light emitting devices; and
a second wiring electrode 612 [0184] on the other side of each of the plurality of semiconductor light emitting devices 613,
wherein the plurality of semiconductor light emitting devices 613 each comprises:
a light emitting structure (e.g. nanorod LED) [0066] having a first region and a second region along the major axis direction (annotated above);
an insulating layer 106 [0068] surrounding a side surface of the first region; and
a first electrode 112 [0099] surrounding a side surface of the second region and extending to cover an upper surface of the second region as a single continuous electrode structure,
wherein a thickness of the insulating layer 106 is the same as a thickness of the first electrode 112,
wherein the light emitting structure comprises:
a first conductivity type semiconductor layer 103 [0067];
an active layer 102 [0067] on the first conductivity type semiconductor layer 103; and
a second conductivity type semiconductor layer 101 [0067] on the active layer 102.
Lee et al. do not expressly disclose wherein the insulating layer comprises:
a first insulating layer surrounding a side surface of the first conductivity type semiconductor layer; and
a second insulating layer surrounding a side surface of the active layer.
Tian et al. in Fig. 1 and [0040]-[0086] teach a first insulating layer 302 surrounding a side surface of a first conductivity type semiconductor layer; and a second insulating layer 301 surrounding a side surface of an active layer. Tian et al. further teach that the insulating layers are formed to prevent the metal in subsequent process steps from adhering to the wall of the light emitting structure to generate short circuit.
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Tian et al. in the device of Lee et al. to improve the device performance.
Regarding claim 21, Lee et al. in view of Tian et al. teach the semiconductor light emitting device of claim 20. Tian et al. do not expressly teach wherein a thickness of the first insulating layer is greater than a thickness of the second insulating layer.
Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B).
Regarding claim 22, Lee et al. in view of Tian et al. teach the semiconductor light emitting device of claim 20. Tian et al. in Fig. 1 teach wherein a thickness of the first insulating layer is the thickest in a lower side of the first region.
Allowable Subject Matter
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art neither anticipates nor renders obvious, in the context of the claims, the first electrode and the insulating layer in contact along the perimeter of the light emitting structure (e.g. with the thicknesses the same).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM.
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/Sonya McCall-Shepard/ Primary Examiner, Art Unit 2898
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