DETAILED ACTION
This office action is responsive to communication filed on October 10, 2025.
Response to Arguments
Applicant's arguments filed October 10, 2025 have been fully considered but they are not persuasive.
Applicant argues, with respect to claim 1, that Sato does not describe a holding unit that is outside a pixel. In particular, Applicant asserts that the first holding unit (SH1, figure 1) of Sato is included in a pixel.
The Examiner respectfully disagrees. What constitutes a pixel is up for interpretation. For instance, claim 1 defines a pixel as including a conversion unit, a charge storage unit, a reset unit, a first amplification unit, a second amplification unit, a first capacitor, and a voltage control unit. Based upon this, the Examiner interprets a pixel to include a conversion unit, a charge storage unit, a reset unit, a first amplification unit, a second amplification unit, a first capacitor, and a voltage control unit. Sato teaches a pixel (see figure 1) including a conversion unit (photodiode, PD), a charge storage unit (floating diffusion capacitor, CFD), a reset unit (first reset transistor, M2), a first amplification unit (first amplification transistor, M4), a second amplification unit (second amplification transistor, M7), a first capacitor (clamp capacitor, CCL), and a voltage control unit (second reset transistor, M5, clamp voltage, VCL). Sato also teaches a holding unit (first holding unit, SH1, figure 1). The holding unit (SH1, see figure 1) is outside of the structure including the conversion unit (photodiode, PD), the charge storage unit (floating diffusion capacitor, CFD), the reset unit (first reset transistor, M2), the first amplification unit (first amplification transistor, M4), the second amplification unit (second amplification transistor, M7), the first capacitor (clamp capacitor, CCL), and the voltage control unit (second reset transistor, M5, clamp voltage, VCL). Therefore, the holding unit (SH1) of Sato is outside of the pixel.
As such, the rejection is maintained by the Examiner.
Claim Interpretation
This claim interpretation is based upon the amended claims filed October 10, 2025.
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“holding unit” in claims 1-12
“conversion unit” in claims 1-12
“reset unit” in claims 1-12
“first amplification unit” in claims 1-12
“second amplification unit” in claims 1-12
“voltage control unit” in claims 1-12
“feedback unit” in claim 6
“capacitance switching unit” in claim 12
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim limitations are interpreted under 35 USC 112(f) as follows:
The “holding unit” in claims 1-12 corresponds to a sample-and-hold circuit including a switch and a capacitor (see paragraph 0078-0080 of US 2014/0388814).
The “conversion unit” in claims 1-12 corresponds to a photodiode (see paragraph 0068 of US 2014/0388814).
The “reset unit” in claims 1-12 corresponds to a transistor (see paragraph 0070 of US 2014/0388814).
The “first amplification unit” in claims 1-12 corresponds to a transistor (see paragraph 0071 of US 2014/0388814).
The “second amplification unit” in claims 1-12 corresponds to a transistor (see paragraph 0074 of US 2014/0388814).
The “voltage control unit” in claims 1-12 corresponds to a voltage source and a voltage control transistor (see paragraph 0075 of US 2014/0388814).
The “feedback unit” in claim 6 corresponds to a switch (see paragraph 0209 of US 2024/0388814).
The “capacitance switching unit” in claim 12 corresponds to a transistor (see paragraph 0147 of US 2024/0388814).
Claim Rejections - 35 USC § 112
All rejections under 35 USC 112 are hereby removed in view of Applicant’s response.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 11 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sato (US 2016/0131772).
Consider claim 1, Sato teaches:
An imaging device (figure 2A) comprising:
a plurality of pixels (see figures 1 and 2A, paragraphs 0031 and 0032, below rationale); and
a holding unit (first holding unit, SH1) configured to hold a first pixel signal output from a first pixel (see figure 1) of the plurality of pixels (“The first holding unit SH1 is a sample-and-hold circuit including a first transfer transistor M8 and a first holding capacitor CS1. Specifically, the state (conductive state or non-conductive state) of the first transfer transistor M8 is switched by using a control signal TS1 to perform sampling and holding so that the first signal obtained by the amplification unit AP amplifying the charge converted by the conversion unit CP having the first sensitivity is transferred to and held in the first holding capacitor CS1.” paragraph 0027); wherein
the holding unit (first holding unit, SH1, paragraph 0027) is outside the plurality of pixels (Claim 1 defines a pixel as including a conversion unit, a charge storage unit, a reset unit, a first amplification unit, a second amplification unit, a first capacitor, and a voltage control unit. Based upon this, the Examiner interprets a pixel to include a conversion unit, a charge storage unit, a reset unit, a first amplification unit, a second amplification unit, a first capacitor, and a voltage control unit. Sato teaches a pixel (see figure 1) including a conversion unit (photodiode, PD), a charge storage unit (floating diffusion capacitor, CFD), a reset unit (first reset transistor, M2), a first amplification unit (first amplification transistor, M4), a second amplification unit (second amplification transistor, M7), a first capacitor (clamp capacitor, CCL), and a voltage control unit (second reset transistor, M5, clamp voltage, VCL). Sato also teaches a holding unit (first holding unit, SH1, figure 1). The holding unit (SH1, see figure 1) is outside of the structure including the conversion unit (photodiode, PD), the charge storage unit (floating diffusion capacitor, CFD), the reset unit (first reset transistor, M2), the first amplification unit (first amplification transistor, M4), the second amplification unit (second amplification transistor, M7), the first capacitor (clamp capacitor, CCL), and the voltage control unit (second reset transistor, M5, clamp voltage, VCL). Therefore, the holding unit (SH1) of Sato is outside of the plurality of pixels.); and
each pixel of the plurality of pixels (see figure 1) includes:
a conversion unit (photodiode, PD) configured to convert radiation or light into charges (see paragraph 0024);
a charge storage unit (floating diffusion capacitor, CFD) configured to store the charges (see paragraph 0024);
a reset unit (first reset transistor, M2) configured to reset the charges stored in the charge storage unit (see paragraph 0026, figure 1);
a first amplification unit (first amplification transistor, M4) configured to:
amplifies the first pixel signal to generate a first amplified signal, wherein the first pixel signal is amplified based on the stored charges (see paragraph 0025);
a second amplification unit (second amplification transistor, M7) configured to:
amplify the first amplified signal to generate a second amplified signal and output the second amplified signal to the holding unit (SH1, see paragraphs 0025 and 0027);
a first capacitor (clamp capacitor, CCL) connected between an output portion of the first amplification unit (M4) and an input portion of the second amplification unit (M7, see figure 1, paragraph 0025); and
a voltage control unit (second reset transistor, M5, clamp voltage, VCL) configured to control a first voltage at the input portion of the second amplification unit (M7, see paragraph 0026).
Consider claim 4, and as applied to claim 1 above, Sato further teaches an ADC (Analog to Digital Converter) (signal reading unit, 20, figures 2B and 3) configured to receive the second amplified signal held by the holding unit and convert the held second amplified signal into a digital signal (see paragraphs 0037 and 0038).
The Examiner notes that claim 11 is directed toward an apparatus (i.e. an imaging device). The recitation “in a period between a readout period in which a signal is read and a shutter period in which the first capacitor holds a voltage based on an operation of the reset unit and the first amplification unit, the reset unit is further configured to continue to reset the charges stored in the charge storage unit; and the voltage control unit is further configured to continue to control the first voltage at the input portion of the second amplification unit” corresponds to a method of operating the claimed apparatus and thus does not materially affect the structure of the apparatus. As detailed in MPEP 2114(II), the manner of operating a device does not differentiate an apparatus claim from the prior art. Specifically, MPEP 2114(II) stipulates that a claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Sato teaches all of the structural limitations of claim 11 and parent claim 1. Whether Sato teaches the claimed manner of operation associated with said structure is inconsequential, as claim 11 is directed toward an apparatus and not toward a method of operating the apparatus.
Consider claim 12, and as applied to claim 1 above, Sato further teaches that each pixel of the plurality of pixels (see figure 1) further includes: an additional capacitance unit (additional capacitor, CFD’) configured to add capacitance to the charge storage unit (see paragraph 0024); and a capacitance switching unit (transistor, M1) configured to switch the addition of capacitance by the additional capacitance unit (CFD’, see figure 1, paragraph 0024).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3 and 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Sato (US 2016/0131772) in view of Hiyama (US 2011/0013046).
Consider claim 3, and as applied to claim 1 above, Sato does not explicitly teach a vertical signal line connected between each of the pixels and the holding unit, wherein the holding unit holds the second amplified signal output from the first pixel via the vertical signal line.
Hiyama similarly teaches an imaging device (figures 1A and 1B) including a plurality of pixels (100) and a holding unit (input capacitor, 108) for receiving an analog pixel signal (see paragraph 0024).
However, Hiyama additionally teaches a vertical signal line (vertical output line, 106) connected between each of the pixels (i.e. pixels (100) of a column of pixels) and the holding unit (108, see figures 1A and 1B, paragraph 0024), wherein the holding unit (108) holds the signal output from the pixel (100) via the signal line (106, see paragraph 0024).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the imaging device taught by Sato include a vertical signal line and holding unit configured in the manner taught by Hiyama for the benefit of enabling accurate A/D conversion results to be obtained (Hiyama, paragraphs 0007 and 0008).
Consider claim 8, and as applied to claim 4 above, Sato does not explicitly teach that the holding unit and the ADC are shared by a plurality of pixels including a second pixel.
Hiyama similarly teaches an imaging device (figures 1A and 1B) including a plurality of pixels (100), a holding unit (input capacitor, 108) for receiving an analog pixel signal (see paragraph 0024), and an ADC (“an A/D conversion circuit including an integrator circuit 125 and a comparator 126” paragraph 0024).
However, Hiyama additionally teaches that the holding unit (108) and the ADC (125, 126) are shared by a plurality of pixels (100) including a second pixel (i.e. shared by a column of pixels (100), figures 1A and 1B, paragraph 0024).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the imaging device taught by Sato include an ADC and holding unit configured in the manner taught by Hiyama for the benefit of enabling accurate A/D conversion results to be obtained (Hiyama, paragraphs 0007 and 0008).
The Examiner notes that claim 8 is directed toward an apparatus (i.e. an imaging device). The recitation “in parallel with the conversion, prior to a reading operation a second pixel signal based on the charge converted by the conversion unit in a second pixel of the plurality of pixels, of the first pixel signal held by the holding unit into the digital signal; the voltage control unit is further configured to control the first voltage of the input portion of the second amplification unit, and the second amplification unit is further configured to output a second voltage signal corresponding to the first voltage” corresponds to a method of operating the claimed apparatus and thus does not materially affect the structure of the apparatus. As detailed in MPEP 2114(II), the manner of operating a device does not differentiate an apparatus claim from the prior art. Specifically, MPEP 2114(II) stipulates that a claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). The combination of Sato and Hiyama teaches all of the structural limitations of claim 8 and parent claims 1 and 4. Whether the combination of Sato and Hiyama teaches the claimed manner of operation associated with said structure is inconsequential, as claim 8 is directed toward an apparatus and not toward a method of operating the apparatus.
The Examiner notes that claim 9 is directed toward an apparatus (i.e. an imaging device). The recitation “the second pixel signal is read subsequent to the reading operation of the first pixel signal of the first pixel of the plurality of pixels” corresponds to a method of operating the claimed apparatus and thus does not materially affect the structure of the apparatus. As detailed in MPEP 2114(II), the manner of operating a device does not differentiate an apparatus claim from the prior art. Specifically, MPEP 2114(II) stipulates that a claim containing a "recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus" if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). The combination of Sato and Hiyama teaches all of the structural limitations of claim 9 and parent claims 1, 4 and 8. Whether the combination of Sato and Hiyama teaches the claimed manner of operation associated with said structure is inconsequential, as claim 9 is directed toward an apparatus and not toward a method of operating the apparatus.
Consider claim 10, and as applied to claim 1 above, Sato further teaches that the plurality of pixels (P) are arranged in a matrix (see figure 2A),
the imaging device further comprises a plurality of holding unit (SH1, see figures 1 and 2A), and the plurality of holding units includes the holding unit (SH1, see figure 1).
However, Sato does not explicitly teach that each of the plurality of holding units is configured to hold signal output from a set of pixels, of the plurality of pixels, included in one pixel column.
Hiyama similarly teaches an imaging device (figures 1A and 1B) including a plurality of pixels (100) and a holding unit (input capacitor, 108) for receiving an analog pixel signal (see paragraph 0024).
However, Hiyama additionally teaches that a plurality of the holding units (108) that hold signals output from each of the plurality of pixels (100) included in one pixel column in parallel are provided (see figures 1A and 1B, paragraph 0024).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the imaging device taught by Sato include a holding unit for each pixel column as taught by Hiyama for the benefit of enabling accurate A/D conversion results to be obtained (Hiyama, paragraphs 0007 and 0008).
Allowable Subject Matter
Claims 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Consider claim 5, the prior art of record does not teach nor reasonably suggest that the voltage control unit is further configured to control the first voltage of the input portion of the second amplification unit prior to a reading operation of the first pixel signal, the first voltage is controlled based on the charges converted by the conversion unit, the second amplification unit if further configured to output, prior to a reading operation of a second pixel signal of a second pixel of the plurality of pixels, a second voltage corresponding to the first voltage, and the held second amplified signal converted into the digital signal based on the second voltage, in combination with the other elements recited in parent claims 1 and 4.
Claims 6 and 7 contain allowable subject matter as depending from claim 5.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBERT H CUTLER whose telephone number is (571)270-1460. The examiner can normally be reached approximately Mon - Fri 8:00-4:30.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached at (571)272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637